Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	482	1			T439	1		T451	2		T829	4
all_values[1]	465	1			T486	2		T550	2		T451	4
all_values[2]	436	1			T486	1		T828	1		T545	1
all_values[3]	448	1			T451	9		T448	1		T829	3
all_values[4]	459	1			T486	2		T550	1		T451	5
all_values[5]	439	1			T87	1		T122	1		T486	1
all_values[6]	450	1			T87	1		T122	1		T828	1
all_values[7]	455	1			T486	1		T551	1		T451	3
all_values[8]	443	1			T122	1		T547	1		T545	1
all_values[9]	477	1			T122	1		T545	1		T451	3
all_values[10]	489	1			T122	1		T545	1		T451	4
all_values[11]	455	1			T486	1		T550	2		T451	1
all_values[12]	431	1			T451	5		T448	1		T829	6
all_values[13]	463	1			T87	1		T828	1		T550	1
all_values[14]	471	1			T87	1		T551	1		T451	2
all_values[15]	456	1			T486	1		T828	1		T551	1
all_values[16]	477	1			T122	1		T486	1		T550	1
all_values[17]	453	1			T122	1		T828	1		T551	1
all_values[18]	438	1			T122	1		T486	1		T470	1
all_values[19]	500	1			T87	1		T122	1		T486	1
all_values[20]	502	1			T685	1		T451	3		T829	4
all_values[21]	456	1			T547	1		T551	1		T550	2
all_values[22]	448	1			T87	1		T486	1		T551	2
all_values[23]	449	1			T122	1		T486	1		T451	5
all_values[24]	446	1			T87	1		T828	1		T547	2
all_values[25]	445	1			T122	2		T486	1		T547	1
all_values[26]	483	1			T87	1		T122	1		T470	1
all_values[27]	472	1			T122	1		T426	1		T550	1
all_values[28]	463	1			T87	1		T122	2		T486	1
all_values[29]	442	1			T122	1		T685	1		T451	2
all_values[30]	452	1			T122	2		T451	4		T448	1
all_values[31]	454	1			T122	1		T486	3		T545	1
all_values[32]	452	1			T451	4		T835	1		T829	4
all_values[33]	454	1			T550	1		T451	5		T829	4
all_values[34]	451	1			T122	1		T551	1		T426	1
all_values[35]	473	1			T87	1		T122	2		T685	1
all_values[36]	444	1			T87	1		T486	1		T451	3
all_values[37]	454	1			T828	1		T451	4		T448	2
all_values[38]	417	1			T122	1		T486	1		T439	1
all_values[39]	474	1			T486	1		T439	1		T451	3
all_values[40]	476	1			T122	1		T547	1		T451	1
all_values[41]	469	1			T828	1		T551	1		T439	1
all_values[42]	457	1			T87	1		T828	1		T551	1
all_values[43]	462	1			T122	1		T551	1		T550	1
all_values[44]	488	1			T87	1		T486	2		T439	1
all_values[45]	430	1			T122	1		T547	1		T426	1
all_values[46]	444	1			T122	2		T685	1		T545	1
all_values[47]	453	1			T547	1		T451	5		T829	1
all_values[48]	442	1			T486	2		T451	2		T829	5
all_values[49]	470	1			T470	1		T550	1		T451	3