Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3389	1			T122	2		T486	5		T427	4
all_values[1]	3243	1			T122	5		T486	7		T427	6
all_values[2]	3314	1			T122	1		T486	5		T427	7
all_values[3]	3351	1			T122	2		T486	1		T427	6
all_values[4]	3401	1			T122	3		T486	8		T427	2
all_values[5]	3373	1			T122	4		T486	4		T427	13
all_values[6]	3272	1			T486	8		T427	5		T470	3
all_values[7]	3222	1			T486	8		T427	2		T470	3
all_values[8]	3201	1			T122	1		T486	7		T427	5
all_values[9]	3444	1			T486	7		T427	7		T470	2
all_values[10]	3292	1			T122	5		T486	6		T427	4
all_values[11]	3352	1			T122	4		T486	10		T427	4
all_values[12]	3269	1			T122	1		T486	5		T427	9
all_values[13]	3306	1			T122	3		T486	4		T427	9
all_values[14]	3238	1			T122	1		T486	10		T427	2
all_values[15]	3312	1			T122	1		T486	3		T427	4
all_values[16]	3226	1			T122	3		T486	5		T427	4
all_values[17]	3285	1			T122	4		T486	2		T427	8
all_values[18]	3301	1			T122	3		T486	9		T427	5
all_values[19]	3251	1			T122	1		T486	11		T427	7
all_values[20]	3344	1			T122	3		T486	3		T427	4
all_values[21]	3288	1			T122	4		T486	3		T427	5
all_values[22]	3347	1			T122	3		T486	9		T427	3
all_values[23]	3350	1			T486	3		T427	6		T426	3
all_values[24]	3295	1			T122	2		T486	4		T427	2
all_values[25]	3175	1			T122	2		T486	4		T427	4
all_values[26]	3310	1			T486	7		T427	6		T426	4
all_values[27]	3235	1			T486	4		T427	7		T470	2
all_values[28]	3304	1			T122	3		T486	6		T427	4
all_values[29]	3186	1			T122	2		T486	10		T427	4
all_values[30]	3331	1			T122	3		T486	5		T427	4
all_values[31]	3221	1			T486	7		T427	7		T470	3
all_values[32]	3300	1			T122	1		T486	2		T427	10
all_values[33]	3230	1			T486	4		T427	5		T470	2
all_values[34]	3290	1			T122	2		T486	7		T427	7
all_values[35]	3375	1			T122	4		T486	6		T427	4
all_values[36]	3166	1			T122	1		T486	8		T427	6
all_values[37]	3287	1			T122	2		T486	6		T427	9
all_values[38]	3314	1			T122	2		T486	2		T427	7
all_values[39]	3275	1			T122	6		T486	4		T427	5
all_values[40]	3191	1			T486	3		T427	9		T470	1
all_values[41]	3223	1			T122	2		T486	6		T427	11
all_values[42]	3312	1			T122	1		T486	7		T427	7
all_values[43]	3378	1			T122	2		T486	7		T427	7
all_values[44]	3304	1			T122	1		T486	7		T427	7
all_values[45]	3319	1			T122	1		T486	8		T427	2
all_values[46]	3282	1			T122	2		T486	6		T427	3
all_values[47]	3345	1			T486	7		T427	6		T470	2
all_values[48]	3225	1			T122	1		T486	5		T427	7
all_values[49]	3272	1			T122	2		T486	5		T427	6
all_values[50]	3298	1			T122	1		T486	4		T427	7
all_values[51]	3288	1			T122	3		T486	3		T427	4
all_values[52]	3338	1			T122	2		T486	5		T427	7
all_values[53]	3276	1			T122	1		T486	7		T427	6
all_values[54]	3253	1			T486	8		T427	6		T470	2
all_values[55]	3315	1			T122	2		T486	3		T427	3
all_values[56]	3334	1			T486	10		T427	5		T470	2
all_values[57]	3353	1			T122	2		T486	6		T427	8
all_values[58]	3402	1			T122	3		T486	3		T427	4
all_values[59]	3222	1			T122	3		T486	4		T427	5
all_values[60]	3316	1			T122	1		T486	5		T427	6
all_values[61]	3294	1			T122	3		T486	3		T427	9
all_values[62]	3264	1			T122	1		T486	7		T427	1
all_values[63]	3272	1			T122	1		T486	8		T427	5