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 LINE       16856
 SUB-EXPRESSION (addr_hit[45] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T36,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[46] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T36,T322
1	1	Covered	T552,T555,T554

 LINE       16856
 SUB-EXPRESSION (addr_hit[47] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T36,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[48] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T36,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[49] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T36,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[50] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T36,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[51] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T36,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[52] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T36,T322
1	1	Covered	T552,T555,T554

 LINE       16856
 SUB-EXPRESSION (addr_hit[53] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T36,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[54] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T36,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[55] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T36,T322
1	1	Covered	T552,T555,T554

 LINE       16856
 SUB-EXPRESSION (addr_hit[56] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T36,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[57] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T36,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[58] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T36,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[59] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T36,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[60] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T36,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[61] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T36,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[62] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T36,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[63] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T36,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[64] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T36,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[65] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T36,T322
1	1	Covered	T552,T555,T554

 LINE       16856
 SUB-EXPRESSION (addr_hit[66] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T36,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[67] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T36,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[68] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T36,T322
1	1	Covered	T552,T555,T554

 LINE       16856
 SUB-EXPRESSION (addr_hit[69] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T24,T321,T36
1	1	Covered	T552,T555,T554

 LINE       16856
 SUB-EXPRESSION (addr_hit[70] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[71] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[72] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T24,T321,T25
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[73] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T24,T321,T25
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[74] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[75] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[76] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[77] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T211,T321,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[78] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T211,T321,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[79] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[80] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T211,T321,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[81] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T211,T321,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[82] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T211,T321,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[83] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T211,T321,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[84] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T211,T321,T322
1	1	Covered	T552,T555,T554

 LINE       16856
 SUB-EXPRESSION (addr_hit[85] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T555,T554

 LINE       16856
 SUB-EXPRESSION (addr_hit[86] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T211,T321,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[87] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[88] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[89] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[90] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[91] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[92] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T327
1	1	Covered	T552,T555,T554

 LINE       16856
 SUB-EXPRESSION (addr_hit[93] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T327
1	1	Covered	T552,T555,T554

 LINE       16856
 SUB-EXPRESSION (addr_hit[94] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[95] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T327
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[96] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T327
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[97] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T327
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[98] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T327
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[99] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T327
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[100] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T555,T554

 LINE       16856
 SUB-EXPRESSION (addr_hit[101] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T327
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[102] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T555,T554

 LINE       16856
 SUB-EXPRESSION (addr_hit[103] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[104] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[105] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[106] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[107] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T215,T103,T321
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[108] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T215,T103,T321
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[109] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T555,T554

 LINE       16856
 SUB-EXPRESSION (addr_hit[110] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T215,T103,T321
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[111] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T215,T103,T321
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[112] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T215,T103,T321
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[113] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T215,T103,T321
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[114] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T215,T103,T321
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[115] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[116] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T215,T103,T321
1	1	Covered	T552,T555,T554

 LINE       16856
 SUB-EXPRESSION (addr_hit[117] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[118] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[119] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[120] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[121] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[122] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T5,T214,T321
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[123] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T5,T214,T321
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[124] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[125] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[126] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[127] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T4,T42,T74
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[128] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T4,T42,T74
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[129] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T4,T42,T74
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[130] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T4,T42,T74
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[131] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T24,T321,T25
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[132] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T24,T321,T25
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[133] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T555,T554

 LINE       16856
 SUB-EXPRESSION (addr_hit[134] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T555,T554

 LINE       16856
 SUB-EXPRESSION (addr_hit[135] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T555,T554

 LINE       16856
 SUB-EXPRESSION (addr_hit[136] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[137] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[138] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[139] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T555,T554

 LINE       16856
 SUB-EXPRESSION (addr_hit[140] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[141] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T555,T554

 LINE       16856
 SUB-EXPRESSION (addr_hit[142] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[143] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[144] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[145] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T555,T554

 LINE       16856
 SUB-EXPRESSION (addr_hit[146] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[147] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T555,T554

 LINE       16856
 SUB-EXPRESSION (addr_hit[148] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[149] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[150] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[151] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[152] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[153] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T17,T95,T70
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[154] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[155] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T71,T321,T322
1	1	Covered	T552,T555,T554

 LINE       16856
 SUB-EXPRESSION (addr_hit[156] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T4,T95,T42
1	1	Covered	T552,T555,T554

 LINE       16856
 SUB-EXPRESSION (addr_hit[157] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T4,T42,T74
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[158] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T140,T362
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[159] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[160] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T351
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[161] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T351
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[162] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T351
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[163] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T351
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[164] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T351
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[165] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[166] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T297,T349,T350
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[167] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T297,T349,T350
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[168] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[169] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[170] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[171] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[172] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T121,T101,T149
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[173] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[174] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T555,T554

 LINE       16856
 SUB-EXPRESSION (addr_hit[175] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T120,T321,T322
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[176] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[177] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T555,T554

 LINE       16856
 SUB-EXPRESSION (addr_hit[178] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[179] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[180] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[181] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T321,T322,T154
1	1	Covered	T552,T553,T555

 LINE       16856
 SUB-EXPRESSION (addr_hit[182] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T17
1	0	Covered	T120,T321,T322
1	1	Covered	T552,T553,T555