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LINE 36651
EXPRESSION (addr_hit[552] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T552,T553,T555 |
| 1 | 1 | 1 | Covered | T412,T7,T8 |
LINE 36653
EXPRESSION (addr_hit[553] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T552,T554,T507 |
| 1 | 1 | 1 | Covered | T448,T380,T468 |
LINE 36655
EXPRESSION (addr_hit[554] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T535,T552,T555 |
| 1 | 1 | 1 | Covered | T448,T429,T380 |
LINE 36657
EXPRESSION (addr_hit[555] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T552,T553,T489 |
| 1 | 1 | 1 | Covered | T469,T380,T143 |
LINE 36659
EXPRESSION (addr_hit[556] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T439,T429,T493 |
| 1 | 1 | 1 | Covered | T439,T380,T143 |
LINE 36661
EXPRESSION (addr_hit[557] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T559,T578,T564 |
| 1 | 1 | 1 | Covered | T427,T470,T380 |
LINE 36663
EXPRESSION (addr_hit[558] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T552,T555,T584 |
| 1 | 1 | 1 | Covered | T448,T380,T143 |
LINE 36665
EXPRESSION (addr_hit[559] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T552,T553,T429 |
| 1 | 1 | 1 | Covered | T3,T13,T14 |
LINE 36668
EXPRESSION (addr_hit[560] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T552,T554,T558 |
| 1 | 1 | 1 | Covered | T544,T448,T428 |
LINE 36671
EXPRESSION (addr_hit[561] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T525,T558,T562 |
| 1 | 1 | 1 | Covered | T449,T380,T488 |
LINE 36674
EXPRESSION (addr_hit[562] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T552,T555,T492 |
| 1 | 1 | 1 | Covered | T9,T439,T448 |
LINE 36677
EXPRESSION (addr_hit[563] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T489,T661,T558 |
| 1 | 1 | 1 | Covered | T380,T488,T383 |
LINE 36680
EXPRESSION (addr_hit[564] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T552,T554,T585 |
| 1 | 1 | 1 | Covered | T1,T2,T15 |
LINE 36683
EXPRESSION (addr_hit[565] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T559,T561,T662 |
| 1 | 1 | 1 | Covered | T486,T380,T143 |
LINE 36686
EXPRESSION (addr_hit[566] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T553,T554,T588 |
| 1 | 1 | 1 | Covered | T11,T12,T380 |
LINE 36689
EXPRESSION (addr_hit[567] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T552,T554,T528 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 40162
EXPRESSION (reg_busy_sel | shadow_busy)
------1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T1,T2,T3 |