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Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1



Summary for Variable cp_rsp_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_rsp_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 200 1 T649 1 T515 1 T637 1
small_delay 973 1 T79 1 T673 1 T82 1
zero 627 1 T78 1 T80 1 T516 1


Summary for Variable cp_req_dly

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_req_dly

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
big_delay 500 1 T673 1 T435 1 T513 1
small_delay 673 1 T79 1 T82 1 T436 1
zero 627 1 T78 1 T80 1 T516 1

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