Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.22	95.64	94.14	95.45		95.00	97.53	99.54

Total tests in report: 2933

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
38.92	38.92	45.69	45.69	44.87	44.87	25.12	25.12			58.75	58.75	58.92	58.92	0.19	0.19	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2831518867
52.02	13.10	61.72	16.03	60.03	15.15	30.38	5.26			74.08	15.33	85.14	26.22	0.80	0.61	/workspace/coverage/default/2.chip_jtag_csr_rw.2996199254
58.07	6.05	69.77	8.06	62.21	2.18	32.11	1.73			74.12	0.04	85.14	0.00	25.09	24.29	/workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.840774918
63.14	5.07	73.32	3.54	67.10	4.89	48.51	16.41			78.82	4.71	85.31	0.17	25.79	0.70	/workspace/coverage/default/1.chip_jtag_csr_rw.193785690
66.57	3.42	79.11	5.80	71.40	4.31	52.41	3.90			80.82	2.00	89.86	4.55	25.79	0.00	/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2955668359
69.88	3.31	79.11	0.00	71.70	0.30	52.41	0.00			80.82	0.00	89.86	0.00	45.35	19.56	/workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.2075117814
72.34	2.47	79.23	0.12	73.22	1.52	54.80	2.39			80.99	0.17	89.86	0.00	55.96	10.61	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.2844693471
74.66	2.32	84.18	4.94	75.90	2.69	57.23	2.43			84.84	3.85	89.86	0.00	55.96	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.2703188406
76.72	2.06	85.43	1.26	76.78	0.88	65.61	8.38			85.97	1.14	90.38	0.52	56.13	0.16	/workspace/coverage/default/9.chip_sw_all_escalation_resets.1676665700
78.71	2.00	85.43	0.00	76.78	0.00	65.61	0.00			85.97	0.00	90.38	0.00	68.11	11.98	/workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.3931969466
80.28	1.56	85.51	0.08	76.79	0.01	74.71	9.10			85.98	0.01	90.56	0.17	68.11	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2010120132
81.61	1.33	85.51	0.00	76.94	0.14	74.71	0.00			86.00	0.02	90.56	0.00	75.94	7.83	/workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.3722173308
82.90	1.29	87.81	2.30	79.05	2.12	75.54	0.84			88.50	2.51	90.56	0.00	75.94	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.2394889772
84.19	1.29	89.39	1.58	81.89	2.84	75.84	0.30			91.16	2.66	90.91	0.35	75.94	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.4150628251
85.23	1.05	89.39	0.00	81.89	0.00	82.11	6.27			91.16	0.00	90.91	0.00	75.94	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1133354988
86.22	0.99	89.39	0.00	82.08	0.19	82.11	0.00			91.16	0.00	90.91	0.00	81.67	5.73	/workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.3224057528
87.14	0.92	90.59	1.20	82.82	0.74	84.70	2.59			91.82	0.66	91.26	0.35	81.67	0.00	/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.1647759148
87.96	0.82	90.66	0.07	83.35	0.53	85.42	0.71			91.87	0.05	91.26	0.00	85.22	3.55	/workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.2143053286
88.69	0.73	91.22	0.56	85.69	2.34	85.95	0.53			92.15	0.28	91.26	0.00	85.89	0.67	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1149343475
89.40	0.71	91.38	0.16	85.80	0.12	85.96	0.01			92.26	0.11	95.10	3.85	85.89	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3231717771
90.03	0.63	91.38	0.00	85.90	0.10	85.96	0.00			92.26	0.00	95.10	0.00	89.57	3.68	/workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.3088651568
90.54	0.52	91.38	0.00	85.90	0.00	85.96	0.00			92.26	0.00	95.10	0.00	92.66	3.09	/workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.3316030001
91.01	0.47	92.21	0.83	86.74	0.84	86.39	0.43			92.96	0.70	95.10	0.00	92.66	0.00	/workspace/coverage/default/1.chip_sw_gpio_smoketest.3844256228
91.47	0.46	92.21	0.00	86.76	0.02	87.90	1.51			92.96	0.00	95.10	0.00	93.89	1.23	/workspace/coverage/default/0.chip_sw_alert_test.4217928256
91.81	0.33	92.22	0.01	88.40	1.64	87.90	0.00			92.96	0.00	95.10	0.00	94.25	0.36	/workspace/coverage/cover_reg_top/12.chip_tl_errors.949457680
92.12	0.32	92.45	0.23	88.65	0.25	89.07	1.16			93.23	0.27	95.10	0.00	94.25	0.00	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1371497929
92.44	0.31	93.34	0.89	88.85	0.20	89.40	0.34			93.32	0.10	95.45	0.35	94.25	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.570798011
92.74	0.31	93.34	0.00	88.92	0.07	89.40	0.00			93.32	0.00	95.45	0.00	96.02	1.76	/workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.3704743303
92.97	0.23	93.55	0.20	89.09	0.17	89.74	0.34			93.44	0.12	95.98	0.52	96.02	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1021910471
93.19	0.22	93.94	0.39	89.52	0.43	89.82	0.08			93.86	0.41	95.98	0.00	96.02	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.2666708442
93.36	0.17	94.07	0.13	90.31	0.79	89.86	0.04			93.87	0.02	95.98	0.00	96.05	0.04	/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2461638455
93.51	0.15	94.07	0.00	90.32	0.01	89.86	0.00			93.87	0.00	95.98	0.00	96.95	0.89	/workspace/coverage/cover_reg_top/65.xbar_random_large_delays.1215718592
93.66	0.15	94.07	0.00	90.32	0.00	90.74	0.88			93.87	0.00	95.98	0.00	96.95	0.00	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3719531505
93.78	0.12	94.07	0.00	90.32	0.00	91.46	0.72			93.87	0.00	95.98	0.00	96.95	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1006496627
93.89	0.12	94.07	0.00	90.32	0.00	92.12	0.66			93.87	0.00	95.98	0.00	96.99	0.05	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.535451589
94.01	0.11	94.26	0.19	90.62	0.30	92.33	0.21			93.87	0.00	95.98	0.00	96.99	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4166384050
94.12	0.11	94.26	0.00	90.93	0.31	92.33	0.00			94.23	0.36	95.98	0.00	96.99	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3456028284
94.23	0.11	94.26	0.00	90.93	0.00	92.33	0.00			94.23	0.00	95.98	0.00	97.65	0.66	/workspace/coverage/cover_reg_top/3.xbar_access_same_device.2974656695
94.34	0.11	94.33	0.07	90.98	0.05	92.45	0.13			94.28	0.05	96.33	0.35	97.65	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.4280600246
94.43	0.10	94.33	0.00	91.13	0.15	92.45	0.00			94.31	0.03	96.33	0.00	98.06	0.41	/workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.725383084
94.52	0.09	94.33	0.00	91.13	0.00	92.98	0.53			94.31	0.00	96.33	0.00	98.06	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2963203847
94.61	0.09	94.33	0.00	91.60	0.47	92.98	0.00			94.31	0.00	96.33	0.00	98.11	0.05	/workspace/coverage/cover_reg_top/3.chip_tl_errors.3485787954
94.68	0.07	94.33	0.00	91.60	0.00	93.40	0.42			94.31	0.00	96.33	0.00	98.11	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.2534338279
94.74	0.06	94.33	0.00	91.77	0.17	93.40	0.00			94.33	0.02	96.33	0.00	98.31	0.20	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.3943139326
94.80	0.06	94.42	0.09	91.87	0.10	93.44	0.04			94.44	0.11	96.33	0.00	98.32	0.01	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1735559129
94.86	0.06	94.42	0.00	91.87	0.00	93.78	0.34			94.44	0.00	96.33	0.00	98.32	0.00	/workspace/coverage/default/0.chip_sw_edn_auto_mode.2853960540
94.91	0.05	94.42	0.00	92.01	0.14	93.79	0.01			94.60	0.16	96.33	0.00	98.32	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1731317403
94.96	0.05	94.42	0.01	92.03	0.02	93.90	0.11			94.60	0.00	96.50	0.17	98.32	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1253685975
95.01	0.05	94.47	0.04	92.06	0.03	93.91	0.02			94.62	0.02	96.68	0.17	98.33	0.01	/workspace/coverage/default/92.chip_sw_all_escalation_resets.2495248028
95.06	0.05	94.47	0.00	92.34	0.29	93.91	0.00			94.62	0.00	96.68	0.00	98.33	0.00	/workspace/coverage/cover_reg_top/20.chip_tl_errors.1165773495
95.10	0.05	94.52	0.05	92.48	0.14	93.91	0.00			94.70	0.08	96.68	0.00	98.33	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.1636978129
95.15	0.04	94.55	0.03	92.51	0.02	93.92	0.01			94.73	0.02	96.85	0.17	98.33	0.00	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1950063685
95.19	0.04	94.57	0.02	92.52	0.01	93.93	0.01			94.73	0.01	97.03	0.17	98.34	0.01	/workspace/coverage/default/55.chip_sw_all_escalation_resets.172690914
95.23	0.04	94.58	0.01	92.53	0.01	93.93	0.00			94.76	0.02	97.20	0.17	98.36	0.01	/workspace/coverage/default/36.chip_sw_all_escalation_resets.2046180197
95.26	0.04	94.58	0.01	92.54	0.01	93.93	0.00			94.77	0.01	97.38	0.17	98.37	0.01	/workspace/coverage/default/40.chip_sw_all_escalation_resets.1287713160
95.30	0.04	94.58	0.00	92.54	0.00	93.97	0.04			94.77	0.00	97.55	0.17	98.37	0.00	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.2335403531
95.33	0.03	94.58	0.00	92.54	0.00	94.17	0.21			94.77	0.00	97.55	0.00	98.37	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2144433557
95.36	0.03	94.58	0.00	92.74	0.19	94.17	0.00			94.77	0.00	97.55	0.00	98.37	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.1474303307
95.39	0.03	94.58	0.00	92.74	0.01	94.36	0.18			94.77	0.00	97.55	0.00	98.37	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1651062961
95.42	0.03	94.58	0.00	92.74	0.01	94.49	0.13			94.77	0.00	97.55	0.00	98.41	0.05	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.4188718094
95.45	0.03	94.58	0.00	92.75	0.01	94.67	0.18			94.77	0.00	97.55	0.00	98.41	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1489633459
95.48	0.03	94.58	0.00	92.92	0.18	94.67	0.00			94.77	0.00	97.55	0.00	98.41	0.00	/workspace/coverage/cover_reg_top/8.chip_tl_errors.165270283
95.51	0.03	94.66	0.07	92.92	0.00	94.76	0.09			94.77	0.01	97.55	0.00	98.41	0.00	/workspace/coverage/default/2.chip_tap_straps_testunlock0.78606434
95.54	0.03	94.71	0.06	92.96	0.04	94.80	0.04			94.80	0.02	97.55	0.00	98.41	0.00	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.246933204
95.56	0.02	94.71	0.00	93.06	0.10	94.80	0.00			94.83	0.03	97.55	0.00	98.41	0.00	/workspace/coverage/cover_reg_top/22.xbar_stress_all.3676118912
95.58	0.02	94.76	0.04	93.11	0.05	94.80	0.01			94.86	0.02	97.55	0.00	98.41	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1027169927
95.60	0.02	94.81	0.06	93.16	0.05	94.80	0.00			94.87	0.02	97.55	0.00	98.41	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.4132969165
95.62	0.02	94.81	0.00	93.16	0.00	94.91	0.11			94.87	0.00	97.55	0.00	98.41	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.899520784
95.64	0.02	94.81	0.00	93.26	0.10	94.91	0.00			94.87	0.00	97.55	0.00	98.41	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.2781151327
95.65	0.02	94.81	0.00	93.36	0.10	94.91	0.01			94.87	0.00	97.55	0.00	98.41	0.00	/workspace/coverage/cover_reg_top/15.chip_csr_rw.4100517180
95.67	0.02	94.81	0.00	93.37	0.01	94.91	0.00			94.87	0.00	97.55	0.00	98.51	0.09	/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.391184219
95.69	0.02	94.86	0.04	93.38	0.01	94.92	0.01			94.90	0.03	97.55	0.00	98.51	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2560807029
95.70	0.02	94.90	0.04	93.40	0.01	94.93	0.01			94.94	0.03	97.55	0.00	98.51	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.63471884
95.72	0.01	94.90	0.00	93.40	0.00	94.93	0.00			94.94	0.00	97.55	0.00	98.59	0.08	/workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.1326626956
95.73	0.01	94.92	0.01	93.42	0.03	94.95	0.02			94.95	0.02	97.55	0.00	98.59	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2292276480
95.74	0.01	94.92	0.00	93.51	0.08	94.95	0.00			94.95	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/cover_reg_top/22.chip_tl_errors.1782922517
95.76	0.01	94.92	0.01	93.53	0.02	95.00	0.05			94.95	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.252696908
95.77	0.01	94.92	0.00	93.60	0.07	95.00	0.00			94.95	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.24712671
95.78	0.01	94.95	0.03	93.63	0.02	95.00	0.00			94.96	0.01	97.55	0.00	98.59	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.306767550
95.79	0.01	94.95	0.00	93.64	0.01	95.00	0.00			94.96	0.00	97.55	0.00	98.64	0.05	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.3426829918
95.80	0.01	94.98	0.02	93.66	0.02	95.01	0.01			94.96	0.00	97.55	0.00	98.64	0.00	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1571638118
95.81	0.01	95.00	0.02	93.66	0.01	95.01	0.01			94.98	0.02	97.55	0.00	98.64	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.350081639
95.82	0.01	95.00	0.00	93.71	0.05	95.01	0.00			94.98	0.00	97.55	0.00	98.64	0.00	/workspace/coverage/cover_reg_top/28.chip_tl_errors.48291190
95.82	0.01	95.00	0.00	93.76	0.05	95.01	0.00			94.98	0.00	97.55	0.00	98.64	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.1801915809
95.83	0.01	95.00	0.00	93.76	0.00	95.06	0.04			94.98	0.00	97.55	0.00	98.64	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1217497123
95.84	0.01	95.00	0.00	93.76	0.00	95.10	0.04			94.98	0.00	97.55	0.00	98.64	0.00	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3509225880
95.85	0.01	95.00	0.00	93.78	0.02	95.10	0.00			94.98	0.00	97.55	0.00	98.66	0.02	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.301878510
95.85	0.01	95.00	0.00	93.78	0.00	95.14	0.04			94.98	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1108649523
95.86	0.01	95.00	0.00	93.78	0.00	95.17	0.04			94.98	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.2140583191
95.86	0.01	95.00	0.00	93.78	0.00	95.17	0.00			94.98	0.00	97.55	0.00	98.70	0.04	/workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.2932350302
95.87	0.01	95.00	0.00	93.80	0.02	95.18	0.01			94.99	0.01	97.55	0.00	98.70	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1417297277
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96.08	0.01	95.04	0.00	94.02	0.00	95.37	0.00			94.99	0.00	97.55	0.00	99.49	0.01	/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1638535154
96.08	0.01	95.04	0.00	94.02	0.00	95.37	0.00			94.99	0.00	97.55	0.00	99.51	0.01	/workspace/coverage/default/76.chip_sw_all_escalation_resets.3782351796
96.08	0.01	95.04	0.00	94.02	0.00	95.37	0.00			94.99	0.00	97.55	0.00	99.52	0.01	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3477432309
96.08	0.01	95.04	0.00	94.02	0.00	95.37	0.00			94.99	0.00	97.55	0.00	99.53	0.01	/workspace/coverage/default/86.chip_sw_all_escalation_resets.1241243006
96.08	0.01	95.04	0.00	94.02	0.00	95.37	0.00			94.99	0.00	97.55	0.00	99.54	0.01	/workspace/coverage/default/97.chip_sw_all_escalation_resets.3117047033
96.09	0.01	95.04	0.00	94.02	0.01	95.37	0.00			94.99	0.01	97.55	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.2555548549
96.09	0.01	95.04	0.00	94.04	0.01	95.37	0.00			94.99	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.537600888
96.09	0.01	95.04	0.00	94.05	0.01	95.37	0.00			94.99	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/29.xbar_random_large_delays.3348999264
96.09	0.01	95.04	0.00	94.06	0.01	95.37	0.00			94.99	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3000045326
96.09	0.01	95.04	0.00	94.07	0.01	95.37	0.00			94.99	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_gpio.3604034983
96.10	0.01	95.04	0.01	94.07	0.00	95.37	0.01			94.99	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/11.chip_sw_all_escalation_resets.2214051533
96.10	0.01	95.05	0.01	94.07	0.00	95.37	0.00			94.99	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.1407518772
96.10	0.01	95.05	0.00	94.07	0.00	95.38	0.01			94.99	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1718283709
96.10	0.01	95.05	0.00	94.07	0.01	95.39	0.01			94.99	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2768872750
96.10	0.01	95.05	0.00	94.07	0.00	95.39	0.00			95.00	0.01	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1531884420
96.10	0.01	95.05	0.00	94.08	0.01	95.39	0.00			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/13.chip_tl_errors.3629030541
96.10	0.01	95.05	0.00	94.08	0.01	95.39	0.00			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.1180219013
96.10	0.01	95.05	0.00	94.09	0.01	95.39	0.00			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/9.chip_tl_errors.227452261
96.11	0.01	95.05	0.00	94.10	0.01	95.39	0.00			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.4271157523
96.11	0.01	95.05	0.00	94.11	0.01	95.39	0.00			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.66898813
96.11	0.01	95.05	0.00	94.11	0.01	95.39	0.00			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.1550573287
96.11	0.01	95.05	0.00	94.12	0.01	95.39	0.00			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.694891445
96.11	0.01	95.05	0.00	94.12	0.00	95.39	0.01			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3228129407
96.11	0.01	95.05	0.00	94.12	0.00	95.40	0.01			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1440156149
96.11	0.01	95.05	0.00	94.12	0.00	95.41	0.01			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3212245544
96.11	0.01	95.06	0.01	94.12	0.01	95.41	0.00			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.219130874
96.12	0.01	95.06	0.01	94.12	0.00	95.41	0.00			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2584345088
96.12	0.01	95.06	0.00	94.12	0.00	95.41	0.01			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.557827127
96.12	0.01	95.06	0.00	94.12	0.00	95.42	0.01			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc.3660047498
96.12	0.01	95.06	0.00	94.12	0.00	95.42	0.01			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.111740561
96.12	0.01	95.06	0.00	94.12	0.00	95.43	0.01			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.3283032586
96.12	0.01	95.06	0.00	94.12	0.00	95.43	0.01			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2632247462
96.12	0.01	95.06	0.00	94.13	0.01	95.43	0.00			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.838941395
96.12	0.01	95.06	0.00	94.13	0.01	95.43	0.00			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.1604677463
96.12	0.01	95.06	0.00	94.13	0.01	95.43	0.00			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.2311022641
96.12	0.01	95.06	0.00	94.14	0.01	95.43	0.00			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.30249227
96.12	0.01	95.06	0.00	94.14	0.01	95.43	0.00			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.1014245438
96.12	0.01	95.06	0.00	94.14	0.01	95.43	0.00			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2525522830
96.12	0.01	95.06	0.00	94.14	0.00	95.43	0.01			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.3126999829
96.12	0.01	95.06	0.00	94.14	0.00	95.44	0.01			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.783097191
96.12	0.01	95.06	0.00	94.14	0.00	95.44	0.01			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.543687286
96.12	0.01	95.06	0.00	94.14	0.00	95.44	0.01			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1790964883
96.12	0.01	95.06	0.00	94.14	0.00	95.44	0.01			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.4027926968
96.13	0.01	95.06	0.00	94.14	0.00	95.45	0.01			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.25765026
96.13	0.01	95.06	0.00	94.14	0.00	95.45	0.01			95.00	0.00	97.55	0.00	99.54	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2450086437

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3393311420
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.1110033340
/workspace/coverage/cover_reg_top/0.chip_csr_rw.2360345043
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.499130483
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2798657824
/workspace/coverage/cover_reg_top/0.chip_tl_errors.4179263654
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2501574215
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.219251835
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3658860575
/workspace/coverage/cover_reg_top/0.xbar_error_random.1052238214
/workspace/coverage/cover_reg_top/0.xbar_random.4269911526
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2605364515
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1612286530
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2065469493
/workspace/coverage/cover_reg_top/0.xbar_same_source.3893525036
/workspace/coverage/cover_reg_top/0.xbar_smoke.938070031
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.699288339
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3586884623
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3014547372
/workspace/coverage/cover_reg_top/0.xbar_stress_all.3091467100
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2027069465
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2353942254
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2517963243
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.814971493
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.4276160822
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.4174657298
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.154527164
/workspace/coverage/cover_reg_top/1.chip_csr_rw.4024678160
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2190360261
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3171513922
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.2326260587
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1369056287
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3083687808
/workspace/coverage/cover_reg_top/1.xbar_error_random.3105589113
/workspace/coverage/cover_reg_top/1.xbar_random.1781842815
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.1450301916
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.2559885176
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.571848800
/workspace/coverage/cover_reg_top/1.xbar_same_source.4134475551
/workspace/coverage/cover_reg_top/1.xbar_smoke.963703232
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3828644371
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2301794985
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.467447312
/workspace/coverage/cover_reg_top/1.xbar_stress_all.2250212895
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1623269992
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2365172233
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3073792576
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1816412718
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.736561215
/workspace/coverage/cover_reg_top/10.chip_csr_rw.3935653532
/workspace/coverage/cover_reg_top/10.chip_tl_errors.4213686969
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.3005027615
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1360270885
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.944794667
/workspace/coverage/cover_reg_top/10.xbar_error_random.1473300411
/workspace/coverage/cover_reg_top/10.xbar_random.2135990983
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2586259574
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3555076525
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.410628188
/workspace/coverage/cover_reg_top/10.xbar_same_source.2145151423
/workspace/coverage/cover_reg_top/10.xbar_smoke.1020576470
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.1333469711
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1206733130
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3514345313
/workspace/coverage/cover_reg_top/10.xbar_stress_all.1491896534
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2779940211
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1068655679
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.983251596
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1199084616
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.515110754
/workspace/coverage/cover_reg_top/11.chip_csr_rw.1492562961
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.4183535645
/workspace/coverage/cover_reg_top/11.chip_tl_errors.316389105
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2579858394
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1168755469
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2902070654
/workspace/coverage/cover_reg_top/11.xbar_error_random.4265812259
/workspace/coverage/cover_reg_top/11.xbar_random.426357804
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1646212096
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3810303289
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1990463570
/workspace/coverage/cover_reg_top/11.xbar_same_source.2749416721
/workspace/coverage/cover_reg_top/11.xbar_smoke.2849880234
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.4269326119
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2206200760
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.136309485
/workspace/coverage/cover_reg_top/11.xbar_stress_all.2586778906
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2082909191
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.247672409
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.323669609
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.710343299
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.3893073818
/workspace/coverage/cover_reg_top/12.chip_csr_rw.2671081573
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.80176737
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.2684908263
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1544653279
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1358234619
/workspace/coverage/cover_reg_top/12.xbar_error_random.197129433
/workspace/coverage/cover_reg_top/12.xbar_random.281804656
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1152957356
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.250157353
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1023024462
/workspace/coverage/cover_reg_top/12.xbar_same_source.1615671179
/workspace/coverage/cover_reg_top/12.xbar_smoke.1319442772
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.300533027
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.4239061423
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.740762572
/workspace/coverage/cover_reg_top/12.xbar_stress_all.1954389978
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.3946624663
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3237996005
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.338187137
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.3475995781
/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.247771163
/workspace/coverage/cover_reg_top/13.chip_csr_rw.3328072335
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3576714519
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.2801420575
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2465675667
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.491581839
/workspace/coverage/cover_reg_top/13.xbar_error_random.2564889937
/workspace/coverage/cover_reg_top/13.xbar_random.2135820807
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.3386654217
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3922478035
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.2465788450
/workspace/coverage/cover_reg_top/13.xbar_same_source.146240118
/workspace/coverage/cover_reg_top/13.xbar_smoke.6572370
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3193528974
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1692562100
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.4147061561
/workspace/coverage/cover_reg_top/13.xbar_stress_all.1256753947
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.660412163
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3446400738
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.2645955311
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.1244285747
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/workspace/coverage/default/2.chip_sw_rv_timer_irq.3891080705
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/workspace/coverage/default/2.chip_sw_spi_device_pass_through.3826424456
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/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2982671008
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/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2326710262
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/workspace/coverage/default/23.chip_sw_all_escalation_resets.4255460620
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/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1883426914
/workspace/coverage/default/29.chip_sw_all_escalation_resets.3942215962
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/workspace/coverage/default/3.chip_tap_straps_testunlock0.3458703794
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3824120796
/workspace/coverage/default/31.chip_sw_all_escalation_resets.683687087
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3882060045
/workspace/coverage/default/32.chip_sw_all_escalation_resets.4121598240
/workspace/coverage/default/33.chip_sw_all_escalation_resets.2214503265
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.4174435795
/workspace/coverage/default/34.chip_sw_all_escalation_resets.558300983
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.897431572
/workspace/coverage/default/35.chip_sw_all_escalation_resets.900515315
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3488460572
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1900221720
/workspace/coverage/default/38.chip_sw_all_escalation_resets.1194847635
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3390313288
/workspace/coverage/default/4.chip_sw_all_escalation_resets.3060567954
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3805796937
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.782841082
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1389942785
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2895462349
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.4108408154
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2193631278
/workspace/coverage/default/4.chip_sw_uart_tx_rx.3441326591
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2061369545
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2434226210
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.948410924
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2259053256
/workspace/coverage/default/4.chip_tap_straps_dev.1996331520
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/workspace/coverage/default/4.chip_tap_straps_rma.1751501418
/workspace/coverage/default/4.chip_tap_straps_testunlock0.1021744722
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1128428624
/workspace/coverage/default/41.chip_sw_all_escalation_resets.3195783238
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2652333725
/workspace/coverage/default/42.chip_sw_all_escalation_resets.3069687778
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1792321018
/workspace/coverage/default/46.chip_sw_all_escalation_resets.2659690610
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1488506366
/workspace/coverage/default/47.chip_sw_all_escalation_resets.4056611085
/workspace/coverage/default/49.chip_sw_all_escalation_resets.2268522406
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2648117273
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.2217599648
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2269809334
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3456931065
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2814813238
/workspace/coverage/default/50.chip_sw_all_escalation_resets.3928620154
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3968532217
/workspace/coverage/default/51.chip_sw_all_escalation_resets.2701735271
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.469116144
/workspace/coverage/default/52.chip_sw_all_escalation_resets.2376547950
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1385464658
/workspace/coverage/default/53.chip_sw_all_escalation_resets.1449615243
/workspace/coverage/default/54.chip_sw_all_escalation_resets.1491341322
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3767037304
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3980474605
/workspace/coverage/default/57.chip_sw_all_escalation_resets.2789333375
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1899037196
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3258237340
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.970613186
/workspace/coverage/default/6.chip_sw_all_escalation_resets.748893341
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2045682210
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.722112655
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.252597430
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.703805439
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2544396327
/workspace/coverage/default/62.chip_sw_all_escalation_resets.3551308271
/workspace/coverage/default/63.chip_sw_all_escalation_resets.2149628940
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3512346888
/workspace/coverage/default/64.chip_sw_all_escalation_resets.39399326
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2358642634
/workspace/coverage/default/65.chip_sw_all_escalation_resets.444356264
/workspace/coverage/default/66.chip_sw_all_escalation_resets.1090316805
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2793914490
/workspace/coverage/default/67.chip_sw_all_escalation_resets.22171177
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1885570786
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.597223816
/workspace/coverage/default/69.chip_sw_all_escalation_resets.96027142
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.48695055
/workspace/coverage/default/7.chip_sw_all_escalation_resets.4159856538
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.4258492561
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3871274456
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.4110532539
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1170641091
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.183836791
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3761026370
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.148927748
/workspace/coverage/default/72.chip_sw_all_escalation_resets.3892186828
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1129170128
/workspace/coverage/default/73.chip_sw_all_escalation_resets.138027148
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1346682635
/workspace/coverage/default/75.chip_sw_all_escalation_resets.910775976
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.211109778
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2007700103
/workspace/coverage/default/77.chip_sw_all_escalation_resets.2242376493
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2921003554
/workspace/coverage/default/78.chip_sw_all_escalation_resets.2328833658
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2922834424
/workspace/coverage/default/79.chip_sw_all_escalation_resets.1603442284
/workspace/coverage/default/8.chip_sw_all_escalation_resets.3220343183
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.54999920
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1118661345
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3840779511
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3879776297
/workspace/coverage/default/80.chip_sw_all_escalation_resets.2185118211
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.362575971
/workspace/coverage/default/81.chip_sw_all_escalation_resets.468442869
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3810498131
/workspace/coverage/default/82.chip_sw_all_escalation_resets.1022015259
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2642273155
/workspace/coverage/default/83.chip_sw_all_escalation_resets.2173195935
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.102752439
/workspace/coverage/default/84.chip_sw_all_escalation_resets.111424467
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1118597556
/workspace/coverage/default/85.chip_sw_all_escalation_resets.818485321
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.561580241
/workspace/coverage/default/87.chip_sw_all_escalation_resets.2063905654
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3948774874
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.382096201
/workspace/coverage/default/89.chip_sw_all_escalation_resets.802591433
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1154061986
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3357613113
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1053662264
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3583140024
/workspace/coverage/default/90.chip_sw_all_escalation_resets.1675182610
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2767760704
/workspace/coverage/default/93.chip_sw_all_escalation_resets.3573935386
/workspace/coverage/default/94.chip_sw_all_escalation_resets.281624966
/workspace/coverage/default/95.chip_sw_all_escalation_resets.911317377
/workspace/coverage/default/96.chip_sw_all_escalation_resets.436460914
/workspace/coverage/default/98.chip_sw_all_escalation_resets.2156205804
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2845378857
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.19873334
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2720837933
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.306987825
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1777625099
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3661763974
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.4068086002
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.294737391
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3664400033

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Total test records in report: 2933

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2831518867			Jul 16 08:58:17 PM PDT 24	Jul 16 09:02:51 PM PDT 24	4253986226 ps
T5	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3003042999			Jul 16 08:31:47 PM PDT 24	Jul 16 08:43:12 PM PDT 24	4254946921 ps
T6	/workspace/coverage/default/0.chip_sw_aes_smoketest.3301973627			Jul 16 08:33:05 PM PDT 24	Jul 16 08:38:32 PM PDT 24	3357072648 ps
T30	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.4280600246			Jul 16 08:36:06 PM PDT 24	Jul 16 09:02:28 PM PDT 24	21953509140 ps
T15	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.573717893			Jul 16 08:57:44 PM PDT 24	Jul 16 09:03:49 PM PDT 24	3293961480 ps
T87	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.826651917			Jul 16 08:49:15 PM PDT 24	Jul 16 08:54:16 PM PDT 24	3030808720 ps
T88	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2302498688			Jul 16 08:45:27 PM PDT 24	Jul 16 08:49:54 PM PDT 24	2774264806 ps
T28	/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3990625781			Jul 16 08:55:28 PM PDT 24	Jul 16 09:02:27 PM PDT 24	6423067140 ps
T89	/workspace/coverage/default/0.chip_sw_power_idle_load.3414019351			Jul 16 08:28:00 PM PDT 24	Jul 16 08:41:30 PM PDT 24	4718306520 ps
T55	/workspace/coverage/default/0.rom_e2e_static_critical.1894208940			Jul 16 08:37:26 PM PDT 24	Jul 16 09:44:40 PM PDT 24	16957740178 ps
T60	/workspace/coverage/default/0.chip_sw_alert_test.4217928256			Jul 16 08:29:31 PM PDT 24	Jul 16 08:35:06 PM PDT 24	2716885520 ps
T110	/workspace/coverage/default/2.chip_sw_aes_masking_off.2739193976			Jul 16 08:44:49 PM PDT 24	Jul 16 08:51:19 PM PDT 24	3183475526 ps
T1	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1021910471			Jul 16 08:29:50 PM PDT 24	Jul 16 08:58:09 PM PDT 24	25022581716 ps
T41	/workspace/coverage/default/9.chip_sw_all_escalation_resets.1676665700			Jul 16 08:55:00 PM PDT 24	Jul 16 09:06:05 PM PDT 24	5975688148 ps
T104	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.141319533			Jul 16 08:35:17 PM PDT 24	Jul 16 08:43:49 PM PDT 24	4902810766 ps
T22	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.570798011			Jul 16 08:28:17 PM PDT 24	Jul 16 08:39:18 PM PDT 24	5552659520 ps
T42	/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1422156404			Jul 16 08:33:35 PM PDT 24	Jul 16 08:43:06 PM PDT 24	4057823425 ps
T56	/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.1647759148			Jul 16 08:53:34 PM PDT 24	Jul 16 09:48:27 PM PDT 24	15272628328 ps
T105	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.246933204			Jul 16 08:52:30 PM PDT 24	Jul 16 09:01:20 PM PDT 24	5105412370 ps
T106	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2268755480			Jul 16 08:36:42 PM PDT 24	Jul 16 10:14:52 PM PDT 24	24850337448 ps
T66	/workspace/coverage/default/92.chip_sw_all_escalation_resets.2495248028			Jul 16 09:02:44 PM PDT 24	Jul 16 09:12:57 PM PDT 24	4804806576 ps
T2	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.306767550			Jul 16 08:40:53 PM PDT 24	Jul 16 08:44:51 PM PDT 24	3216473008 ps
T67	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.2254413756			Jul 16 08:33:08 PM PDT 24	Jul 16 08:42:29 PM PDT 24	4325549410 ps
T121	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4166384050			Jul 16 08:47:21 PM PDT 24	Jul 16 08:56:43 PM PDT 24	5914331772 ps
T113	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3719531505			Jul 16 08:45:38 PM PDT 24	Jul 16 09:03:55 PM PDT 24	5974076335 ps
T248	/workspace/coverage/default/2.chip_sw_rv_timer_irq.3891080705			Jul 16 08:43:23 PM PDT 24	Jul 16 08:47:38 PM PDT 24	3439183776 ps
T284	/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.3536362425			Jul 16 08:28:19 PM PDT 24	Jul 16 08:52:27 PM PDT 24	7343014190 ps
T251	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1443827668			Jul 16 08:40:00 PM PDT 24	Jul 16 08:46:18 PM PDT 24	3885868380 ps
T285	/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1835343992			Jul 16 08:31:29 PM PDT 24	Jul 16 08:35:22 PM PDT 24	3008533914 ps
T142	/workspace/coverage/default/2.chip_sw_power_idle_load.2473266638			Jul 16 08:47:34 PM PDT 24	Jul 16 08:59:00 PM PDT 24	4314539780 ps
T107	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1371497929			Jul 16 08:40:21 PM PDT 24	Jul 16 09:29:32 PM PDT 24	21355893964 ps
T286	/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2676945567			Jul 16 08:30:41 PM PDT 24	Jul 16 08:39:12 PM PDT 24	5878997032 ps
T165	/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1540524654			Jul 16 08:29:08 PM PDT 24	Jul 16 08:38:28 PM PDT 24	5255319456 ps
T16	/workspace/coverage/default/1.chip_jtag_mem_access.740010609			Jul 16 08:29:37 PM PDT 24	Jul 16 08:56:03 PM PDT 24	13790640200 ps
T249	/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3988866175			Jul 16 08:50:29 PM PDT 24	Jul 16 08:54:45 PM PDT 24	2664176520 ps
T509	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1129114081			Jul 16 08:56:58 PM PDT 24	Jul 16 09:05:06 PM PDT 24	3751349376 ps
T57	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3845603684			Jul 16 08:45:19 PM PDT 24	Jul 16 10:19:25 PM PDT 24	15522277980 ps
T211	/workspace/coverage/default/0.chip_sw_pattgen_ios.3072774830			Jul 16 08:28:39 PM PDT 24	Jul 16 08:33:59 PM PDT 24	3048081640 ps
T118	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.3075817476			Jul 16 08:35:27 PM PDT 24	Jul 16 08:57:50 PM PDT 24	6301344788 ps
T23	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.3826424456			Jul 16 08:42:39 PM PDT 24	Jul 16 08:56:22 PM PDT 24	6958637550 ps
T879	/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.359728730			Jul 16 08:40:45 PM PDT 24	Jul 16 08:48:45 PM PDT 24	4089149208 ps
T190	/workspace/coverage/default/93.chip_sw_all_escalation_resets.3573935386			Jul 16 09:00:11 PM PDT 24	Jul 16 09:09:49 PM PDT 24	5993429022 ps
T657	/workspace/coverage/default/0.chip_sw_aes_masking_off.820631676			Jul 16 08:28:26 PM PDT 24	Jul 16 08:34:13 PM PDT 24	3147386386 ps
T191	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1735559129			Jul 16 08:27:42 PM PDT 24	Jul 16 08:57:10 PM PDT 24	14092734992 ps
T17	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2010120132			Jul 16 08:26:42 PM PDT 24	Jul 16 09:57:08 PM PDT 24	50335491479 ps
T18	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2938766455			Jul 16 08:42:33 PM PDT 24	Jul 17 12:32:06 AM PDT 24	78215973400 ps
T160	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1431432901			Jul 16 08:34:47 PM PDT 24	Jul 16 08:44:35 PM PDT 24	4180352148 ps
T384	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2252323656			Jul 16 08:57:56 PM PDT 24	Jul 16 09:04:28 PM PDT 24	3493473734 ps
T164	/workspace/coverage/default/2.chip_sw_flash_init.93501729			Jul 16 08:41:22 PM PDT 24	Jul 16 09:18:24 PM PDT 24	20493246340 ps
T431	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2429912216			Jul 16 08:49:38 PM PDT 24	Jul 16 08:55:00 PM PDT 24	2629513456 ps
T217	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1133354988			Jul 16 08:35:40 PM PDT 24	Jul 16 09:24:37 PM PDT 24	12342937760 ps
T114	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1253685975			Jul 16 08:29:02 PM PDT 24	Jul 16 08:40:36 PM PDT 24	4439995038 ps
T59	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.1830199127			Jul 16 08:30:41 PM PDT 24	Jul 16 08:42:32 PM PDT 24	6442219448 ps
T304	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3686325569			Jul 16 08:46:28 PM PDT 24	Jul 16 09:20:51 PM PDT 24	7561964100 ps
T215	/workspace/coverage/default/25.chip_sw_all_escalation_resets.3342889455			Jul 16 08:56:56 PM PDT 24	Jul 16 09:05:36 PM PDT 24	4332297976 ps
T218	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2853957220			Jul 16 08:27:33 PM PDT 24	Jul 16 08:51:23 PM PDT 24	7789531840 ps
T172	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.4181768530			Jul 16 08:47:36 PM PDT 24	Jul 16 08:59:00 PM PDT 24	6782421780 ps
T52	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1410748683			Jul 16 08:35:42 PM PDT 24	Jul 16 09:35:50 PM PDT 24	14034304387 ps
T25	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.37826375			Jul 16 08:42:04 PM PDT 24	Jul 16 08:54:47 PM PDT 24	4614084804 ps
T58	/workspace/coverage/default/1.chip_jtag_csr_rw.193785690			Jul 16 08:29:18 PM PDT 24	Jul 16 09:07:40 PM PDT 24	16769486680 ps
T216	/workspace/coverage/default/69.chip_sw_all_escalation_resets.96027142			Jul 16 09:00:17 PM PDT 24	Jul 16 09:10:48 PM PDT 24	6071170416 ps
T213	/workspace/coverage/default/0.chip_sw_uart_tx_rx.2681347483			Jul 16 08:27:43 PM PDT 24	Jul 16 08:37:19 PM PDT 24	4166958872 ps
T701	/workspace/coverage/default/2.chip_sw_hmac_oneshot.2506076935			Jul 16 08:45:01 PM PDT 24	Jul 16 08:49:32 PM PDT 24	2964119400 ps
T212	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3525356536			Jul 16 08:30:18 PM PDT 24	Jul 16 08:42:37 PM PDT 24	4739981292 ps
T312	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2756545979			Jul 16 08:41:35 PM PDT 24	Jul 16 08:52:01 PM PDT 24	4620663155 ps
T83	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1616827945			Jul 16 08:36:16 PM PDT 24	Jul 16 08:43:46 PM PDT 24	4105943076 ps
T210	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3000489625			Jul 16 08:32:27 PM PDT 24	Jul 16 08:42:57 PM PDT 24	4179058190 ps
T880	/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1039326346			Jul 16 08:47:27 PM PDT 24	Jul 16 08:53:01 PM PDT 24	3241451528 ps
T53	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.3509225880			Jul 16 08:40:53 PM PDT 24	Jul 16 10:11:07 PM PDT 24	14933185914 ps
T130	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.350081639			Jul 16 08:50:07 PM PDT 24	Jul 16 08:56:23 PM PDT 24	4043986208 ps
T881	/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.2139315461			Jul 16 08:31:45 PM PDT 24	Jul 16 10:06:45 PM PDT 24	26307839810 ps
T108	/workspace/coverage/default/0.chip_sw_power_sleep_load.1503007448			Jul 16 08:28:59 PM PDT 24	Jul 16 08:38:56 PM PDT 24	9703685640 ps
T365	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1693200412			Jul 16 08:37:00 PM PDT 24	Jul 16 09:41:09 PM PDT 24	15497145700 ps
T424	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.825188580			Jul 16 08:33:07 PM PDT 24	Jul 16 08:37:17 PM PDT 24	3006687016 ps
T882	/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.4017862837			Jul 16 08:37:14 PM PDT 24	Jul 16 08:42:13 PM PDT 24	2716094186 ps
T432	/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3643138242			Jul 16 08:29:45 PM PDT 24	Jul 16 08:34:52 PM PDT 24	3264315710 ps
T366	/workspace/coverage/default/2.rom_e2e_self_hash.391385427			Jul 16 08:53:30 PM PDT 24	Jul 16 10:18:43 PM PDT 24	27288394712 ps
T72	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1108649523			Jul 16 08:31:03 PM PDT 24	Jul 16 08:41:28 PM PDT 24	4045439760 ps
T883	/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2498685854			Jul 16 08:36:47 PM PDT 24	Jul 16 08:42:41 PM PDT 24	3870919160 ps
T884	/workspace/coverage/default/0.chip_sw_example_rom.4006935900			Jul 16 08:26:42 PM PDT 24	Jul 16 08:28:40 PM PDT 24	2434324380 ps
T330	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2519516534			Jul 16 08:33:16 PM PDT 24	Jul 16 08:53:44 PM PDT 24	14751532877 ps
T159	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3434161357			Jul 16 08:34:41 PM PDT 24	Jul 16 09:24:33 PM PDT 24	11077809684 ps
T395	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.4207322683			Jul 16 08:44:12 PM PDT 24	Jul 16 09:42:36 PM PDT 24	14807902120 ps
T885	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2971970647			Jul 16 08:36:47 PM PDT 24	Jul 16 08:40:02 PM PDT 24	2867879768 ps
T64	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.880900724			Jul 16 08:31:57 PM PDT 24	Jul 16 09:08:23 PM PDT 24	27601698286 ps
T702	/workspace/coverage/default/1.chip_sw_hmac_multistream.1372596650			Jul 16 08:37:47 PM PDT 24	Jul 16 09:06:16 PM PDT 24	7545106550 ps
T19	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.4150628251			Jul 16 08:28:33 PM PDT 24	Jul 16 08:34:33 PM PDT 24	3325149689 ps
T71	/workspace/coverage/default/2.chip_tap_straps_prod.241613994			Jul 16 08:47:16 PM PDT 24	Jul 16 08:49:37 PM PDT 24	2409475842 ps
T84	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1138829097			Jul 16 08:45:43 PM PDT 24	Jul 17 12:25:20 AM PDT 24	254886500556 ps
T189	/workspace/coverage/default/0.chip_tap_straps_dev.2458505386			Jul 16 08:28:13 PM PDT 24	Jul 16 08:30:58 PM PDT 24	2129290975 ps
T886	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.20875075			Jul 16 08:38:58 PM PDT 24	Jul 16 08:42:02 PM PDT 24	2171624882 ps
T46	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1816238771			Jul 16 08:43:41 PM PDT 24	Jul 16 08:53:38 PM PDT 24	5646239564 ps
T430	/workspace/coverage/default/1.chip_sw_power_idle_load.2614074364			Jul 16 08:39:59 PM PDT 24	Jul 16 08:51:57 PM PDT 24	5064994000 ps
T706	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.630921713			Jul 16 08:29:41 PM PDT 24	Jul 16 08:37:10 PM PDT 24	3859326854 ps
T221	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1651062961			Jul 16 08:42:09 PM PDT 24	Jul 16 08:51:12 PM PDT 24	4214740232 ps
T336	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1027169927			Jul 16 08:26:48 PM PDT 24	Jul 16 08:36:35 PM PDT 24	3682159439 ps
T65	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.2534338279			Jul 16 08:46:18 PM PDT 24	Jul 16 10:16:39 PM PDT 24	49951104635 ps
T115	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.534266861			Jul 16 08:36:38 PM PDT 24	Jul 16 08:46:50 PM PDT 24	4378121180 ps
T166	/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.823818021			Jul 16 08:56:07 PM PDT 24	Jul 16 09:13:37 PM PDT 24	13123183050 ps
T887	/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2487368282			Jul 16 08:29:11 PM PDT 24	Jul 16 08:39:40 PM PDT 24	5086310644 ps
T888	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1574474684			Jul 16 08:50:29 PM PDT 24	Jul 16 09:11:48 PM PDT 24	7530329289 ps
T68	/workspace/coverage/default/2.chip_tap_straps_testunlock0.78606434			Jul 16 08:47:09 PM PDT 24	Jul 16 09:03:00 PM PDT 24	8141497533 ps
T380	/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1638535154			Jul 16 08:58:33 PM PDT 24	Jul 16 09:04:24 PM PDT 24	3733140808 ps
T151	/workspace/coverage/default/59.chip_sw_all_escalation_resets.1431112215			Jul 16 08:58:34 PM PDT 24	Jul 16 09:08:19 PM PDT 24	5395152440 ps
T305	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3364666394			Jul 16 08:29:30 PM PDT 24	Jul 16 09:02:02 PM PDT 24	8126457048 ps
T219	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.289795615			Jul 16 08:46:23 PM PDT 24	Jul 16 09:06:35 PM PDT 24	6796780688 ps
T141	/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3406811429			Jul 16 08:56:10 PM PDT 24	Jul 16 09:37:35 PM PDT 24	12930629610 ps
T889	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1156538577			Jul 16 08:29:10 PM PDT 24	Jul 16 08:48:23 PM PDT 24	6526720863 ps
T143	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2835699083			Jul 16 08:40:12 PM PDT 24	Jul 16 09:49:48 PM PDT 24	24689100345 ps
T752	/workspace/coverage/default/89.chip_sw_all_escalation_resets.802591433			Jul 16 09:02:49 PM PDT 24	Jul 16 09:11:35 PM PDT 24	6039092906 ps
T120	/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2300426254			Jul 16 08:33:31 PM PDT 24	Jul 16 08:40:10 PM PDT 24	6751324964 ps
T222	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.417989239			Jul 16 08:35:00 PM PDT 24	Jul 16 08:56:35 PM PDT 24	7551536836 ps
T144	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3303910395			Jul 16 08:44:22 PM PDT 24	Jul 16 09:39:49 PM PDT 24	18986447919 ps
T890	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2142185314			Jul 16 08:34:37 PM PDT 24	Jul 16 09:06:36 PM PDT 24	28838142728 ps
T339	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.4271157523			Jul 16 08:28:21 PM PDT 24	Jul 16 08:39:52 PM PDT 24	3759003824 ps
T111	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3075369460			Jul 16 08:37:55 PM PDT 24	Jul 17 02:05:48 AM PDT 24	148084310654 ps
T708	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1908520719			Jul 16 08:56:31 PM PDT 24	Jul 16 09:01:35 PM PDT 24	3384660712 ps
T711	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3071937893			Jul 16 08:55:40 PM PDT 24	Jul 16 09:02:57 PM PDT 24	4222414344 ps
T361	/workspace/coverage/default/3.chip_tap_straps_dev.1677988			Jul 16 08:50:23 PM PDT 24	Jul 16 08:53:05 PM PDT 24	2821648481 ps
T109	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3228129407			Jul 16 08:29:41 PM PDT 24	Jul 16 08:39:58 PM PDT 24	18150561400 ps
T332	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.997788617			Jul 16 08:48:34 PM PDT 24	Jul 16 08:55:44 PM PDT 24	3817446070 ps
T24	/workspace/coverage/default/1.chip_sw_spi_device_pass_through.2931934075			Jul 16 08:32:11 PM PDT 24	Jul 16 08:46:49 PM PDT 24	7005693497 ps
T223	/workspace/coverage/default/24.chip_sw_all_escalation_resets.3743260580			Jul 16 08:57:07 PM PDT 24	Jul 16 09:09:16 PM PDT 24	5066982860 ps
T712	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3882060045			Jul 16 08:57:06 PM PDT 24	Jul 16 09:03:24 PM PDT 24	4251403332 ps
T707	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.40521092			Jul 16 08:29:06 PM PDT 24	Jul 16 08:44:12 PM PDT 24	7132926848 ps
T323	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.219130874			Jul 16 08:27:32 PM PDT 24	Jul 16 08:41:12 PM PDT 24	5050574180 ps
T344	/workspace/coverage/default/21.chip_sw_all_escalation_resets.1209398861			Jul 16 08:57:50 PM PDT 24	Jul 16 09:09:34 PM PDT 24	6357205130 ps
T776	/workspace/coverage/default/37.chip_sw_all_escalation_resets.1323806584			Jul 16 09:02:56 PM PDT 24	Jul 16 09:13:45 PM PDT 24	6376656152 ps
T239	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1950063685			Jul 16 08:47:24 PM PDT 24	Jul 16 08:54:39 PM PDT 24	5017244164 ps
T54	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.4208198624			Jul 16 08:35:28 PM PDT 24	Jul 16 09:54:06 PM PDT 24	17972944600 ps
T250	/workspace/coverage/default/1.chip_sw_rv_timer_irq.2487140838			Jul 16 08:34:39 PM PDT 24	Jul 16 08:39:43 PM PDT 24	3114939408 ps
T260	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2819947479			Jul 16 08:29:54 PM PDT 24	Jul 16 08:49:45 PM PDT 24	6559957200 ps
T261	/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3582295080			Jul 16 08:43:07 PM PDT 24	Jul 16 09:03:01 PM PDT 24	7954280832 ps
T262	/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2731219437			Jul 16 08:32:34 PM PDT 24	Jul 16 08:55:37 PM PDT 24	5591470756 ps
T263	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2863843058			Jul 16 08:46:00 PM PDT 24	Jul 16 08:56:09 PM PDT 24	9147164426 ps
T264	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3223216230			Jul 16 08:41:10 PM PDT 24	Jul 16 08:46:27 PM PDT 24	3004049812 ps
T265	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3085997697			Jul 16 08:36:29 PM PDT 24	Jul 16 09:37:47 PM PDT 24	14454829728 ps
T119	/workspace/coverage/default/2.chip_sw_edn_kat.1077144673			Jul 16 08:51:40 PM PDT 24	Jul 16 09:02:38 PM PDT 24	3624190520 ps
T232	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1400661037			Jul 16 08:30:57 PM PDT 24	Jul 16 09:06:33 PM PDT 24	20032534637 ps
T891	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1203169704			Jul 16 08:37:58 PM PDT 24	Jul 16 08:42:15 PM PDT 24	3272417944 ps
T81	/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3731291095			Jul 16 08:47:54 PM PDT 24	Jul 16 08:55:50 PM PDT 24	3740429020 ps
T325	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.948410924			Jul 16 08:51:40 PM PDT 24	Jul 16 09:05:33 PM PDT 24	4283734540 ps
T699	/workspace/coverage/default/97.chip_sw_all_escalation_resets.3117047033			Jul 16 09:00:13 PM PDT 24	Jul 16 09:11:13 PM PDT 24	4579258710 ps
T26	/workspace/coverage/default/1.chip_sw_gpio_smoketest.3844256228			Jul 16 08:41:21 PM PDT 24	Jul 16 08:45:55 PM PDT 24	2669587945 ps
T398	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1237543376			Jul 16 08:55:15 PM PDT 24	Jul 16 09:01:20 PM PDT 24	2976578680 ps
T246	/workspace/coverage/default/1.chip_sw_plic_sw_irq.21177778			Jul 16 08:37:44 PM PDT 24	Jul 16 08:42:26 PM PDT 24	2973674170 ps
T306	/workspace/coverage/default/0.chip_plic_all_irqs_20.2703188406			Jul 16 08:31:15 PM PDT 24	Jul 16 08:42:50 PM PDT 24	4665789080 ps
T892	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3431136959			Jul 16 08:38:39 PM PDT 24	Jul 16 09:36:44 PM PDT 24	14466942176 ps
T208	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.2421036939			Jul 16 08:41:56 PM PDT 24	Jul 16 08:59:15 PM PDT 24	5491215064 ps
T893	/workspace/coverage/default/2.chip_sw_csrng_smoketest.175205688			Jul 16 08:55:24 PM PDT 24	Jul 16 08:59:24 PM PDT 24	2790091624 ps
T238	/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1419285364			Jul 16 08:31:57 PM PDT 24	Jul 17 12:06:10 AM PDT 24	254441669082 ps
T894	/workspace/coverage/default/1.chip_sw_ast_clk_outputs.2599470174			Jul 16 08:37:35 PM PDT 24	Jul 16 08:59:33 PM PDT 24	7555454264 ps
T895	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3321326983			Jul 16 08:33:52 PM PDT 24	Jul 16 08:39:31 PM PDT 24	3783002912 ps
T353	/workspace/coverage/default/29.chip_sw_all_escalation_resets.3942215962			Jul 16 08:57:26 PM PDT 24	Jul 16 09:07:55 PM PDT 24	5268365436 ps
T896	/workspace/coverage/default/0.chip_sw_aes_entropy.127191762			Jul 16 08:30:27 PM PDT 24	Jul 16 08:34:36 PM PDT 24	2896885852 ps
T418	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2240447571			Jul 16 08:55:27 PM PDT 24	Jul 16 09:01:56 PM PDT 24	3451631994 ps
T897	/workspace/coverage/default/2.chip_sw_otbn_smoketest.136301510			Jul 16 08:50:07 PM PDT 24	Jul 16 09:19:48 PM PDT 24	8294986696 ps
T741	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.908674658			Jul 16 08:57:30 PM PDT 24	Jul 16 09:05:00 PM PDT 24	3775859450 ps
T898	/workspace/coverage/default/0.chip_sw_csrng_kat_test.2572663239			Jul 16 08:32:39 PM PDT 24	Jul 16 08:36:48 PM PDT 24	2641920340 ps
T899	/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3805796937			Jul 16 08:51:10 PM PDT 24	Jul 16 09:01:29 PM PDT 24	7870078228 ps
T900	/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3153740837			Jul 16 08:38:13 PM PDT 24	Jul 16 08:47:07 PM PDT 24	4775348952 ps
T425	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1212222481			Jul 16 08:51:57 PM PDT 24	Jul 16 08:56:28 PM PDT 24	2880248580 ps
T901	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2716000839			Jul 16 08:36:39 PM PDT 24	Jul 16 09:38:47 PM PDT 24	14406212407 ps
T742	/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1644958349			Jul 16 08:45:08 PM PDT 24	Jul 16 08:56:48 PM PDT 24	5408220508 ps
T902	/workspace/coverage/default/1.rom_e2e_asm_init_rma.701668760			Jul 16 08:43:41 PM PDT 24	Jul 16 09:43:07 PM PDT 24	14480646231 ps
T326	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.926146133			Jul 16 08:26:22 PM PDT 24	Jul 16 08:37:30 PM PDT 24	4314938456 ps
T112	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1440156149			Jul 16 08:32:23 PM PDT 24	Jul 17 01:43:34 AM PDT 24	129599531586 ps
T266	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1497771683			Jul 16 08:44:11 PM PDT 24	Jul 16 08:46:29 PM PDT 24	2890361827 ps
T903	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2979530637			Jul 16 08:48:08 PM PDT 24	Jul 16 08:56:55 PM PDT 24	3839975720 ps
T904	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.458189003			Jul 16 08:28:37 PM PDT 24	Jul 16 08:35:53 PM PDT 24	4089907800 ps
T700	/workspace/coverage/default/18.chip_sw_all_escalation_resets.3874821212			Jul 16 08:56:53 PM PDT 24	Jul 16 09:03:47 PM PDT 24	5257080448 ps
T267	/workspace/coverage/default/2.rom_e2e_shutdown_output.3552888469			Jul 16 08:52:35 PM PDT 24	Jul 16 09:52:17 PM PDT 24	28108969355 ps
T230	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3231835283			Jul 16 08:48:07 PM PDT 24	Jul 16 09:15:18 PM PDT 24	19048583851 ps
T333	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3920025321			Jul 16 08:32:05 PM PDT 24	Jul 16 08:59:28 PM PDT 24	12985144855 ps
T434	/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.54999920			Jul 16 08:55:10 PM PDT 24	Jul 16 09:25:16 PM PDT 24	9222408198 ps
T905	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.3063306274			Jul 16 08:33:09 PM PDT 24	Jul 16 08:43:46 PM PDT 24	4010588926 ps
T753	/workspace/coverage/default/67.chip_sw_all_escalation_resets.22171177			Jul 16 08:58:56 PM PDT 24	Jul 16 09:06:32 PM PDT 24	6295378108 ps
T167	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1118661345			Jul 16 08:54:34 PM PDT 24	Jul 16 09:04:09 PM PDT 24	10319068783 ps
T906	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1392976694			Jul 16 08:26:36 PM PDT 24	Jul 16 08:48:15 PM PDT 24	8693879800 ps
T907	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1177826394			Jul 16 08:30:26 PM PDT 24	Jul 16 08:36:02 PM PDT 24	6780791212 ps
T799	/workspace/coverage/default/95.chip_sw_all_escalation_resets.911317377			Jul 16 08:59:03 PM PDT 24	Jul 16 09:06:14 PM PDT 24	4912670184 ps
T220	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2983106379			Jul 16 08:35:40 PM PDT 24	Jul 16 09:01:24 PM PDT 24	6993946968 ps
T908	/workspace/coverage/default/62.chip_sw_all_escalation_resets.3551308271			Jul 16 08:57:56 PM PDT 24	Jul 16 09:07:40 PM PDT 24	5334302958 ps
T224	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2105255873			Jul 16 08:27:51 PM PDT 24	Jul 16 08:52:03 PM PDT 24	7725744500 ps
T173	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3046400102			Jul 16 08:30:49 PM PDT 24	Jul 16 08:40:37 PM PDT 24	6735433632 ps
T721	/workspace/coverage/default/16.chip_sw_all_escalation_resets.2068216976			Jul 16 08:55:50 PM PDT 24	Jul 16 09:05:32 PM PDT 24	5020224080 ps
T178	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1006496627			Jul 16 08:42:31 PM PDT 24	Jul 16 10:05:11 PM PDT 24	44926834720 ps
T209	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2713406606			Jul 16 08:32:40 PM PDT 24	Jul 16 08:45:51 PM PDT 24	4595415100 ps
T29	/workspace/coverage/default/0.chip_sw_usbdev_setuprx.3864553452			Jul 16 08:26:23 PM PDT 24	Jul 16 08:36:00 PM PDT 24	4642974776 ps
T334	/workspace/coverage/default/0.chip_sw_aon_timer_irq.214947918			Jul 16 08:28:52 PM PDT 24	Jul 16 08:35:38 PM PDT 24	4203069560 ps
T909	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.4041353491			Jul 16 08:35:41 PM PDT 24	Jul 16 09:35:22 PM PDT 24	16092923131 ps
T910	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3376790090			Jul 16 08:49:19 PM PDT 24	Jul 16 08:57:18 PM PDT 24	3404514908 ps
T314	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.2839932196			Jul 16 08:43:43 PM PDT 24	Jul 16 08:55:41 PM PDT 24	4169412360 ps
T911	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.3227647461			Jul 16 08:48:46 PM PDT 24	Jul 16 08:57:19 PM PDT 24	6411091376 ps
T777	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1519878748			Jul 16 08:29:59 PM PDT 24	Jul 16 08:37:50 PM PDT 24	3564890964 ps
T382	/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.365981441			Jul 16 08:47:08 PM PDT 24	Jul 16 08:50:36 PM PDT 24	2819927312 ps
T912	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2053583898			Jul 16 08:39:35 PM PDT 24	Jul 16 08:49:33 PM PDT 24	5783888504 ps
T337	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1284327878			Jul 16 08:49:48 PM PDT 24	Jul 16 09:02:20 PM PDT 24	4843769855 ps
T27	/workspace/coverage/default/0.chip_sw_gpio_smoketest.57513778			Jul 16 08:30:32 PM PDT 24	Jul 16 08:34:56 PM PDT 24	2869056383 ps
T913	/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.510513950			Jul 16 08:56:05 PM PDT 24	Jul 16 09:10:00 PM PDT 24	9996113561 ps
T145	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3212245544			Jul 16 08:42:16 PM PDT 24	Jul 16 11:38:08 PM PDT 24	59595114456 ps
T309	/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3583140024			Jul 16 08:54:12 PM PDT 24	Jul 16 09:17:25 PM PDT 24	8099386696 ps
T349	/workspace/coverage/default/1.chip_sival_flash_info_access.3498737717			Jul 16 08:30:21 PM PDT 24	Jul 16 08:35:21 PM PDT 24	3478792832 ps
T116	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2780683986			Jul 16 08:26:59 PM PDT 24	Jul 16 08:34:14 PM PDT 24	4230200518 ps
T47	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.262776149			Jul 16 08:34:56 PM PDT 24	Jul 16 08:42:30 PM PDT 24	6571478596 ps
T228	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1355930470			Jul 16 08:29:28 PM PDT 24	Jul 16 09:32:46 PM PDT 24	14299566472 ps
T152	/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.211109778			Jul 16 08:58:25 PM PDT 24	Jul 16 09:04:50 PM PDT 24	3757359080 ps
T914	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2753233074			Jul 16 08:41:10 PM PDT 24	Jul 16 08:46:45 PM PDT 24	2921951336 ps
T242	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.3623614655			Jul 16 08:33:05 PM PDT 24	Jul 16 08:40:13 PM PDT 24	3775630576 ps
T73	/workspace/coverage/default/0.chip_tap_straps_testunlock0.1135319257			Jul 16 08:32:43 PM PDT 24	Jul 16 08:48:38 PM PDT 24	9261799185 ps
T698	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3477432309			Jul 16 08:59:33 PM PDT 24	Jul 16 09:06:49 PM PDT 24	3221951518 ps
T243	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.1909462386			Jul 16 08:46:49 PM PDT 24	Jul 16 08:56:29 PM PDT 24	5560138140 ps
T915	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2712230974			Jul 16 08:57:47 PM PDT 24	Jul 16 09:19:46 PM PDT 24	7606528088 ps
T916	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.3375477920			Jul 16 08:44:11 PM PDT 24	Jul 16 08:54:52 PM PDT 24	5012073856 ps
T917	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3697729479			Jul 16 08:55:13 PM PDT 24	Jul 16 09:34:17 PM PDT 24	9344171544 ps
T918	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.4160158284			Jul 16 08:30:39 PM PDT 24	Jul 16 08:35:23 PM PDT 24	2633162980 ps
T74	/workspace/coverage/default/4.chip_tap_straps_rma.1751501418			Jul 16 08:50:59 PM PDT 24	Jul 16 08:56:21 PM PDT 24	3432311745 ps
T3	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.4203724595			Jul 16 08:48:13 PM PDT 24	Jul 16 09:13:57 PM PDT 24	23852132250 ps
T231	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3270283021			Jul 16 08:38:13 PM PDT 24	Jul 16 09:07:48 PM PDT 24	20031637955 ps
T919	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.3561052373			Jul 16 08:57:43 PM PDT 24	Jul 16 09:45:30 PM PDT 24	15162230488 ps
T714	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3258237340			Jul 16 08:58:09 PM PDT 24	Jul 16 09:06:25 PM PDT 24	3530750440 ps
T307	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1387041806			Jul 16 08:29:48 PM PDT 24	Jul 16 08:40:45 PM PDT 24	5000564218 ps
T732	/workspace/coverage/default/85.chip_sw_all_escalation_resets.818485321			Jul 16 08:59:58 PM PDT 24	Jul 16 09:09:18 PM PDT 24	6133434028 ps
T117	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.831766286			Jul 16 08:30:57 PM PDT 24	Jul 16 08:42:40 PM PDT 24	3624748840 ps
T661	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1531884420			Jul 16 08:31:28 PM PDT 24	Jul 16 08:43:52 PM PDT 24	6505465142 ps
T920	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1928013846			Jul 16 08:49:18 PM PDT 24	Jul 16 08:59:13 PM PDT 24	4111356200 ps
T168	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1463772737			Jul 16 08:46:28 PM PDT 24	Jul 16 09:18:48 PM PDT 24	28198736440 ps
T740	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1676745211			Jul 16 08:56:43 PM PDT 24	Jul 16 09:03:57 PM PDT 24	3457998056 ps
T90	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2921003554			Jul 16 09:01:26 PM PDT 24	Jul 16 09:08:22 PM PDT 24	3631095488 ps
T94	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3255365128			Jul 16 08:28:27 PM PDT 24	Jul 16 08:33:15 PM PDT 24	3268360462 ps
T95	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3732512035			Jul 16 08:33:29 PM PDT 24	Jul 16 09:34:45 PM PDT 24	18980839960 ps
T96	/workspace/coverage/default/0.chip_sw_edn_sw_mode.4222483395			Jul 16 08:29:22 PM PDT 24	Jul 16 08:53:44 PM PDT 24	6940013056 ps
T97	/workspace/coverage/default/1.chip_sw_csrng_kat_test.1575904391			Jul 16 08:40:34 PM PDT 24	Jul 16 08:46:36 PM PDT 24	2794001972 ps
T98	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3687973569			Jul 16 08:35:15 PM PDT 24	Jul 16 09:46:50 PM PDT 24	15364879248 ps
T99	/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.543598054			Jul 16 08:35:35 PM PDT 24	Jul 16 08:53:06 PM PDT 24	6791755558 ps
T100	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2434226210			Jul 16 08:52:12 PM PDT 24	Jul 16 08:59:00 PM PDT 24	4018058047 ps
T69	/workspace/coverage/default/3.chip_tap_straps_rma.1023316954			Jul 16 08:51:48 PM PDT 24	Jul 16 09:04:28 PM PDT 24	6500227706 ps
T101	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.2455056233			Jul 16 08:50:55 PM PDT 24	Jul 16 09:08:09 PM PDT 24	6343610700 ps
T273	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.845779449			Jul 16 08:57:49 PM PDT 24	Jul 16 09:04:09 PM PDT 24	3968674060 ps
T274	/workspace/coverage/default/1.chip_sw_aes_entropy.3981491970			Jul 16 08:35:25 PM PDT 24	Jul 16 08:39:56 PM PDT 24	2405627806 ps
T237	/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2840916631			Jul 16 08:36:12 PM PDT 24	Jul 16 11:38:54 PM PDT 24	254532823580 ps
T268	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3128276809			Jul 16 08:35:01 PM PDT 24	Jul 16 09:32:03 PM PDT 24	13388450480 ps
T275	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.294183175			Jul 16 08:49:55 PM PDT 24	Jul 16 09:03:31 PM PDT 24	6580869098 ps
T276	/workspace/coverage/default/0.chip_sw_kmac_idle.3967837585			Jul 16 08:37:15 PM PDT 24	Jul 16 08:42:06 PM PDT 24	2245491932 ps
T174	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.662765663			Jul 16 08:43:48 PM PDT 24	Jul 16 08:48:19 PM PDT 24	2980387398 ps
T34	/workspace/coverage/default/2.chip_sw_gpio_smoketest.3367140883			Jul 16 08:50:31 PM PDT 24	Jul 16 08:55:17 PM PDT 24	3044430912 ps
T91	/workspace/coverage/default/55.chip_sw_all_escalation_resets.172690914			Jul 16 08:58:29 PM PDT 24	Jul 16 09:05:12 PM PDT 24	4067707832 ps
T207	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3388911093			Jul 16 08:57:04 PM PDT 24	Jul 16 09:03:46 PM PDT 24	3309844744 ps
T298	/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.4193364326			Jul 16 08:49:03 PM PDT 24	Jul 16 08:53:08 PM PDT 24	2577078512 ps
T299	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.252696908			Jul 16 08:28:51 PM PDT 24	Jul 16 08:51:56 PM PDT 24	7383254464 ps