Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	415	1			T78	2		T82	2		T513	1
all_values[1]	499	1			T78	3		T82	2		T512	1
all_values[2]	488	1			T78	4		T82	5		T513	1
all_values[3]	459	1			T78	6		T82	3		T513	1
all_values[4]	498	1			T78	4		T514	1		T437	1
all_values[5]	483	1			T78	5		T82	8		T512	3
all_values[6]	484	1			T78	1		T82	2		T512	4
all_values[7]	487	1			T78	1		T79	1		T82	4
all_values[8]	533	1			T78	2		T79	2		T82	5
all_values[9]	464	1			T78	3		T673	1		T82	1
all_values[10]	460	1			T78	1		T82	6		T513	2
all_values[11]	510	1			T78	4		T79	1		T82	3
all_values[12]	473	1			T78	4		T82	6		T512	3
all_values[13]	481	1			T78	5		T82	3		T512	1
all_values[14]	467	1			T78	8		T82	2		T437	4
all_values[15]	477	1			T78	3		T82	1		T512	2
all_values[16]	472	1			T78	5		T82	5		T512	3
all_values[17]	524	1			T78	3		T673	1		T82	2
all_values[18]	493	1			T78	3		T82	3		T512	1
all_values[19]	480	1			T78	1		T79	2		T82	2
all_values[20]	459	1			T78	1		T79	1		T82	2
all_values[21]	470	1			T78	2		T82	1		T513	1
all_values[22]	468	1			T78	4		T82	1		T512	1
all_values[23]	461	1			T78	1		T82	2		T512	1
all_values[24]	479	1			T78	4		T82	1		T437	4
all_values[25]	477	1			T78	1		T82	4		T512	1
all_values[26]	487	1			T78	2		T82	1		T512	2
all_values[27]	469	1			T78	5		T513	2		T512	2
all_values[28]	475	1			T78	4		T82	1		T513	1
all_values[29]	452	1			T78	3		T80	1		T673	1
all_values[30]	492	1			T78	5		T82	3		T513	1
all_values[31]	436	1			T78	5		T79	1		T512	1
all_values[32]	510	1			T78	5		T82	3		T437	2
all_values[33]	522	1			T78	1		T79	1		T82	1
all_values[34]	468	1			T78	3		T79	1		T82	7
all_values[35]	504	1			T78	4		T79	1		T82	4
all_values[36]	481	1			T78	5		T82	2		T514	1
all_values[37]	505	1			T78	4		T82	2		T518	1
all_values[38]	529	1			T78	2		T82	3		T512	3
all_values[39]	461	1			T78	3		T79	2		T82	4
all_values[40]	507	1			T78	2		T79	2		T82	7
all_values[41]	470	1			T78	5		T82	5		T512	2
all_values[42]	470	1			T78	2		T437	5		T456	1
all_values[43]	500	1			T78	2		T82	3		T512	2
all_values[44]	513	1			T78	3		T79	1		T512	2
all_values[45]	482	1			T78	6		T82	4		T513	1
all_values[46]	466	1			T78	3		T82	1		T512	1
all_values[47]	490	1			T78	4		T79	1		T82	4
all_values[48]	514	1			T78	5		T79	1		T82	2
all_values[49]	472	1			T78	5		T82	3		T512	7