Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3858	1			T78	20		T79	1		T80	1
all_values[1]	3744	1			T78	26		T79	3		T80	1
all_values[2]	3760	1			T78	27		T79	5		T80	1
all_values[3]	3773	1			T78	15		T79	4		T80	1
all_values[4]	3863	1			T78	27		T79	6		T80	1
all_values[5]	3793	1			T78	14		T79	2		T80	2
all_values[6]	3644	1			T78	23		T79	5		T80	4
all_values[7]	3733	1			T78	15		T79	4		T80	3
all_values[8]	3811	1			T78	22		T79	2		T80	2
all_values[9]	3868	1			T78	28		T79	4		T80	1
all_values[10]	3775	1			T78	25		T79	4		T82	13
all_values[11]	3809	1			T78	21		T79	2		T80	1
all_values[12]	3771	1			T78	25		T79	1		T80	1
all_values[13]	3712	1			T78	24		T79	2		T82	18
all_values[14]	3706	1			T78	14		T79	4		T80	2
all_values[15]	3785	1			T78	23		T79	1		T80	4
all_values[16]	3791	1			T78	29		T79	4		T80	1
all_values[17]	3774	1			T78	27		T79	2		T80	2
all_values[18]	3796	1			T78	28		T79	2		T80	3
all_values[19]	3802	1			T78	16		T79	4		T80	2
all_values[20]	3810	1			T78	34		T79	4		T80	2
all_values[21]	3728	1			T78	11		T79	5		T80	3
all_values[22]	3711	1			T78	27		T79	2		T80	3
all_values[23]	3686	1			T78	20		T79	1		T80	3
all_values[24]	3827	1			T78	27		T79	3		T80	2
all_values[25]	3782	1			T78	22		T80	3		T82	18
all_values[26]	3749	1			T78	24		T79	6		T80	1
all_values[27]	3858	1			T78	28		T79	3		T80	3
all_values[28]	3824	1			T78	26		T79	5		T80	1
all_values[29]	3695	1			T78	32		T79	3		T80	1
all_values[30]	3787	1			T78	28		T79	1		T82	20
all_values[31]	3765	1			T78	24		T79	3		T82	18
all_values[32]	3722	1			T78	30		T79	1		T80	4
all_values[33]	3876	1			T78	25		T79	4		T80	1
all_values[34]	3809	1			T78	27		T79	4		T80	2
all_values[35]	3723	1			T78	24		T79	2		T80	2
all_values[36]	3781	1			T78	42		T79	3		T80	2
all_values[37]	3764	1			T78	17		T79	5		T80	4
all_values[38]	3919	1			T78	23		T79	2		T80	2
all_values[39]	3698	1			T78	18		T79	4		T82	23
all_values[40]	3807	1			T78	22		T79	2		T80	2
all_values[41]	3954	1			T78	28		T79	2		T80	2
all_values[42]	3726	1			T78	29		T79	5		T80	3
all_values[43]	3783	1			T78	26		T79	1		T80	3
all_values[44]	3870	1			T78	30		T82	18		T512	16
all_values[45]	3852	1			T78	16		T79	2		T80	2
all_values[46]	3802	1			T78	33		T79	2		T80	3
all_values[47]	3875	1			T78	31		T79	2		T80	2
all_values[48]	3678	1			T78	23		T79	2		T80	1
all_values[49]	3775	1			T78	32		T79	1		T80	2
all_values[50]	3749	1			T78	20		T79	4		T80	2
all_values[51]	3759	1			T78	23		T79	2		T80	3
all_values[52]	3817	1			T78	21		T79	1		T82	29
all_values[53]	3807	1			T78	19		T79	2		T80	4
all_values[54]	3725	1			T78	20		T79	4		T82	10
all_values[55]	3691	1			T78	18		T79	4		T80	1
all_values[56]	3865	1			T78	31		T79	7		T80	3
all_values[57]	3751	1			T78	23		T79	3		T80	1
all_values[58]	3803	1			T78	23		T79	2		T80	5
all_values[59]	3792	1			T78	24		T79	2		T80	2
all_values[60]	3726	1			T78	13		T79	4		T80	1
all_values[61]	3810	1			T78	24		T79	3		T80	2
all_values[62]	3685	1			T78	22		T79	5		T82	10
all_values[63]	3799	1			T78	25		T79	2		T80	2