LINE 18005
EXPRESSION (addr_hit[200] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 0 | 1 | 1 | Covered | T4,T5,T15 |
| 1 | 0 | 1 | Covered | T7,T696,T697 |
| 1 | 1 | 0 | Covered | T521,T523,T545 |
| 1 | 1 | 1 | Covered | T246,T7,T247 |
LINE 18008
EXPRESSION (addr_hit[201] & reg_we & ((!reg_error)))
------1------ ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 0 | 1 | 1 | Covered | T4,T5,T15 |
| 1 | 0 | 1 | Covered | T7,T126,T138 |
| 1 | 1 | 0 | Covered | T525,T545,T691 |
| 1 | 1 | 1 | Covered | T60,T7,T61 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |