aad711e1bc| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_example_tests | chip_sw_example_flash | 5.141m | 3.266ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.005m | 2.475ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 4.628m | 2.517ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 5.046m | 3.217ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 6.705m | 6.842ms | 5 | 5 | 100.00 |
| V1 | csr_rw | chip_csr_rw | 11.611m | 6.993ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | chip_csr_bit_bash | 1.510h | 43.358ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 2.920h | 68.227ms | 4 | 5 | 80.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 15.659m | 10.747ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 2.920h | 68.227ms | 4 | 5 | 80.00 |
| chip_csr_rw | 11.611m | 6.993ms | 20 | 20 | 100.00 | ||
| V1 | xbar_smoke | xbar_smoke | 10.690s | 270.030us | 100 | 100 | 100.00 |
| V1 | chip_sw_gpio_out | chip_sw_gpio | 9.691m | 4.336ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 9.691m | 4.336ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 9.691m | 4.336ms | 3 | 3 | 100.00 |
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 12.224m | 4.640ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 12.224m | 4.640ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 13.869m | 4.284ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 11.318m | 4.418ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 12.702m | 4.614ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_baud_rate | chip_sw_uart_rand_baudrate | 41.402m | 12.931ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 40.622m | 13.210ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 28.514m | 12.905ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 219 | 220 | 99.55 | |||
| V2 | chip_pin_mux | chip_padctrl_attributes | 5.137m | 5.218ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 5.137m | 5.218ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 5.978m | 3.325ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 7.969m | 6.621ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 6.469m | 4.700ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 6.264m | 4.185ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 15.889m | 9.262ms | 4 | 5 | 80.00 | ||
| chip_tap_straps_rma | 1.823h | 60.000ms | 3 | 5 | 60.00 | ||
| chip_tap_straps_prod | 17.655m | 10.414ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 5.122m | 3.048ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 21.625m | 8.694ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 17.221m | 6.344ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 17.221m | 6.344ms | 6 | 6 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 21.961m | 7.555ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 49.152m | 21.356ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 13.069m | 3.922ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 21.072m | 5.391ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.021h | 18.981ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.122m | 3.063ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 25.026m | 7.990ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.850m | 3.023ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 41.483m | 10.781ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.744m | 2.783ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 13.333m | 5.418ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.408m | 3.253ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 5.455m | 3.341ms | 1 | 1 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 16.390m | 6.915ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 9.569m | 5.456ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 5.759m | 3.374ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 9.569m | 5.456ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 4.767m | 2.802ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 5.402m | 3.357ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 6.816m | 2.663ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 4.079m | 2.577ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 3.984m | 2.790ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 9.037m | 3.586ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 4.741m | 3.044ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 6.691m | 3.405ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 6.281m | 3.108ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 29.666m | 8.295ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 11.259m | 6.810ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 6.979m | 6.423ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 5.197m | 2.780ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 4.402m | 2.882ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 5.564m | 2.922ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 4.503m | 2.880ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 6.504m | 3.426ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_smoketest | chip_sw_otp_ctrl_smoketest | 5.623m | 3.783ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 11.157m | 4.712ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 4.182h | 78.316ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 1.091h | 15.244ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 4.933m | 5.357ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 13.489m | 4.718ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 9.923m | 9.704ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 3.163h | 58.640ms | 3 | 3 | 100.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 3.419h | 64.739ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 8.602m | 5.278ms | 30 | 30 | 100.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 8.602m | 5.278ms | 30 | 30 | 100.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 2.920h | 68.227ms | 4 | 5 | 80.00 |
| chip_same_csr_outstanding | 1.279h | 29.063ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 6.705m | 6.842ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 11.611m | 6.993ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 2.920h | 68.227ms | 4 | 5 | 80.00 |
| chip_same_csr_outstanding | 1.279h | 29.063ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 6.705m | 6.842ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 11.611m | 6.993ms | 20 | 20 | 100.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 1.732m | 2.675ms | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 7.390s | 54.238us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 2.115m | 11.364ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 2.011m | 6.609ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 55.590s | 619.327us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 23.730m | 119.932ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 22.220m | 70.404ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 1.105m | 1.470ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 55.710s | 1.425ms | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 1.609m | 2.722ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 55.710s | 1.425ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 2.478m | 3.674ms | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 52.043m | 157.576ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.474m | 2.676ms | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 11.174m | 17.536ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 10.963m | 19.622ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 18.333m | 10.608ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 17.721m | 9.694ms | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 1.091h | 15.244ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 1.142h | 28.431ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 1.503h | 14.933ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 51.513m | 11.082ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 1.137h | 15.777ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 1.158h | 15.326ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 1.316h | 15.321ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 1.138h | 14.980ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 49.844m | 11.078ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 1.077h | 14.858ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 1.568h | 15.522ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 1.069h | 15.497ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 1.193h | 15.365ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 1.381h | 18.494ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 1.878h | 24.237ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 1.585h | 24.049ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 1.659h | 24.230ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 1.668h | 22.687ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 1.310h | 17.973ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 2.052h | 23.102ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 1.451h | 23.695ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 1.652h | 23.312ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 1.605h | 22.878ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 45.548m | 11.930ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 1.022h | 14.455ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 1.002h | 14.034ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 59.542m | 14.622ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 59.386m | 14.810ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 50.614m | 11.544ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 1.481h | 15.039ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 1.035h | 14.406ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 56.568m | 14.670ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 57.014m | 13.388ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 52.984m | 11.239ms | 3 | 3 | 100.00 |
| rom_e2e_asm_init_dev | 1.331h | 15.383ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod | 1.129h | 15.346ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod_end | 1.005h | 15.870ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_rma | 1.107h | 15.500ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 1.058h | 15.155ms | 3 | 3 | 100.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 1.130h | 14.329ms | 3 | 3 | 100.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 1.234h | 14.774ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 1.120h | 16.958ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 6.123m | 3.095ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 5.122m | 3.063ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_multi_block | chip_sw_aes_multi_block | 0 | 0 | -- | ||
| V2 | chip_sw_aes_interrupt_encryption | chip_sw_aes_interrupt_encryption | 0 | 0 | -- | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 4.650m | 2.823ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_prng_reseed | chip_sw_aes_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_force_prng_reseed | chip_sw_aes_force_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 5.636m | 3.323ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 37.274m | 10.588ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.420m | 18.690ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.420m | 18.690ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 8.293m | 3.711ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 11.259m | 6.810ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 8.293m | 3.711ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 16.808m | 8.140ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 16.808m | 8.140ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 10.309m | 7.870ms | 5 | 5 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 10.919m | 5.001ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 18.985m | 5.855ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 5.636m | 3.323ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 5.162m | 2.951ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 4.847m | 2.245ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 10.497m | 5.272ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 9.368m | 5.353ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 8.089m | 3.835ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 9.750m | 4.892ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 21.980m | 9.120ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 13.285m | 4.241ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 14.286m | 4.881ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 13.874m | 4.069ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 14.891m | 5.284ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 12.143m | 4.593ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 12.950m | 4.960ms | 3 | 3 | 100.00 | ||
| chip_sw_ast_clk_outputs | 21.961m | 7.555ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 17.528m | 11.265ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 13.874m | 4.069ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 14.891m | 5.284ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 13.069m | 3.922ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 21.072m | 5.391ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.021h | 18.981ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.122m | 3.063ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 25.026m | 7.990ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.850m | 3.023ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 41.483m | 10.781ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.744m | 2.783ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 13.333m | 5.418ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.408m | 3.253ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 4.189m | 2.875ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 12.904m | 5.051ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 22.110m | 7.808ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.635h | 24.850ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 5.130m | 2.809ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 5.547m | 3.255ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 32.818m | 13.067ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 6.073m | 3.452ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 12.890m | 5.684ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 35.565m | 20.033ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 5.464h | 148.084ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 21.961m | 7.555ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 10.454m | 5.086ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 8.783m | 3.840ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 13.429m | 5.104ms | 98 | 100 | 98.00 |
| V2 | chip_sw_clkmgr_alert_handler_clock_enables | chip_sw_alert_handler_lpg_clkoff | 34.358m | 7.562ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 29.342m | 7.976ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 8.950m | 4.116ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 10.302m | 7.393ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 6.006m | 2.794ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 21.416m | 8.299ms | 3 | 3 | 100.00 |
| chip_sw_sysrst_ctrl_reset | 33.387m | 23.232ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 6.373m | 3.243ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 7.035m | 3.570ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 11.384m | 4.255ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 33.387m | 23.232ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 33.387m | 23.232ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 59.642m | 20.809ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 59.642m | 20.809ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 9.932m | 5.646ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 10.420m | 18.690ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 1.654h | 25.613ms | 10 | 10 | 100.00 |
| chip_sw_entropy_src_ast_rng_req | 5.008m | 2.459ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs | 26.628m | 6.345ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 5.008m | 2.459ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 29.342m | 7.976ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 4.438m | 2.774ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fw_observe_many_contiguous | chip_sw_entropy_src_fw_observe_many_contiguous | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_fw_extract_and_insert | chip_sw_entropy_src_fw_extract_and_insert | 0 | 0 | -- | ||
| V2 | chip_sw_flash_init | chip_sw_flash_init | 40.649m | 26.341ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 22.393m | 5.763ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 21.072m | 5.391ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 14.024m | 4.533ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 13.069m | 3.922ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.377h | 44.927ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 40.649m | 26.341ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 5.979m | 3.646ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 42.990m | 12.355ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 9.784m | 4.180ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.377h | 44.927ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 9.784m | 4.180ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 9.784m | 4.180ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 9.784m | 4.180ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 9.784m | 4.180ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 13.429m | 5.104ms | 98 | 100 | 98.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 2.922m | 4.549ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 19.750m | 5.366ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 11.349m | 4.560ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_write_clear | chip_sw_flash_crash_alert | 11.349m | 4.560ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 6.482m | 3.321ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 5.850m | 3.023ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 5.162m | 2.951ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_all_configurations | chip_sw_hmac_oneshot | 5.806m | 3.081ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_multistream_mode | chip_sw_hmac_multistream | 32.501m | 6.849ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 17.317m | 5.491ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 11.944m | 4.169ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 16.538m | 5.227ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 12.294m | 4.740ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 42.990m | 12.355ms | 3 | 3 | 100.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 41.483m | 10.781ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 24.155m | 7.726ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 37.274m | 10.588ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 1.055h | 14.300ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 5.080m | 3.264ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 5.873m | 3.367ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.744m | 2.783ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 42.990m | 12.355ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 20.050m | 13.321ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 5.515m | 2.870ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 4.618m | 3.578ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 4.847m | 2.245ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 11.343m | 5.731ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 6.264m | 4.185ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 1.823h | 60.000ms | 3 | 5 | 60.00 | ||
| chip_tap_straps_prod | 17.655m | 10.414ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 6.638m | 3.232ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 20.050m | 13.321ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 20.050m | 13.321ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 20.050m | 13.321ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 25.705m | 6.994ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 9.784m | 4.180ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.377h | 44.927ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 13.897m | 4.665ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 26.741m | 8.670ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 24.720m | 9.252ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 24.854m | 9.064ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 20.050m | 13.321ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 42.990m | 12.355ms | 3 | 3 | 100.00 | ||
| chip_sw_rom_ctrl_integrity_check | 12.862m | 8.376ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 17.482m | 9.536ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 2.922m | 4.549ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 17.528m | 11.265ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 13.285m | 4.241ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 14.286m | 4.881ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 13.874m | 4.069ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 14.891m | 5.284ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 12.143m | 4.593ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 12.950m | 4.960ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 6.264m | 4.185ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 1.823h | 60.000ms | 3 | 5 | 60.00 | ||
| chip_tap_straps_prod | 17.655m | 10.414ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 9.292m | 17.307ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 1.934m | 2.258ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 2.397m | 2.784ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 2.354m | 2.587ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 5.452m | 3.609ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 39.550m | 31.427ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 9.292m | 17.307ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.507h | 50.335ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.584h | 48.770ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 19.433m | 9.190ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.642h | 50.037ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 39.550m | 31.427ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 1.941m | 2.089ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 2.264m | 2.890ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 2.257m | 2.487ms | 3 | 3 | 100.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 20.050m | 13.321ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 40.649m | 26.341ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.498m | 3.368ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 42.990m | 12.355ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 11.200m | 5.451ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.263m | 3.156ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 40.649m | 26.341ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.498m | 3.368ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 42.990m | 12.355ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 11.200m | 5.451ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 4.263m | 3.156ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 20.050m | 13.321ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 10.258m | 4.558ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 6.638m | 3.232ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 13.897m | 4.665ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 26.741m | 8.670ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 24.720m | 9.252ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 24.854m | 9.064ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 20.050m | 13.321ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 2.922m | 4.549ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 2.922m | 4.549ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_dai_lock | chip_sw_otp_ctrl_dai_lock | 1.583h | 26.308ms | 1 | 1 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 10.457m | 8.274ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 28.819m | 23.716ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 9.840m | 7.080ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_por_reset | chip_sw_pwrmgr_deep_sleep_por_reset | 12.323m | 9.674ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_por_reset | chip_sw_pwrmgr_normal_sleep_por_reset | 14.565m | 7.481ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 33.778m | 24.400ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 29.440m | 14.093ms | 3 | 3 | 100.00 |
| chip_sw_aon_timer_wdog_bite_reset | 16.808m | 8.140ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 25.705m | 13.517ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 10.994m | 4.786ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 10.457m | 8.274ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 9.506m | 4.058ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 1.106h | 42.151ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 9.974m | 8.106ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 11.146m | 6.581ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 47.013m | 25.614ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 21.416m | 8.299ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_all_reset_reqs | 30.146m | 13.373ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 45.753m | 32.437ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 5.504m | 2.652ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 13.429m | 5.104ms | 98 | 100 | 98.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 12.862m | 8.376ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 12.862m | 8.376ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_all_reset_reqs | 30.146m | 13.373ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 47.013m | 25.614ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_wdog_reset | 10.994m | 4.786ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 11.259m | 6.810ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 9.533m | 5.083ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 8.825m | 6.273ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 6.970m | 4.498ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 34.205m | 13.480ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 5.187m | 3.146ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 13.429m | 5.104ms | 98 | 100 | 98.00 |
| V2 | chip_sw_rstmgr_alert_handler_reset_enables | chip_sw_alert_handler_lpg_reset_toggle | 31.662m | 7.160ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs_0 | 22.455m | 6.128ms | 3 | 3 | 100.00 |
| chip_plic_all_irqs_10 | 12.181m | 4.451ms | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_20 | 14.098m | 4.572ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 5.778m | 3.145ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 5.715m | 3.564ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | rom_e2e_smoke | 1.091h | 15.244ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 14.617m | 7.006ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 9.528m | 3.602ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 7.307m | 3.052ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 5.727m | 3.369ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 11.200m | 5.451ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 13.333m | 5.418ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents_no_scramble | 14.532m | 8.987ms | 3 | 3 | 100.00 |
| chip_sw_sleep_sram_ret_contents_scramble | 11.381m | 6.782ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 17.482m | 9.536ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 13.429m | 5.104ms | 98 | 100 | 98.00 |
| chip_sw_data_integrity_escalation | 17.221m | 6.344ms | 6 | 6 | 100.00 | ||
| V2 | chip_sw_usbdev_mem | chip_sw_usbdev_mem | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_vbus | chip_sw_usbdev_vbus | 3.808m | 2.936ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pullup | chip_sw_usbdev_pullup | 5.369m | 3.262ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_aon_pullup | chip_sw_usbdev_aon_pullup | 7.918m | 4.011ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_sof | chip_sw_usbdev_sof | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_setup_rx | chip_sw_usbdev_setuprx | 9.613m | 4.643ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_config_host | chip_sw_usbdev_config_host | 35.395m | 8.577ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pincfg | chip_sw_usbdev_pincfg | 2.000h | 32.209ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_tx_rx | chip_sw_usbdev_dpi | 55.342m | 11.531ms | 1 | 1 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 6.018m | 3.753ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 11.343m | 5.731ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalation_nmi_reset | chip_sw_alert_handler_escalation_nmi_reset | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_escalation_methods | chip_sw_alert_handler_escalation_methods | 0 | 0 | -- | ||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 13.429m | 5.104ms | 98 | 100 | 98.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 7.628m | 3.183ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 34.205m | 13.480ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 11.657m | 5.408ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 9.565m | 4.127ms | 89 | 90 | 98.89 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 25.865m | 12.794ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 34.358m | 7.562ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 31.662m | 7.160ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_ok | chip_sw_alert_handler_ping_ok | 24.111m | 7.343ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.660h | 254.887ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 38.352m | 16.769ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 26.410m | 13.791ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 9.533m | 5.083ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 10.804m | 4.788ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 11.819m | 6.442ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 1.823h | 60.000ms | 3 | 5 | 60.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 9.292m | 17.307ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_jtag | chip_rv_dm_jtag | 0 | 0 | -- | ||
| V2 | chip_rv_dm_dtm | chip_rv_dm_dtm | 0 | 0 | -- | ||
| V2 | chip_rv_dm_control_status | chip_rv_dm_control_status | 0 | 0 | -- | ||
| V2 | TOTAL | 2638 | 2644 | 99.77 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 8.321m | 3.296ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 3.943h | 72.234ms | 1 | 1 | 100.00 |
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 0 | 3 | 0.00 | ||
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 34.342m | 10.555ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 29.281m | 11.373ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 36.230m | 9.987ms | 1 | 1 | 100.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 44.032m | 33.120ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_inject_dev | 45.249m | 24.234ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_inject_rma | 36.423m | 25.886ms | 1 | 1 | 100.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 1.698h | 25.748ms | 3 | 3 | 100.00 |
| V3 | manuf_cp_unlock_raw | manuf_cp_unlock_raw | 0 | 0 | -- | ||
| V3 | manuf_scrap | manuf_scrap | 0 | 0 | -- | ||
| V3 | manuf_cp_yield_test | manuf_cp_yield_test | 0 | 0 | -- | ||
| V3 | manuf_cp_ast_test_execution | manuf_cp_ast_test_execution | 0 | 0 | -- | ||
| V3 | manuf_cp_device_info_flash_wr | manuf_cp_device_info_flash_wr | 0 | 0 | -- | ||
| V3 | manuf_cp_test_lock | manuf_cp_test_lock | 0 | 0 | -- | ||
| V3 | manuf_ft_exit_token | manuf_ft_exit_token | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization_preop | manuf_ft_sku_individualization_preop | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization | manuf_ft_sku_individualization | 0 | 0 | -- | ||
| V3 | manuf_ft_provision_rma_token_and_personalization | manuf_ft_provision_rma_token_and_personalization | 0 | 0 | -- | ||
| V3 | manuf_ft_load_transport_image | manuf_ft_load_transport_image | 0 | 0 | -- | ||
| V3 | manuf_ft_load_certificates | manuf_ft_load_certificates | 0 | 0 | -- | ||
| V3 | manuf_ft_eom | manuf_ft_eom | 0 | 0 | -- | ||
| V3 | manuf_rma_entry | manuf_rma_entry | 0 | 0 | -- | ||
| V3 | manuf_sram_program_crc_functest | manuf_sram_program_crc_functest | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_normal | chip_sw_adc_ctrl_normal | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_oneshot | chip_sw_adc_ctrl_oneshot | 0 | 0 | -- | ||
| V3 | chip_sw_clkmgr_jitter_cycle_measurements | chip_sw_clkmgr_jitter_frequency | 8.503m | 3.846ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_boot_mode | chip_sw_edn_boot_mode | 10.498m | 2.696ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_auto_mode | chip_sw_edn_auto_mode | 20.041m | 4.848ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_sw_mode | chip_sw_edn_sw_mode | 36.232m | 10.688ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_kat | chip_sw_edn_kat | 11.637m | 3.809ms | 3 | 3 | 100.00 |
| V3 | chip_sw_entropy_src_bypass_mode_health_tests | chip_sw_entropy_src_bypass_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_fips_mode_health_tests | chip_sw_entropy_src_fips_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_validation | chip_sw_entropy_src_validation | 0 | 0 | -- | ||
| V3 | chip_sw_flash_memory_protection | chip_sw_flash_ctrl_mem_protection | 23.031m | 5.591ms | 3 | 3 | 100.00 |
| V3 | chip_sw_hmac_sha2_stress | chip_sw_hmac_sha2_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_stress | chip_sw_hmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_endianness | chip_sw_hmac_endianness | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_secure_wipe | chip_sw_hmac_secure_wipe | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_error_conditions | chip_sw_hmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_speed | chip_sw_i2c_speed | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_override | chip_sw_i2c_override | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_clockstretching | chip_sw_i2c_clockstretching | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_nack | chip_sw_i2c_nack | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_repeatedstart | chip_sw_i2c_repeatedstart | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_attestation | chip_sw_keymgr_derive_attestation | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_sealing | chip_sw_keymgr_derive_sealing | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_sha3_stress | chip_sw_kmac_sha3_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_shake_stress | chip_sw_kmac_shake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_cshake_stress | chip_sw_kmac_cshake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_stress | chip_sw_kmac_kmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_key_sideload | chip_sw_kmac_kmac_key_sideload | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_endianess | chip_sw_kmac_endianess | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_entropy_stress | chip_sw_kmac_entropy_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_error_conditions | chip_sw_kmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_debug_access | chip_sw_lc_ctrl_debug_access | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 4.034m | 2.890ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 12.668m | 5.113ms | 1 | 1 | 100.00 |
| V3 | otp_ctrl_calibration | otp_ctrl_calibration | 0 | 0 | -- | ||
| V3 | otp_ctrl_partition_access_locked | otp_ctrl_partition_access_locked | 0 | 0 | -- | ||
| V3 | otp_ctrl_check_timeout | otp_ctrl_check_timeout | 0 | 0 | -- | ||
| V3 | chip_sw_sensor_ctrl_deep_sleep_wake_up | chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 10.044m | 5.529ms | 3 | 3 | 100.00 |
| V3 | chip_sw_pwrmgr_usb_clk_disabled_when_active | chip_sw_pwrmgr_usb_clk_disabled_when_active | 7.446m | 4.588ms | 3 | 3 | 100.00 |
| V3 | chip_sw_all_resets | chip_sw_pwrmgr_all_reset_reqs | 30.146m | 13.373ms | 3 | 3 | 100.00 |
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_digests | chip_sw_rom_ctrl_digests | 0 | 0 | -- | ||
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 13.429m | 5.104ms | 98 | 100 | 98.00 |
| V3 | tick_configuration | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | counter_wrap | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | chip_sw_spi_device_pass_through_flash_model | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_pass_through | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_configuration | //sw/device/tests:spi_host_config_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_events | chip_sw_spi_host_events | 0 | 0 | -- | ||
| V3 | chip_sw_sram_memset | chip_sw_sram_memset | 0 | 0 | -- | ||
| V3 | chip_sw_sram_readback | chip_sw_sram_readback | 0 | 0 | -- | ||
| V3 | chip_sw_sram_subword_access | chip_sw_sram_subword_access | 0 | 0 | -- | ||
| V3 | chip_sw_uart_parity | chip_sw_uart_parity | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_loopback | chip_sw_uart_line_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_system_loopback | chip_sw_uart_system_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_break | chip_sw_uart_line_break | 0 | 0 | -- | ||
| V3 | chip_sw_uart_watermarks | chip_sw_uart_tx_rx | 12.224m | 4.640ms | 5 | 5 | 100.00 |
| V3 | chip_sw_usbdev_stream | chip_sw_usbdev_stream | 1.217h | 18.172ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usbdev_iso | chip_sw_usbdev_iso | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_mixed | chip_sw_usbdev_mixed | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_suspend_resume | chip_sw_usbdev_suspend_resume | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_reset | chip_sw_usbdev_aon_wake_reset | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_disconnect | chip_sw_usbdev_aon_wake_disconnect | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_toggle_restore | chip_sw_usbdev_toggle_restore | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 34.342m | 10.555ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 29.281m | 11.373ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 36.230m | 9.987ms | 1 | 1 | 100.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 12.397m | 6.505ms | 3 | 3 | 100.00 |
| V3 | TOTAL | 42 | 48 | 87.50 | |||
| Unmapped tests | chip_sival_flash_info_access | 5.283m | 2.776ms | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 12.988m | 5.013ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_ecc_error_vendor_test | 4.972m | 2.716ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq | 1.275h | 17.037ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_rnd | 17.791m | 5.888ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_nmi_irq | 15.635m | 4.877ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_lowpower_cancel | 7.641m | 3.567ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_sleep_wake_5_bug | 10.190m | 5.553ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_address_translation | 5.494m | 2.384ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_lockstep_glitch | 5.974m | 3.398ms | 1 | 3 | 33.33 | ||
| chip_sw_flash_ctrl_write_clear | 6.795m | 3.199ms | 3 | 3 | 100.00 | ||
| TOTAL | 2933 | 2948 | 99.49 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 11 | 11 | 10 | 90.91 |
| V1 | 18 | 18 | 17 | 94.44 |
| V2 | 285 | 270 | 266 | 93.33 |
| V2S | 1 | 1 | 1 | 100.00 |
| V3 | 90 | 22 | 20 | 22.22 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.22 | 95.64 | 94.14 | 95.45 | -- | 95.00 | 97.53 | 99.54 |
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 7 failures:
0.chip_sw_rv_timer_systick_test.101211122307173537228505802633824401854814001964243782178224020347895771129333
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:ec9beb05-e86d-4d71-8cbc-657b4dbe052d
1.chip_sw_rv_timer_systick_test.544519029002178787321362304594847141907117004821575297663996050652557688897
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:aaf92644-68ab-44b0-a14b-359b1218d1dc
... and 1 more failures.
0.chip_sw_power_virus.64897081122526388246908004926686955873373918397023546362694453434947100179306
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
Job ID: smart:2d3988df-3560-4b17-b1dd-81389367877d
1.chip_sw_power_virus.21602950395931647754927427908232266116290675378139320626629404278896214375468
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
Job ID: smart:065e4cb4-f932-437f-b9d0-70cfe6490866
... and 1 more failures.
1.chip_tap_straps_testunlock0.75431844815931046579341515416179768831336782568441909496832938042890257476849
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_testunlock0/latest/run.log
Job ID: smart:dfa6c208-5bb4-4c0f-b603-45c14d0b739e
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 2 failures:
0.chip_sw_rv_core_ibex_lockstep_glitch.35945725056867962477323186259481372523631701681529732678124044731245482376458
Line 791, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
UVM_FATAL @ 2467.550744 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2467.550744 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.chip_sw_rv_core_ibex_lockstep_glitch.64818752534575178982374662408356134038844650645871115115264724929264379230816
Line 785, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
UVM_FATAL @ 3397.862480 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 3397.862480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue has 2 failures:
1.chip_tap_straps_rma.175041557857334040708704552084732492245975141247780396365598277192139402998
Line 5983, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_rma/latest/run.log
UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.chip_tap_straps_rma.14894164431096288525301270062144039722984222560840310559252933345018191525016
Line 6006, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_rma/latest/run.log
UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 2 failures:
70.chip_sw_all_escalation_resets.58820133032917818478481646897140111524391171875688283741776846118376200706005
Line 862, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/70.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 3130.651208 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 3130.651208 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
88.chip_sw_all_escalation_resets.8656503104401197387168625060550679457235235109964202576357596493143928248669
Line 780, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/88.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 2505.655876 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 2505.655876 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
0.chip_csr_aliasing.66607710570639225702339409419261265110877523020748157383471970174985727200875
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
Job ID: smart:884da467-f9f5-499a-a1ce-814375d91dad
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 1 failures:
8.chip_sw_alert_handler_lpg_sleep_mode_alerts.50782701112851330984264483300056367925347629318586805989948472419998480119219
Line 780, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 4292.313544 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003720 MTVAL=40600800
UVM_INFO @ 4292.313544 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---