CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 405983 | 1 | T78 | 5 | T84 | 1455 | T251 | 1 | ||||
rising | 406072 | 1 | T78 | 5 | T84 | 1455 | T251 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1114494 | 1 | T78 | 10 | T84 | 3676 | T251 | 2 | ||||
auto[1] | 9749985 | 1 | T78 | 4518 | T79 | 328 | T80 | 258 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 352288 | 1 | T78 | 7 | T84 | 1302 | T126 | 4 | ||||
rising | 352384 | 1 | T78 | 7 | T84 | 1302 | T126 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1250008 | 1 | T78 | 14 | T84 | 4456 | T126 | 8 | ||||
auto[1] | 10492023 | 1 | T78 | 4612 | T79 | 274 | T80 | 322 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 717077 | 1 | T78 | 16 | T84 | 2310 | T126 | 12 | ||||
rising | 717132 | 1 | T78 | 16 | T84 | 2310 | T126 | 12 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1131990 | 1 | T78 | 32 | T84 | 3921 | T126 | 12 | ||||
auto[1] | 9858205 | 1 | T78 | 4762 | T79 | 364 | T80 | 256 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6861 | 1 | T84 | 1 | T251 | 105 | T485 | 1 | ||||
rising | 6900 | 1 | T84 | 1 | T251 | 106 | T485 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 184285 | 1 | T78 | 99 | T79 | 2 | T80 | 8 | ||||
auto[1] | 13823 | 1 | T84 | 1 | T251 | 280 | T485 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5736 | 1 | T84 | 2 | T452 | 87 | T561 | 1 | ||||
rising | 5764 | 1 | T84 | 2 | T452 | 88 | T561 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 191479 | 1 | T78 | 85 | T79 | 5 | T80 | 9 | ||||
auto[1] | 8541 | 1 | T84 | 2 | T452 | 175 | T561 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 3444 | 1 | T84 | 17 | T561 | 2 | T450 | 1 | ||||
rising | 3464 | 1 | T84 | 17 | T561 | 2 | T450 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 183676 | 1 | T78 | 94 | T79 | 5 | T80 | 3 | ||||
auto[1] | 3756 | 1 | T84 | 17 | T561 | 2 | T450 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 7952 | 1 | T84 | 1 | T252 | 1 | T452 | 97 | ||||
rising | 8006 | 1 | T84 | 1 | T252 | 1 | T452 | 98 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 167244 | 1 | T78 | 88 | T79 | 6 | T80 | 3 | ||||
auto[1] | 23081 | 1 | T84 | 1 | T252 | 1 | T452 | 343 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 4508 | 1 | T84 | 2 | T450 | 2 | T489 | 2 | ||||
rising | 4532 | 1 | T84 | 2 | T450 | 2 | T489 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 185755 | 1 | T78 | 85 | T79 | 12 | T80 | 2 | ||||
auto[1] | 5179 | 1 | T84 | 2 | T450 | 2 | T489 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 7053 | 1 | T84 | 17 | T126 | 5 | T452 | 104 | ||||
rising | 7097 | 1 | T84 | 17 | T126 | 5 | T452 | 105 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 176874 | 1 | T78 | 106 | T79 | 17 | T80 | 4 | ||||
auto[1] | 13504 | 1 | T84 | 18 | T126 | 5 | T452 | 192 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 7187 | 1 | T84 | 65 | T452 | 83 | T561 | 2 | ||||
rising | 7229 | 1 | T84 | 65 | T452 | 83 | T561 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 179696 | 1 | T78 | 91 | T79 | 10 | T80 | 3 | ||||
auto[1] | 15581 | 1 | T84 | 81 | T452 | 102 | T561 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 4919 | 1 | T84 | 2 | T485 | 1 | T452 | 113 | ||||
rising | 4948 | 1 | T84 | 2 | T485 | 1 | T452 | 113 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 187745 | 1 | T78 | 87 | T79 | 10 | T80 | 12 | ||||
auto[1] | 10452 | 1 | T84 | 2 | T485 | 1 | T452 | 179 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 4692 | 1 | T84 | 6 | T561 | 1 | T571 | 98 | ||||
rising | 4729 | 1 | T84 | 6 | T561 | 1 | T571 | 98 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 186007 | 1 | T78 | 100 | T79 | 7 | T80 | 4 | ||||
auto[1] | 9145 | 1 | T84 | 6 | T561 | 1 | T571 | 249 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5438 | 1 | T84 | 1 | T452 | 76 | T561 | 2 | ||||
rising | 5474 | 1 | T84 | 1 | T452 | 76 | T561 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 188679 | 1 | T78 | 94 | T79 | 6 | T80 | 4 | ||||
auto[1] | 8427 | 1 | T84 | 1 | T452 | 84 | T561 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6017 | 1 | T84 | 1 | T561 | 1 | T450 | 28 | ||||
rising | 6042 | 1 | T84 | 1 | T561 | 2 | T450 | 28 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 189776 | 1 | T78 | 94 | T79 | 17 | T80 | 4 | ||||
auto[1] | 7719 | 1 | T84 | 1 | T561 | 2 | T450 | 28 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 15577 | 1 | T80 | 1 | T84 | 34 | T251 | 21 | ||||
rising | 15612 | 1 | T80 | 1 | T84 | 34 | T251 | 21 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1490961 | 1 | T78 | 650 | T79 | 37 | T80 | 44 | ||||
auto[1] | 16303 | 1 | T80 | 1 | T84 | 34 | T251 | 22 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 7109 | 1 | T84 | 1 | T486 | 1 | T561 | 1 | ||||
rising | 7156 | 1 | T80 | 1 | T84 | 1 | T486 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 191604 | 1 | T78 | 109 | T79 | 9 | T80 | 6 | ||||
auto[1] | 15309 | 1 | T80 | 1 | T84 | 1 | T486 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 8225 | 1 | T84 | 83 | T571 | 93 | T450 | 9 | ||||
rising | 8265 | 1 | T84 | 83 | T252 | 1 | T571 | 93 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 175550 | 1 | T78 | 87 | T79 | 7 | T80 | 5 | ||||
auto[1] | 21059 | 1 | T84 | 262 | T252 | 1 | T571 | 345 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 2410 | 1 | T84 | 17 | T251 | 27 | T485 | 2 | ||||
rising | 2429 | 1 | T84 | 17 | T251 | 27 | T485 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 198620 | 1 | T78 | 91 | T79 | 4 | T80 | 5 | ||||
auto[1] | 2572 | 1 | T84 | 17 | T251 | 27 | T485 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 7770 | 1 | T80 | 1 | T84 | 8 | T452 | 115 | ||||
rising | 7815 | 1 | T80 | 1 | T84 | 8 | T452 | 116 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 193853 | 1 | T78 | 109 | T79 | 9 | T80 | 8 | ||||
auto[1] | 14661 | 1 | T80 | 1 | T84 | 8 | T452 | 276 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6078 | 1 | T80 | 1 | T84 | 83 | T126 | 5 | ||||
rising | 6123 | 1 | T80 | 1 | T84 | 83 | T126 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 174698 | 1 | T78 | 95 | T79 | 9 | T80 | 3 | ||||
auto[1] | 13141 | 1 | T80 | 1 | T84 | 177 | T126 | 5 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 7128 | 1 | T84 | 7 | T126 | 1 | T252 | 1 | ||||
rising | 7159 | 1 | T84 | 7 | T126 | 1 | T252 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 176542 | 1 | T78 | 97 | T79 | 13 | T80 | 5 | ||||
auto[1] | 13124 | 1 | T84 | 8 | T126 | 1 | T252 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6100 | 1 | T84 | 1 | T251 | 129 | T486 | 1 | ||||
rising | 6131 | 1 | T84 | 1 | T251 | 129 | T486 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 192622 | 1 | T78 | 94 | T79 | 10 | T80 | 2 | ||||
auto[1] | 9158 | 1 | T84 | 1 | T251 | 249 | T486 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 2444 | 1 | T84 | 1 | T561 | 3 | T450 | 42 | ||||
rising | 2467 | 1 | T84 | 1 | T561 | 3 | T450 | 42 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 191893 | 1 | T78 | 100 | T79 | 4 | T80 | 7 | ||||
auto[1] | 2613 | 1 | T84 | 1 | T561 | 3 | T450 | 45 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6188 | 1 | T84 | 71 | T251 | 94 | T485 | 1 | ||||
rising | 6230 | 1 | T84 | 71 | T251 | 95 | T485 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 174207 | 1 | T78 | 90 | T79 | 5 | T80 | 2 | ||||
auto[1] | 9125 | 1 | T84 | 107 | T251 | 190 | T485 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 39727 | 1 | T408 | 941 | T578 | 1643 | T583 | 568 | ||||
rising | 39733 | 1 | T408 | 941 | T578 | 1644 | T583 | 567 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 86228 | 1 | T408 | 2187 | T578 | 3659 | T583 | 1379 | ||||
auto[1] | 77120 | 1 | T408 | 1754 | T578 | 3239 | T583 | 1142 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 22884 | 1 | T408 | 607 | T578 | 952 | T583 | 367 | ||||
rising | 22873 | 1 | T408 | 607 | T578 | 952 | T583 | 366 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 134933 | 1 | T408 | 3168 | T578 | 5702 | T583 | 2027 | ||||
auto[1] | 28415 | 1 | T408 | 773 | T578 | 1196 | T583 | 494 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 22884 | 1 | T408 | 607 | T578 | 952 | T583 | 367 | ||||
rising | 22873 | 1 | T408 | 607 | T578 | 952 | T583 | 366 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 134933 | 1 | T408 | 3168 | T578 | 5702 | T583 | 2027 | ||||
auto[1] | 28415 | 1 | T408 | 773 | T578 | 1196 | T583 | 494 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 4179 | 1 | T408 | 180 | T578 | 138 | T583 | 126 | ||||
rising | 4174 | 1 | T408 | 180 | T578 | 138 | T583 | 126 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 157328 | 1 | T408 | 3703 | T578 | 6664 | T583 | 2336 | ||||
auto[1] | 6020 | 1 | T408 | 238 | T578 | 234 | T583 | 185 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 117538 | 1 | T408 | 2 | T578 | 2 | T579 | 1 | ||||
rising | 117562 | 1 | T408 | 2 | T578 | 2 | T579 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 39210039 | 1 | T4 | 11038 | T5 | 11572 | T6 | 7062 | ||||
auto[1] | 642299 | 1 | T408 | 2 | T578 | 2 | T579 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 40246 | 1 | T408 | 972 | T578 | 1720 | T583 | 606 | ||||
rising | 40254 | 1 | T408 | 972 | T578 | 1720 | T583 | 607 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 86292 | 1 | T408 | 2167 | T578 | 3592 | T583 | 1393 | ||||
auto[1] | 77056 | 1 | T408 | 1774 | T578 | 3306 | T583 | 1128 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 34197 | 1 | T408 | 820 | T578 | 1469 | T583 | 519 | ||||
rising | 34191 | 1 | T408 | 819 | T578 | 1469 | T583 | 518 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 114524 | 1 | T408 | 2770 | T578 | 4817 | T583 | 1786 | ||||
auto[1] | 48824 | 1 | T408 | 1171 | T578 | 2081 | T583 | 735 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 2495 | 1 | T561 | 3 | T450 | 2 | T575 | 1 | ||||
rising | 2518 | 1 | T561 | 3 | T450 | 2 | T575 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 196978 | 1 | T78 | 109 | T79 | 11 | T80 | 5 | ||||
auto[1] | 2638 | 1 | T561 | 4 | T450 | 2 | T575 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 3773 | 1 | T84 | 2 | T485 | 1 | T570 | 45 | ||||
rising | 3795 | 1 | T84 | 2 | T485 | 1 | T570 | 45 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 195407 | 1 | T78 | 98 | T79 | 5 | T80 | 7 | ||||
auto[1] | 4047 | 1 | T84 | 2 | T485 | 1 | T570 | 49 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 8237 | 1 | T84 | 3 | T251 | 30 | T570 | 101 | ||||
rising | 8290 | 1 | T84 | 3 | T251 | 31 | T485 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 178658 | 1 | T78 | 98 | T79 | 7 | T80 | 9 | ||||
auto[1] | 29564 | 1 | T84 | 3 | T251 | 432 | T485 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 7465 | 1 | T84 | 1 | T570 | 68 | T448 | 101 | ||||
rising | 7513 | 1 | T84 | 1 | T570 | 69 | T448 | 102 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 168347 | 1 | T78 | 78 | T79 | 6 | T80 | 6 | ||||
auto[1] | 19971 | 1 | T84 | 1 | T570 | 433 | T448 | 262 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 2473 | 1 | T84 | 1 | T126 | 1 | T452 | 44 | ||||
rising | 2492 | 1 | T84 | 1 | T126 | 1 | T452 | 44 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 183651 | 1 | T78 | 89 | T79 | 5 | T80 | 4 | ||||
auto[1] | 2628 | 1 | T84 | 1 | T126 | 1 | T452 | 45 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 6444 | 1 | T84 | 1 | T561 | 2 | T450 | 2 | ||||
rising | 6484 | 1 | T84 | 1 | T561 | 2 | T450 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 178156 | 1 | T78 | 87 | T79 | 5 | T80 | 1 | ||||
auto[1] | 11709 | 1 | T84 | 1 | T561 | 2 | T450 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 9008 | 1 | T251 | 95 | T126 | 3 | T448 | 60 | ||||
rising | 9057 | 1 | T251 | 95 | T126 | 3 | T448 | 60 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 180625 | 1 | T78 | 84 | T79 | 4 | T80 | 7 | ||||
auto[1] | 19517 | 1 | T251 | 283 | T126 | 3 | T448 | 98 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 5007 | 1 | T84 | 3 | T485 | 1 | T486 | 1 | ||||
rising | 5045 | 1 | T84 | 3 | T485 | 1 | T486 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 184868 | 1 | T78 | 91 | T79 | 5 | T80 | 5 | ||||
auto[1] | 10046 | 1 | T84 | 3 | T485 | 1 | T486 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 22244 | 1 | T79 | 2 | T84 | 34 | T251 | 37 | ||||
rising | 22273 | 1 | T79 | 2 | T84 | 34 | T251 | 37 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1481528 | 1 | T78 | 681 | T79 | 39 | T80 | 44 | ||||
auto[1] | 23304 | 1 | T79 | 2 | T84 | 34 | T251 | 39 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 8168 | 1 | T84 | 1 | T452 | 113 | T561 | 1 | ||||
rising | 8212 | 1 | T84 | 1 | T485 | 1 | T452 | 113 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 185010 | 1 | T78 | 82 | T79 | 5 | T80 | 4 | ||||
auto[1] | 15164 | 1 | T84 | 1 | T485 | 1 | T452 | 240 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 4862 | 1 | T84 | 115 | T570 | 122 | T561 | 1 | ||||
rising | 4890 | 1 | T84 | 115 | T570 | 123 | T561 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 188768 | 1 | T78 | 95 | T79 | 1 | T80 | 4 | ||||
auto[1] | 7596 | 1 | T84 | 216 | T570 | 218 | T561 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 197864 | 1 | T126 | 514 | T485 | 83 | T486 | 34 | ||||
rising | 197864 | 1 | T126 | 515 | T485 | 84 | T486 | 34 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 1781338 | 1 | T126 | 4733 | T485 | 648 | T486 | 353 | ||||
auto[1] | 222801 | 1 | T126 | 575 | T485 | 91 | T486 | 39 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 491983 | 1 | T126 | 1296 | T485 | 175 | T486 | 95 | ||||
rising | 491977 | 1 | T126 | 1296 | T485 | 175 | T486 | 94 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 889716 | 1 | T126 | 2342 | T485 | 304 | T486 | 155 | ||||
auto[1] | 1114423 | 1 | T126 | 2966 | T485 | 435 | T486 | 237 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
falling | 491983 | 1 | T126 | 1296 | T485 | 175 | T486 | 95 | ||||
rising | 491977 | 1 | T126 | 1296 | T485 | 175 | T486 | 94 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 889716 | 1 | T126 | 2342 | T485 | 304 | T486 | 155 | ||||
auto[1] | 1114423 | 1 | T126 | 2966 | T485 | 435 | T486 | 237 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |