Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.19	95.50	94.17	95.48		94.88	97.53	99.57

Total tests in report: 2934

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
40.10	40.10	45.21	45.21	46.73	46.73	27.36	27.36			63.28	63.28	57.87	57.87	0.14	0.14	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2741812885
47.34	7.24	58.17	12.97	57.99	11.26	33.62	6.26			75.46	12.18	57.87	0.00	0.90	0.76	/workspace/coverage/default/2.chip_jtag_csr_rw.1115333914
53.99	6.65	58.41	0.24	61.35	3.36	34.57	0.95			75.89	0.43	57.87	0.00	35.84	34.93	/workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.869576914
60.08	6.09	61.92	3.51	65.09	3.74	35.66	1.09			78.79	2.90	83.04	25.17	35.97	0.13	/workspace/coverage/default/1.chip_jtag_csr_rw.469539723
64.07	3.99	68.01	6.09	66.59	1.50	39.38	3.72			78.88	0.09	83.04	0.00	48.51	12.55	/workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.841454977
67.95	3.88	75.56	7.55	72.41	5.82	44.48	5.09			82.05	3.17	84.62	1.57	48.57	0.06	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1506769740
71.12	3.17	80.68	5.12	76.30	3.89	48.14	3.66			83.85	1.80	89.16	4.55	48.57	0.00	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.218471240
73.91	2.80	80.68	0.00	76.30	0.00	64.91	16.77			83.85	0.00	89.16	0.00	48.57	0.00	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3741061646
76.06	2.15	80.68	0.00	76.30	0.00	64.91	0.00			83.85	0.00	89.16	0.00	61.49	12.91	/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1810312691
78.10	2.04	80.79	0.11	76.40	0.10	76.19	11.28			84.02	0.17	89.69	0.52	61.53	0.05	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1848249761
79.76	1.66	84.24	3.45	78.45	2.05	78.25	2.06			86.41	2.39	89.69	0.00	61.53	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.2103778653
81.33	1.57	84.24	0.00	78.45	0.00	78.25	0.00			86.41	0.00	89.69	0.00	70.96	9.42	/workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.1207389720
82.58	1.25	84.24	0.00	78.45	0.00	78.28	0.03			86.41	0.00	89.69	0.00	78.40	7.45	/workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.648644490
83.56	0.98	85.30	1.05	79.30	0.85	79.62	1.34			87.29	0.88	91.43	1.75	78.40	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2693189901
84.52	0.96	85.30	0.00	79.71	0.41	79.62	0.00			87.34	0.05	91.43	0.00	83.69	5.29	/workspace/coverage/cover_reg_top/81.xbar_access_same_device.1103879212
85.45	0.94	86.86	1.56	80.83	1.12	81.30	1.68			88.61	1.27	91.43	0.00	83.69	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.1905141685
86.35	0.90	88.19	1.33	81.66	0.84	83.12	1.83			89.70	1.09	91.61	0.17	83.84	0.15	/workspace/coverage/default/90.chip_sw_all_escalation_resets.3759087986
87.24	0.88	89.25	1.06	84.25	2.59	83.37	0.25			90.39	0.69	91.61	0.00	84.56	0.72	/workspace/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.3248353242
87.97	0.73	89.54	0.30	84.36	0.11	83.38	0.01			90.50	0.11	95.45	3.85	84.56	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3069774496
88.55	0.58	90.12	0.58	84.60	0.24	85.75	2.37			90.61	0.11	95.63	0.17	84.56	0.00	/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2127810090
89.12	0.58	91.24	1.12	85.56	0.96	85.88	0.13			91.86	1.25	95.63	0.00	84.56	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.2612310478
89.69	0.57	91.24	0.00	85.56	0.00	85.88	0.00			91.86	0.00	95.63	0.00	87.97	3.41	/workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.3746705666
90.20	0.51	91.24	0.01	85.71	0.16	86.57	0.69			91.89	0.03	95.63	0.00	90.15	2.19	/workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.543982959
90.71	0.50	92.05	0.81	86.61	0.89	87.10	0.53			92.69	0.80	95.63	0.00	90.15	0.00	/workspace/coverage/default/1.chip_sw_gpio_smoketest.1229682982
91.16	0.46	92.05	0.00	86.61	0.00	87.10	0.00			92.69	0.00	95.63	0.00	92.89	2.74	/workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.1786437927
91.58	0.41	92.08	0.03	86.65	0.05	87.80	0.70			92.69	0.00	95.63	0.00	94.60	1.70	/workspace/coverage/default/2.chip_sw_alert_test.1925493027
91.95	0.38	92.85	0.77	87.18	0.53	87.94	0.14			93.53	0.84	95.63	0.00	94.60	0.00	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2338876244
92.29	0.34	92.86	0.01	87.18	0.01	89.94	2.00			93.53	0.00	95.63	0.00	94.60	0.00	/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3054463902
92.62	0.33	92.86	0.01	89.02	1.84	89.94	0.00			93.53	0.00	95.63	0.00	94.76	0.16	/workspace/coverage/cover_reg_top/6.chip_tl_errors.976895966
92.89	0.27	93.66	0.80	89.22	0.19	90.10	0.17			93.61	0.09	95.98	0.35	94.76	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1674197163
93.15	0.26	93.66	0.00	89.27	0.05	90.10	0.00			93.61	0.00	95.98	0.00	96.26	1.50	/workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.320964778
93.38	0.23	93.88	0.22	90.27	1.00	90.15	0.05			93.70	0.09	95.98	0.00	96.26	0.00	/workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.3435256252
93.53	0.15	94.13	0.24	90.59	0.32	90.50	0.35			93.70	0.00	95.98	0.00	96.26	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.315169614
93.68	0.15	94.13	0.00	90.59	0.00	91.41	0.91			93.70	0.00	95.98	0.00	96.26	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3613559105
93.82	0.14	94.13	0.00	90.60	0.01	91.41	0.00			93.70	0.00	95.98	0.00	97.12	0.86	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.4280826743
93.96	0.14	94.13	0.00	90.60	0.00	92.12	0.71			93.70	0.00	95.98	0.00	97.25	0.13	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1961964708
94.08	0.12	94.13	0.00	90.64	0.04	92.12	0.00			93.74	0.03	95.98	0.00	97.87	0.62	/workspace/coverage/cover_reg_top/91.xbar_random_large_delays.478615008
94.19	0.11	94.13	0.00	90.94	0.30	92.13	0.01			94.08	0.34	95.98	0.00	97.87	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3341094998
94.28	0.10	94.13	0.00	91.49	0.55	92.13	0.00			94.08	0.00	95.98	0.00	97.90	0.02	/workspace/coverage/cover_reg_top/14.chip_tl_errors.459526558
94.38	0.09	94.13	0.01	91.51	0.02	92.64	0.51			94.10	0.02	95.98	0.00	97.90	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3583676130
94.46	0.08	94.20	0.07	91.56	0.05	92.65	0.01			94.12	0.02	96.33	0.35	97.90	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.2200030901
94.54	0.08	94.20	0.00	91.56	0.00	93.11	0.46			94.12	0.00	96.33	0.00	97.90	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1992057538
94.60	0.07	94.27	0.07	91.58	0.01	93.23	0.11			94.14	0.02	96.50	0.17	97.91	0.01	/workspace/coverage/default/97.chip_sw_all_escalation_resets.2239130287
94.67	0.07	94.27	0.00	91.76	0.19	93.23	0.00			94.35	0.21	96.50	0.00	97.91	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2752973988
94.74	0.06	94.35	0.08	91.82	0.06	93.24	0.01			94.40	0.05	96.68	0.17	97.92	0.01	/workspace/coverage/default/45.chip_sw_all_escalation_resets.3839263860
94.79	0.06	94.35	0.00	91.88	0.06	93.24	0.00			94.42	0.02	96.68	0.00	98.20	0.28	/workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.446454425
94.85	0.05	94.35	0.00	92.20	0.31	93.24	0.00			94.42	0.00	96.68	0.00	98.20	0.00	/workspace/coverage/cover_reg_top/18.chip_tl_errors.1313803923
94.90	0.05	94.42	0.07	92.34	0.14	93.24	0.00			94.52	0.10	96.68	0.00	98.20	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.2156580801
94.95	0.05	94.43	0.01	92.38	0.04	93.29	0.05			94.54	0.02	96.85	0.17	98.20	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3162385709
95.00	0.05	94.43	0.00	92.40	0.02	93.53	0.24			94.56	0.02	96.85	0.00	98.21	0.01	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2976212468
95.04	0.04	94.43	0.00	92.40	0.00	93.75	0.22			94.56	0.00	96.85	0.00	98.25	0.04	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2599135383
95.08	0.04	94.43	0.00	92.55	0.15	93.75	0.00			94.60	0.05	96.85	0.00	98.30	0.05	/workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.2965317953
95.12	0.04	94.46	0.03	92.56	0.01	93.76	0.01			94.61	0.01	97.03	0.17	98.31	0.01	/workspace/coverage/default/93.chip_sw_all_escalation_resets.1634195664
95.16	0.04	94.49	0.03	92.61	0.05	93.86	0.11			94.65	0.03	97.03	0.00	98.31	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1857915345
95.19	0.04	94.50	0.01	92.62	0.01	93.87	0.01			94.65	0.01	97.20	0.17	98.32	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.1111509190
95.23	0.04	94.50	0.01	92.63	0.01	93.88	0.01			94.66	0.01	97.38	0.17	98.33	0.01	/workspace/coverage/default/22.chip_sw_all_escalation_resets.323738817
95.27	0.04	94.50	0.00	92.63	0.00	93.92	0.04			94.66	0.00	97.55	0.17	98.33	0.00	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.1029348302
95.30	0.03	94.50	0.00	92.81	0.18	93.92	0.00			94.66	0.00	97.55	0.00	98.33	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.2587751003
95.32	0.03	94.54	0.04	92.92	0.11	93.94	0.03			94.66	0.00	97.55	0.00	98.33	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.821961798
95.35	0.03	94.54	0.00	92.92	0.00	94.11	0.16			94.66	0.00	97.55	0.00	98.33	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3291475596
95.38	0.03	94.60	0.06	92.95	0.03	94.13	0.02			94.71	0.05	97.55	0.00	98.33	0.00	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.107377021
95.40	0.03	94.68	0.07	92.95	0.00	94.20	0.08			94.72	0.01	97.55	0.00	98.33	0.00	/workspace/coverage/default/4.chip_tap_straps_testunlock0.1521567859
95.43	0.02	94.68	0.00	93.00	0.05	94.20	0.00			94.72	0.00	97.55	0.00	98.43	0.09	/workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.2569442251
95.45	0.02	94.68	0.00	93.00	0.00	94.34	0.14			94.72	0.00	97.55	0.00	98.43	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.565753295
95.47	0.02	94.68	0.00	93.00	0.00	94.47	0.13			94.72	0.00	97.55	0.00	98.43	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3501308662
95.49	0.02	94.68	0.00	93.02	0.02	94.47	0.00			94.72	0.00	97.55	0.00	98.53	0.11	/workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.1026128222
95.52	0.02	94.71	0.03	93.03	0.01	94.53	0.06			94.73	0.02	97.55	0.00	98.53	0.00	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2025074902
95.54	0.02	94.71	0.00	93.15	0.11	94.53	0.00			94.73	0.00	97.55	0.00	98.54	0.01	/workspace/coverage/cover_reg_top/1.chip_tl_errors.992143573
95.56	0.02	94.76	0.05	93.19	0.05	94.54	0.01			94.75	0.02	97.55	0.00	98.54	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.183267399
95.57	0.02	94.76	0.00	93.19	0.00	94.65	0.11			94.75	0.00	97.55	0.00	98.54	0.00	/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.847778894
95.59	0.02	94.80	0.04	93.23	0.04	94.65	0.00			94.77	0.02	97.55	0.00	98.54	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2762776240
95.61	0.02	94.80	0.00	93.23	0.00	94.75	0.10			94.77	0.00	97.55	0.00	98.54	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3290296381
95.62	0.01	94.80	0.00	93.23	0.00	94.84	0.09			94.77	0.00	97.55	0.00	98.54	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1995335993
95.64	0.01	94.81	0.01	93.25	0.02	94.88	0.04			94.79	0.02	97.55	0.00	98.54	0.00	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.3009630711
95.65	0.01	94.81	0.00	93.28	0.02	94.93	0.05			94.79	0.00	97.55	0.00	98.54	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.4271754057
95.66	0.01	94.81	0.00	93.28	0.01	94.93	0.00			94.79	0.00	97.55	0.00	98.61	0.07	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.3717231120
95.67	0.01	94.81	0.00	93.35	0.07	94.93	0.00			94.79	0.00	97.55	0.00	98.61	0.00	/workspace/coverage/cover_reg_top/2.chip_tl_errors.1700216287
95.69	0.01	94.81	0.00	93.41	0.07	94.93	0.00			94.79	0.00	97.55	0.00	98.61	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.111887561
95.70	0.01	94.81	0.00	93.48	0.07	94.93	0.00			94.79	0.00	97.55	0.00	98.61	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.210855181
95.71	0.01	94.82	0.01	93.52	0.04	94.94	0.01			94.80	0.01	97.55	0.00	98.61	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3835619863
95.72	0.01	94.82	0.00	93.56	0.04	94.94	0.00			94.80	0.00	97.55	0.00	98.63	0.01	/workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.112412846
95.73	0.01	94.82	0.00	93.57	0.01	94.94	0.00			94.80	0.00	97.55	0.00	98.67	0.05	/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2109033507
95.73	0.01	94.82	0.00	93.57	0.00	95.00	0.05			94.80	0.00	97.55	0.00	98.67	0.00	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.427838268
95.74	0.01	94.83	0.01	93.60	0.03	95.01	0.01			94.80	0.00	97.55	0.00	98.67	0.00	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3539519824
95.75	0.01	94.85	0.02	93.60	0.01	95.01	0.01			94.82	0.02	97.55	0.00	98.67	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2393098891
95.76	0.01	94.85	0.00	93.65	0.05	95.01	0.00			94.82	0.00	97.55	0.00	98.67	0.00	/workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.1859104595
95.77	0.01	94.85	0.00	93.65	0.00	95.06	0.05			94.82	0.00	97.55	0.00	98.67	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.454894842
95.78	0.01	94.85	0.00	93.69	0.04	95.06	0.00			94.82	0.01	97.55	0.00	98.67	0.00	/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.374199590
95.78	0.01	94.87	0.02	93.70	0.01	95.06	0.01			94.84	0.02	97.55	0.00	98.67	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1436952327
95.79	0.01	94.87	0.00	93.74	0.04	95.06	0.00			94.84	0.00	97.55	0.00	98.67	0.00	/workspace/coverage/default/1.chip_sw_gpio.477376051
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96.04	0.01	94.91	0.00	94.02	0.00	95.41	0.00			94.86	0.00	97.55	0.00	99.47	0.01	/workspace/coverage/default/59.chip_sw_all_escalation_resets.3106248216
96.04	0.01	94.91	0.00	94.02	0.00	95.41	0.00			94.86	0.00	97.55	0.00	99.48	0.01	/workspace/coverage/default/61.chip_sw_all_escalation_resets.2061317350
96.04	0.01	94.91	0.00	94.02	0.00	95.41	0.00			94.86	0.00	97.55	0.00	99.49	0.01	/workspace/coverage/default/62.chip_sw_all_escalation_resets.3614388700
96.04	0.01	94.91	0.00	94.02	0.00	95.41	0.00			94.86	0.00	97.55	0.00	99.51	0.01	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2078798808
96.04	0.01	94.91	0.00	94.02	0.00	95.41	0.00			94.86	0.00	97.55	0.00	99.52	0.01	/workspace/coverage/default/79.chip_sw_all_escalation_resets.3850867373
96.05	0.01	94.91	0.00	94.02	0.00	95.41	0.00			94.86	0.00	97.55	0.00	99.53	0.01	/workspace/coverage/default/8.chip_sw_all_escalation_resets.2591318
96.05	0.01	94.91	0.00	94.02	0.00	95.41	0.00			94.86	0.00	97.55	0.00	99.54	0.01	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3063452643
96.05	0.01	94.91	0.00	94.02	0.00	95.41	0.00			94.86	0.00	97.55	0.00	99.55	0.01	/workspace/coverage/default/94.chip_sw_all_escalation_resets.4287993887
96.05	0.01	94.91	0.00	94.02	0.00	95.41	0.00			94.86	0.00	97.55	0.00	99.57	0.01	/workspace/coverage/default/96.chip_sw_all_escalation_resets.1667528502
96.05	0.01	94.91	0.00	94.03	0.01	95.41	0.00			94.86	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/25.chip_tl_errors.2044924098
96.06	0.01	94.91	0.00	94.04	0.01	95.41	0.00			94.86	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3094453484
96.06	0.01	94.91	0.00	94.05	0.01	95.41	0.00			94.86	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1171200977
96.06	0.01	94.91	0.00	94.06	0.01	95.41	0.00			94.86	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.3220443346
96.06	0.01	94.92	0.01	94.07	0.01	95.41	0.00			94.86	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/2.chip_sw_pattgen_ios.407080439
96.06	0.01	94.92	0.01	94.07	0.00	95.41	0.01			94.86	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/55.chip_sw_all_escalation_resets.97108754
96.06	0.01	94.92	0.00	94.07	0.00	95.42	0.01			94.86	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1413833064
96.07	0.01	94.92	0.00	94.07	0.00	95.43	0.01			94.86	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.3633109922
96.07	0.01	94.93	0.01	94.07	0.00	95.43	0.01			94.86	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_power_idle_load.487386809
96.07	0.01	94.93	0.00	94.07	0.00	95.43	0.00			94.86	0.01	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.4170965641
96.07	0.01	94.93	0.00	94.07	0.00	95.43	0.00			94.87	0.01	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3590469343
96.07	0.01	94.93	0.00	94.07	0.00	95.43	0.00			94.88	0.01	97.55	0.00	99.57	0.00	/workspace/coverage/default/4.chip_tap_straps_dev.1097430371
96.07	0.01	94.93	0.00	94.08	0.01	95.43	0.00			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/0.xbar_same_source.3361578764
96.07	0.01	94.93	0.00	94.08	0.01	95.43	0.00			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/1.xbar_stress_all.3045839011
96.08	0.01	94.93	0.00	94.09	0.01	95.43	0.00			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2636993378
96.08	0.01	94.93	0.00	94.10	0.01	95.43	0.00			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/11.chip_tl_errors.2789445360
96.08	0.01	94.93	0.00	94.11	0.01	95.43	0.00			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1573020735
96.08	0.01	94.93	0.00	94.11	0.01	95.43	0.00			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2033371929
96.08	0.01	94.93	0.00	94.12	0.01	95.43	0.00			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.253074386
96.08	0.01	94.93	0.00	94.13	0.01	95.43	0.00			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/2.chip_sw_gpio.370235338
96.08	0.01	94.93	0.00	94.13	0.00	95.44	0.01			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1541414669
96.08	0.01	94.93	0.00	94.13	0.00	95.45	0.01			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4256645251
96.08	0.01	94.93	0.00	94.13	0.00	95.45	0.01			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2391415810
96.08	0.01	94.93	0.00	94.13	0.00	95.46	0.01			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.743382989
96.09	0.01	94.93	0.00	94.13	0.00	95.46	0.01			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.189059154
96.09	0.01	94.93	0.00	94.13	0.00	95.47	0.01			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2347176743
96.09	0.01	94.93	0.00	94.13	0.00	95.47	0.01			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1993868908
96.09	0.01	94.93	0.00	94.13	0.01	95.47	0.00			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_rw.3500594068
96.09	0.01	94.93	0.00	94.13	0.01	95.47	0.00			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.2467887794
96.09	0.01	94.93	0.00	94.14	0.01	95.47	0.00			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3828288885
96.09	0.01	94.93	0.00	94.14	0.01	95.47	0.00			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.3407919181
96.09	0.01	94.93	0.00	94.14	0.01	95.47	0.00			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.3291519530
96.09	0.01	94.93	0.00	94.15	0.01	95.47	0.00			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.2542017067
96.09	0.01	94.93	0.00	94.15	0.01	95.47	0.00			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.4055105487
96.09	0.01	94.93	0.00	94.16	0.01	95.47	0.00			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.1676797587
96.09	0.01	94.93	0.00	94.16	0.01	95.47	0.00			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2261938979
96.09	0.01	94.93	0.00	94.16	0.01	95.47	0.00			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3144897835
96.09	0.01	94.93	0.00	94.17	0.01	95.47	0.00			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.4249945158
96.09	0.01	94.93	0.00	94.17	0.01	95.47	0.00			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.18982060
96.09	0.01	94.93	0.00	94.17	0.00	95.47	0.01			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.29503889
96.10	0.01	94.93	0.00	94.17	0.00	95.48	0.01			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.4188531654
96.10	0.01	94.93	0.00	94.17	0.00	95.48	0.01			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2318497950
96.10	0.01	94.93	0.00	94.17	0.00	95.48	0.01			94.88	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1528213941

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.1296251950
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2017418849
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.3954828410
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.897937471
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1429423372
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2498210384
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.333532357
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1406053125
/workspace/coverage/cover_reg_top/0.xbar_error_random.3246426263
/workspace/coverage/cover_reg_top/0.xbar_random.1426782665
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.1319102931
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1807873172
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.912407139
/workspace/coverage/cover_reg_top/0.xbar_smoke.4190433362
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3073133884
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.69975456
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2967606975
/workspace/coverage/cover_reg_top/0.xbar_stress_all.299317539
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.1320594252
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.4013196777
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.922982203
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.539707125
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.2919493669
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1088169426
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1244310676
/workspace/coverage/cover_reg_top/1.chip_csr_rw.1447656416
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2314972092
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.964730632
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1626109324
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.2302879669
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3852646304
/workspace/coverage/cover_reg_top/1.xbar_error_random.3640050003
/workspace/coverage/cover_reg_top/1.xbar_random.925135331
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.1400468212
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1462815064
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3715703112
/workspace/coverage/cover_reg_top/1.xbar_same_source.3369851080
/workspace/coverage/cover_reg_top/1.xbar_smoke.1864077440
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.264248791
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1221000318
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2319955628
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.2616309414
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1572450778
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.1785146604
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2155654675
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.1893498563
/workspace/coverage/cover_reg_top/10.chip_csr_rw.208586422
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.4147362271
/workspace/coverage/cover_reg_top/10.chip_tl_errors.2052047361
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1159873763
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1552965060
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.892064553
/workspace/coverage/cover_reg_top/10.xbar_error_random.2225499356
/workspace/coverage/cover_reg_top/10.xbar_random.2451605505
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.882487779
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1263166046
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.3014516215
/workspace/coverage/cover_reg_top/10.xbar_same_source.3460515001
/workspace/coverage/cover_reg_top/10.xbar_smoke.2412077836
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3880976773
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1087466104
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2223353598
/workspace/coverage/cover_reg_top/10.xbar_stress_all.1179334196
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1531711590
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3095147843
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.480394316
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.3936923441
/workspace/coverage/cover_reg_top/11.chip_csr_rw.3024965380
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.1238978359
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2522966910
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.1554808617
/workspace/coverage/cover_reg_top/11.xbar_error_random.757678711
/workspace/coverage/cover_reg_top/11.xbar_random.33353653
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.52647391
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.629495289
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.485661671
/workspace/coverage/cover_reg_top/11.xbar_same_source.4063853687
/workspace/coverage/cover_reg_top/11.xbar_smoke.496862497
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.1364052432
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.744634262
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3761399575
/workspace/coverage/cover_reg_top/11.xbar_stress_all.4117855892
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2642322866
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.942752933
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1398756484
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.3033342159
/workspace/coverage/cover_reg_top/12.chip_csr_rw.89603990
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3005027208
/workspace/coverage/cover_reg_top/12.chip_tl_errors.2303651228
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.373143085
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.240477155
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1875722578
/workspace/coverage/cover_reg_top/12.xbar_error_random.3341740378
/workspace/coverage/cover_reg_top/12.xbar_random.1060946550
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1943119498
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.118805821
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1167981623
/workspace/coverage/cover_reg_top/12.xbar_same_source.3492312519
/workspace/coverage/cover_reg_top/12.xbar_smoke.3204619821
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.1665660965
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2449821533
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.406030543
/workspace/coverage/cover_reg_top/12.xbar_stress_all.3932622688
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.3707836883
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1975247872
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.617002677
/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.3741661401
/workspace/coverage/cover_reg_top/13.chip_csr_rw.387372817
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.47200265
/workspace/coverage/cover_reg_top/13.chip_tl_errors.2360084299
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.667131413
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2095395155
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.927278726
/workspace/coverage/cover_reg_top/13.xbar_error_random.2369913450
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/workspace/coverage/default/33.chip_sw_all_escalation_resets.3400741809
/workspace/coverage/default/35.chip_sw_all_escalation_resets.3672647639
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3552506604
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/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.548085040
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1590534177
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1481824414
/workspace/coverage/default/4.chip_sw_all_escalation_resets.2783075996
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3497150625
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2488889859
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/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3566299877
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/workspace/coverage/default/4.chip_sw_uart_tx_rx.4245994870
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/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1233003477
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/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.945708758
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2918733987
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1204492950
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/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1304201674
/workspace/coverage/default/50.chip_sw_all_escalation_resets.1822520944
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3781913454
/workspace/coverage/default/52.chip_sw_all_escalation_resets.2602082183
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.900417935
/workspace/coverage/default/53.chip_sw_all_escalation_resets.4175958877
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.949320758
/workspace/coverage/default/56.chip_sw_all_escalation_resets.508257000
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.808879035
/workspace/coverage/default/57.chip_sw_all_escalation_resets.1967645411
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1101844488
/workspace/coverage/default/58.chip_sw_all_escalation_resets.3281179774
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2714920434
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2028525966
/workspace/coverage/default/6.chip_sw_all_escalation_resets.914306872
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.4162343902
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2431213888
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.551824000
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.217332604
/workspace/coverage/default/60.chip_sw_all_escalation_resets.274162914
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1663761046
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.167393144
/workspace/coverage/default/63.chip_sw_all_escalation_resets.2532908233
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1051824766
/workspace/coverage/default/64.chip_sw_all_escalation_resets.2302531754
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1422438027
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2839308573
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1935373025
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/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2153059673
/workspace/coverage/default/67.chip_sw_all_escalation_resets.3054256688
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2168958771
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/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.988081522
/workspace/coverage/default/69.chip_sw_all_escalation_resets.3985132061
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.4050037076
/workspace/coverage/default/7.chip_sw_all_escalation_resets.3757278969
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2039992230
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1062949177
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.830351531
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1571575014
/workspace/coverage/default/70.chip_sw_all_escalation_resets.3648029959
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1810814208
/workspace/coverage/default/71.chip_sw_all_escalation_resets.1442362579
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.4186197155
/workspace/coverage/default/72.chip_sw_all_escalation_resets.574661653
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2427889167
/workspace/coverage/default/73.chip_sw_all_escalation_resets.332118004
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2765283278
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/workspace/coverage/default/75.chip_sw_all_escalation_resets.147776914
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.563138248
/workspace/coverage/default/76.chip_sw_all_escalation_resets.111799037
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1659830980
/workspace/coverage/default/77.chip_sw_all_escalation_resets.2143726166
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1464137631
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.292430307
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3399280187
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/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.770847190
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/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3139924180
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/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.604764095
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/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2456299899
/workspace/coverage/default/84.chip_sw_all_escalation_resets.4174853999
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1729427409
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2771917319
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2096155386
/workspace/coverage/default/86.chip_sw_all_escalation_resets.846224422
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.674156401
/workspace/coverage/default/87.chip_sw_all_escalation_resets.1085912129
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3710068352
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.38952160
/workspace/coverage/default/89.chip_sw_all_escalation_resets.305154561
/workspace/coverage/default/9.chip_sw_all_escalation_resets.1202904262
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1744893714
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1048289506
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3153818439
/workspace/coverage/default/91.chip_sw_all_escalation_resets.480398427
/workspace/coverage/default/92.chip_sw_all_escalation_resets.3075528500
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2062262627
/workspace/coverage/default/98.chip_sw_all_escalation_resets.4177170097
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2530376650
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3592195753
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3227266459
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.731618600
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.501228489
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1283015956
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1616879957
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3535589762
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.133540029

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Total test records in report: 2934

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2976212468			Jul 17 08:29:45 PM PDT 24	Jul 17 08:40:28 PM PDT 24	8809238210 ps
T5	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2484600210			Jul 17 08:34:25 PM PDT 24	Jul 17 08:42:56 PM PDT 24	7935181814 ps
T6	/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1898367816			Jul 17 08:33:40 PM PDT 24	Jul 17 08:39:15 PM PDT 24	4149235480 ps
T18	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1506769740			Jul 17 08:56:44 PM PDT 24	Jul 17 09:02:34 PM PDT 24	3021807904 ps
T62	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.479823327			Jul 17 08:55:58 PM PDT 24	Jul 17 08:58:00 PM PDT 24	2516334287 ps
T19	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.481362092			Jul 17 08:48:05 PM PDT 24	Jul 17 08:53:01 PM PDT 24	2919017280 ps
T48	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.718081564			Jul 17 08:36:17 PM PDT 24	Jul 17 08:45:50 PM PDT 24	6499223760 ps
T20	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3689373885			Jul 17 08:30:48 PM PDT 24	Jul 17 08:39:49 PM PDT 24	8539211298 ps
T23	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2741812885			Jul 17 08:46:53 PM PDT 24	Jul 17 08:51:42 PM PDT 24	2830336522 ps
T21	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.75551644			Jul 17 08:48:59 PM PDT 24	Jul 17 09:00:07 PM PDT 24	8889171252 ps
T172	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1391783284			Jul 17 08:31:36 PM PDT 24	Jul 17 08:38:36 PM PDT 24	3117051200 ps
T60	/workspace/coverage/default/4.chip_tap_straps_testunlock0.1521567859			Jul 17 08:53:33 PM PDT 24	Jul 17 09:08:33 PM PDT 24	9847673941 ps
T63	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3427619134			Jul 17 08:48:43 PM PDT 24	Jul 17 08:59:39 PM PDT 24	4337309020 ps
T256	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2025074902			Jul 17 08:40:54 PM PDT 24	Jul 17 08:46:45 PM PDT 24	3277401308 ps
T68	/workspace/coverage/default/30.chip_sw_all_escalation_resets.2042538981			Jul 17 08:57:01 PM PDT 24	Jul 17 09:06:56 PM PDT 24	5821758550 ps
T118	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.619467357			Jul 17 08:52:13 PM PDT 24	Jul 17 09:07:35 PM PDT 24	7377767215 ps
T69	/workspace/coverage/default/90.chip_sw_all_escalation_resets.3759087986			Jul 17 09:01:09 PM PDT 24	Jul 17 09:09:54 PM PDT 24	5453708504 ps
T57	/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2127810090			Jul 17 08:46:14 PM PDT 24	Jul 17 09:33:23 PM PDT 24	12049731770 ps
T125	/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3054463902			Jul 17 08:55:49 PM PDT 24	Jul 17 09:35:56 PM PDT 24	11217955534 ps
T70	/workspace/coverage/default/91.chip_sw_all_escalation_resets.480398427			Jul 17 09:05:52 PM PDT 24	Jul 17 09:14:47 PM PDT 24	5320557016 ps
T22	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1848249761			Jul 17 08:56:54 PM PDT 24	Jul 17 10:19:45 PM PDT 24	48408785376 ps
T345	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.329221917			Jul 17 08:43:13 PM PDT 24	Jul 17 08:48:25 PM PDT 24	3260794736 ps
T410	/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.130477152			Jul 17 08:39:53 PM PDT 24	Jul 17 08:45:36 PM PDT 24	2526601404 ps
T173	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2609841827			Jul 17 08:54:00 PM PDT 24	Jul 17 08:59:32 PM PDT 24	6285611816 ps
T61	/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.103454257			Jul 17 08:45:03 PM PDT 24	Jul 17 10:06:13 PM PDT 24	48464217170 ps
T411	/workspace/coverage/default/1.chip_sw_kmac_app_rom.1291559490			Jul 17 08:39:07 PM PDT 24	Jul 17 08:42:28 PM PDT 24	2671177440 ps
T341	/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2448352003			Jul 17 08:59:18 PM PDT 24	Jul 17 09:06:50 PM PDT 24	4542979972 ps
T216	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.2338876244			Jul 17 08:55:41 PM PDT 24	Jul 17 09:07:24 PM PDT 24	4608709304 ps
T152	/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.123087691			Jul 17 08:30:22 PM PDT 24	Jul 17 08:34:23 PM PDT 24	3401963132 ps
T58	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.797200487			Jul 17 08:57:38 PM PDT 24	Jul 17 09:54:38 PM PDT 24	15058672232 ps
T415	/workspace/coverage/default/0.chip_sw_kmac_app_rom.678399469			Jul 17 08:32:04 PM PDT 24	Jul 17 08:36:42 PM PDT 24	2556155460 ps
T32	/workspace/coverage/default/0.chip_sw_usbdev_dpi.241146458			Jul 17 08:30:39 PM PDT 24	Jul 17 09:21:57 PM PDT 24	11949326820 ps
T59	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1407938791			Jul 17 08:58:33 PM PDT 24	Jul 17 09:49:16 PM PDT 24	15023372526 ps
T197	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.3090942171			Jul 17 08:36:58 PM PDT 24	Jul 17 08:43:44 PM PDT 24	4268934800 ps
T881	/workspace/coverage/default/1.chip_sw_example_concurrency.2526025774			Jul 17 08:31:51 PM PDT 24	Jul 17 08:35:18 PM PDT 24	2784747960 ps
T257	/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2979299138			Jul 17 08:37:10 PM PDT 24	Jul 17 08:49:16 PM PDT 24	5272739280 ps
T73	/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.847778894			Jul 17 08:50:40 PM PDT 24	Jul 17 09:00:29 PM PDT 24	3986691752 ps
T349	/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3995584398			Jul 17 08:39:01 PM PDT 24	Jul 17 08:46:24 PM PDT 24	3829869400 ps
T220	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.858781726			Jul 17 08:30:09 PM PDT 24	Jul 17 08:45:35 PM PDT 24	5870201176 ps
T146	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2110931064			Jul 17 08:53:11 PM PDT 24	Jul 17 09:03:56 PM PDT 24	3962904420 ps
T368	/workspace/coverage/default/96.chip_sw_all_escalation_resets.1667528502			Jul 17 09:01:29 PM PDT 24	Jul 17 09:10:14 PM PDT 24	5967974932 ps
T329	/workspace/coverage/default/97.chip_sw_all_escalation_resets.2239130287			Jul 17 09:01:13 PM PDT 24	Jul 17 09:11:11 PM PDT 24	5186290764 ps
T127	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.107377021			Jul 17 08:54:54 PM PDT 24	Jul 17 09:09:22 PM PDT 24	8894975782 ps
T116	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1169423028			Jul 17 08:32:19 PM PDT 24	Jul 17 08:52:07 PM PDT 24	7208683868 ps
T1	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2693189901			Jul 17 08:40:38 PM PDT 24	Jul 17 09:13:50 PM PDT 24	26678085184 ps
T67	/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.3448467041			Jul 17 08:46:46 PM PDT 24	Jul 17 08:53:48 PM PDT 24	5072363337 ps
T105	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2196801770			Jul 17 08:31:35 PM PDT 24	Jul 17 08:35:30 PM PDT 24	2941447469 ps
T29	/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.165840793			Jul 17 08:56:33 PM PDT 24	Jul 17 09:03:50 PM PDT 24	4146539640 ps
T106	/workspace/coverage/default/0.rom_e2e_asm_init_dev.259948289			Jul 17 08:35:44 PM PDT 24	Jul 17 09:46:02 PM PDT 24	15052775010 ps
T107	/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2490706590			Jul 17 08:33:17 PM PDT 24	Jul 17 08:42:50 PM PDT 24	4527670158 ps
T108	/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2647142794			Jul 17 08:57:59 PM PDT 24	Jul 17 10:47:06 PM PDT 24	27220177616 ps
T109	/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.317208521			Jul 17 08:37:10 PM PDT 24	Jul 17 08:46:19 PM PDT 24	5413966780 ps
T110	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.4118430318			Jul 17 08:39:33 PM PDT 24	Jul 17 09:40:54 PM PDT 24	14933843360 ps
T111	/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.113530749			Jul 17 08:38:27 PM PDT 24	Jul 17 08:57:49 PM PDT 24	6914200964 ps
T477	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2454051157			Jul 17 08:58:39 PM PDT 24	Jul 17 09:04:25 PM PDT 24	4383516296 ps
T214	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.1146975338			Jul 17 08:47:12 PM PDT 24	Jul 17 09:16:50 PM PDT 24	8769226450 ps
T34	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.1939909468			Jul 17 08:47:00 PM PDT 24	Jul 17 08:53:08 PM PDT 24	3541692080 ps
T217	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1561714910			Jul 17 08:28:30 PM PDT 24	Jul 17 08:39:57 PM PDT 24	4129220192 ps
T121	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.496431313			Jul 17 08:33:17 PM PDT 24	Jul 17 08:45:05 PM PDT 24	4033262540 ps
T85	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1259552644			Jul 17 08:52:50 PM PDT 24	Jul 18 12:12:52 AM PDT 24	255296572772 ps
T480	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.560331246			Jul 17 08:30:53 PM PDT 24	Jul 17 08:43:12 PM PDT 24	5160418830 ps
T223	/workspace/coverage/default/47.chip_sw_all_escalation_resets.1885758691			Jul 17 08:58:55 PM PDT 24	Jul 17 09:09:20 PM PDT 24	4238813452 ps
T248	/workspace/coverage/default/98.chip_sw_all_escalation_resets.4177170097			Jul 17 09:01:53 PM PDT 24	Jul 17 09:12:30 PM PDT 24	5080764744 ps
T224	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3741061646			Jul 17 08:48:28 PM PDT 24	Jul 17 09:55:49 PM PDT 24	16413312760 ps
T302	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.885863285			Jul 17 08:39:01 PM PDT 24	Jul 17 10:17:07 PM PDT 24	24525179696 ps
T303	/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1571575014			Jul 17 09:01:11 PM PDT 24	Jul 17 09:06:22 PM PDT 24	4312926360 ps
T51	/workspace/coverage/default/1.chip_sw_spi_device_tpm.187816720			Jul 17 08:34:45 PM PDT 24	Jul 17 08:40:53 PM PDT 24	3968348742 ps
T304	/workspace/coverage/default/2.chip_sw_hmac_smoketest.4066972314			Jul 17 08:54:23 PM PDT 24	Jul 17 09:01:13 PM PDT 24	3182227992 ps
T305	/workspace/coverage/default/1.rom_keymgr_functest.3213447221			Jul 17 08:42:50 PM PDT 24	Jul 17 08:51:04 PM PDT 24	4802099288 ps
T254	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.3502863506			Jul 17 08:30:47 PM PDT 24	Jul 17 08:35:24 PM PDT 24	2466004780 ps
T306	/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.420756645			Jul 17 08:38:52 PM PDT 24	Jul 17 08:47:15 PM PDT 24	5222396198 ps
T307	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2427889167			Jul 17 09:01:18 PM PDT 24	Jul 17 09:07:30 PM PDT 24	3719489760 ps
T113	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.298821111			Jul 17 08:40:26 PM PDT 24	Jul 17 09:48:52 PM PDT 24	28664151993 ps
T33	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1745583338			Jul 17 08:29:50 PM PDT 24	Jul 17 08:36:18 PM PDT 24	4063169720 ps
T369	/workspace/coverage/default/28.chip_sw_all_escalation_resets.1067137442			Jul 17 08:58:08 PM PDT 24	Jul 17 09:07:18 PM PDT 24	5220203380 ps
T30	/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.623117977			Jul 17 08:55:44 PM PDT 24	Jul 17 09:07:24 PM PDT 24	4308687296 ps
T479	/workspace/coverage/default/2.chip_sw_kmac_smoketest.1960311404			Jul 17 08:52:04 PM PDT 24	Jul 17 08:56:26 PM PDT 24	2195265340 ps
T882	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3624925966			Jul 17 08:35:10 PM PDT 24	Jul 17 08:42:31 PM PDT 24	7356927720 ps
T31	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3736599542			Jul 17 08:52:44 PM PDT 24	Jul 17 09:17:04 PM PDT 24	8196017225 ps
T218	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2320445385			Jul 17 08:43:48 PM PDT 24	Jul 17 09:08:21 PM PDT 24	8975898025 ps
T86	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1961964708			Jul 17 08:46:37 PM PDT 24	Jul 17 09:06:50 PM PDT 24	11469387748 ps
T213	/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.3145129643			Jul 17 08:30:50 PM PDT 24	Jul 17 08:35:20 PM PDT 24	3006319560 ps
T335	/workspace/coverage/default/1.chip_sival_flash_info_access.805646723			Jul 17 08:32:59 PM PDT 24	Jul 17 08:37:54 PM PDT 24	2555424980 ps
T359	/workspace/coverage/default/61.chip_sw_all_escalation_resets.2061317350			Jul 17 08:59:43 PM PDT 24	Jul 17 09:08:35 PM PDT 24	5129026068 ps
T327	/workspace/coverage/default/1.chip_sw_flash_crash_alert.2642835564			Jul 17 08:39:46 PM PDT 24	Jul 17 08:50:32 PM PDT 24	5178224352 ps
T74	/workspace/coverage/default/2.rom_raw_unlock.1188668463			Jul 17 08:51:48 PM PDT 24	Jul 17 08:57:00 PM PDT 24	5153219292 ps
T672	/workspace/coverage/default/15.chip_sw_all_escalation_resets.1887078358			Jul 17 08:59:36 PM PDT 24	Jul 17 09:10:39 PM PDT 24	5812191720 ps
T241	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1531009588			Jul 17 08:37:23 PM PDT 24	Jul 17 08:44:58 PM PDT 24	4060670496 ps
T293	/workspace/coverage/default/18.chip_sw_all_escalation_resets.3960901453			Jul 17 08:55:28 PM PDT 24	Jul 17 09:07:30 PM PDT 24	4868500088 ps
T165	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3613559105			Jul 17 08:33:39 PM PDT 24	Jul 17 10:05:12 PM PDT 24	43900814090 ps
T294	/workspace/coverage/default/1.rom_e2e_static_critical.82270091			Jul 17 08:48:21 PM PDT 24	Jul 17 09:57:55 PM PDT 24	17765053548 ps
T295	/workspace/coverage/default/0.chip_sw_flash_ctrl_access.2753140914			Jul 17 08:27:37 PM PDT 24	Jul 17 08:46:05 PM PDT 24	5369421640 ps
T296	/workspace/coverage/default/0.chip_sw_aes_masking_off.2079116354			Jul 17 08:33:26 PM PDT 24	Jul 17 08:38:30 PM PDT 24	3233484888 ps
T297	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.4249945158			Jul 17 08:32:53 PM PDT 24	Jul 17 08:39:14 PM PDT 24	3029838620 ps
T219	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1332389821			Jul 17 08:44:28 PM PDT 24	Jul 17 09:00:29 PM PDT 24	4297519520 ps
T119	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3162385709			Jul 17 08:31:50 PM PDT 24	Jul 17 08:40:49 PM PDT 24	3955384115 ps
T298	/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3907370377			Jul 17 08:38:12 PM PDT 24	Jul 17 08:43:43 PM PDT 24	2995048124 ps
T221	/workspace/coverage/default/3.chip_sw_uart_tx_rx.2239835792			Jul 17 08:52:56 PM PDT 24	Jul 17 09:03:53 PM PDT 24	4648664900 ps
T883	/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1467334689			Jul 17 08:47:37 PM PDT 24	Jul 17 09:02:31 PM PDT 24	5519692248 ps
T364	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.483384725			Jul 17 08:44:38 PM PDT 24	Jul 17 08:58:14 PM PDT 24	4274496882 ps
T884	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2924787065			Jul 17 08:41:13 PM PDT 24	Jul 17 08:44:04 PM PDT 24	3140952640 ps
T174	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3861942520			Jul 17 08:39:56 PM PDT 24	Jul 17 08:50:54 PM PDT 24	8236835664 ps
T701	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1135367245			Jul 17 08:55:06 PM PDT 24	Jul 17 09:01:47 PM PDT 24	3584115320 ps
T128	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.315169614			Jul 17 08:48:30 PM PDT 24	Jul 17 08:56:19 PM PDT 24	5971164302 ps
T379	/workspace/coverage/default/2.rom_e2e_asm_init_dev.243148698			Jul 17 08:58:27 PM PDT 24	Jul 17 09:59:28 PM PDT 24	15204068541 ps
T75	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.3355865893			Jul 17 08:41:05 PM PDT 24	Jul 17 08:48:28 PM PDT 24	5397042448 ps
T885	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1810270176			Jul 17 08:49:40 PM PDT 24	Jul 17 08:59:15 PM PDT 24	3787141800 ps
T886	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.906326109			Jul 17 08:48:46 PM PDT 24	Jul 17 08:55:51 PM PDT 24	3483709804 ps
T887	/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.2405270843			Jul 17 08:56:10 PM PDT 24	Jul 17 09:18:14 PM PDT 24	8051836154 ps
T351	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.3559658056			Jul 17 08:45:46 PM PDT 24	Jul 17 08:49:29 PM PDT 24	3076324280 ps
T77	/workspace/coverage/default/0.chip_sw_usbdev_pullup.792140327			Jul 17 08:29:39 PM PDT 24	Jul 17 08:35:37 PM PDT 24	3829769400 ps
T188	/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2431213888			Jul 17 08:54:28 PM PDT 24	Jul 17 09:08:02 PM PDT 24	10898805735 ps
T81	/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.2753877681			Jul 17 08:37:16 PM PDT 24	Jul 17 09:25:28 PM PDT 24	31563157095 ps
T700	/workspace/coverage/default/0.chip_sw_aes_smoketest.3687167653			Jul 17 08:33:15 PM PDT 24	Jul 17 08:37:19 PM PDT 24	3357855724 ps
T352	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2762776240			Jul 17 08:29:43 PM PDT 24	Jul 17 08:40:02 PM PDT 24	3723405464 ps
T324	/workspace/coverage/default/11.chip_sw_all_escalation_resets.1539438493			Jul 17 08:56:26 PM PDT 24	Jul 17 09:05:28 PM PDT 24	5972156064 ps
T888	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.149461462			Jul 17 08:38:13 PM PDT 24	Jul 17 08:46:52 PM PDT 24	4075434346 ps
T2	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1573020735			Jul 17 08:28:29 PM PDT 24	Jul 17 08:33:09 PM PDT 24	3399512214 ps
T189	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1204492950			Jul 17 08:53:20 PM PDT 24	Jul 17 09:06:15 PM PDT 24	11498100145 ps
T249	/workspace/coverage/default/45.chip_sw_all_escalation_resets.3839263860			Jul 17 09:00:21 PM PDT 24	Jul 17 09:08:26 PM PDT 24	5458864938 ps
T421	/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1051464859			Jul 17 08:41:21 PM PDT 24	Jul 17 09:00:17 PM PDT 24	5852671596 ps
T422	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3533209234			Jul 17 08:52:52 PM PDT 24	Jul 17 08:57:29 PM PDT 24	2793770368 ps
T423	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3491162776			Jul 17 08:49:30 PM PDT 24	Jul 17 08:59:52 PM PDT 24	5514660750 ps
T424	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.4017472640			Jul 17 08:28:10 PM PDT 24	Jul 17 08:46:19 PM PDT 24	5925827934 ps
T122	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2182493028			Jul 17 08:50:59 PM PDT 24	Jul 17 09:04:03 PM PDT 24	4270026470 ps
T117	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.238902956			Jul 17 08:35:32 PM PDT 24	Jul 17 09:55:34 PM PDT 24	18149072840 ps
T425	/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3497150625			Jul 17 08:54:29 PM PDT 24	Jul 17 08:59:14 PM PDT 24	5858792168 ps
T674	/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.330298774			Jul 17 09:00:26 PM PDT 24	Jul 17 09:06:30 PM PDT 24	3391473960 ps
T26	/workspace/coverage/default/1.chip_sw_spi_device_pass_through.2936598038			Jul 17 08:32:27 PM PDT 24	Jul 17 08:47:49 PM PDT 24	7922975474 ps
T149	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1910747998			Jul 17 08:32:10 PM PDT 24	Jul 17 09:34:30 PM PDT 24	24831500018 ps
T333	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2033371929			Jul 17 08:38:59 PM PDT 24	Jul 17 08:47:20 PM PDT 24	4371764759 ps
T467	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.2093186626			Jul 17 08:34:43 PM PDT 24	Jul 17 08:38:43 PM PDT 24	3103063504 ps
T492	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2995038359			Jul 17 08:30:20 PM PDT 24	Jul 17 08:43:25 PM PDT 24	8015549040 ps
T156	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3583676130			Jul 17 08:30:38 PM PDT 24	Jul 17 08:42:31 PM PDT 24	6163084460 ps
T150	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3324910607			Jul 17 08:37:04 PM PDT 24	Jul 17 09:40:35 PM PDT 24	17029053840 ps
T390	/workspace/coverage/default/19.chip_sw_all_escalation_resets.2456418785			Jul 17 08:55:31 PM PDT 24	Jul 17 09:05:34 PM PDT 24	5158651288 ps
T123	/workspace/coverage/default/0.chip_sw_edn_auto_mode.1363862793			Jul 17 08:39:09 PM PDT 24	Jul 17 08:58:06 PM PDT 24	5189824930 ps
T370	/workspace/coverage/default/22.chip_sw_all_escalation_resets.323738817			Jul 17 08:58:00 PM PDT 24	Jul 17 09:05:06 PM PDT 24	4338515868 ps
T54	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1239643765			Jul 17 08:36:57 PM PDT 24	Jul 17 09:56:23 PM PDT 24	15300876617 ps
T112	/workspace/coverage/default/1.chip_sw_power_sleep_load.2739847649			Jul 17 08:41:57 PM PDT 24	Jul 17 08:48:36 PM PDT 24	4378150086 ps
T360	/workspace/coverage/default/3.chip_sw_all_escalation_resets.4279545144			Jul 17 08:52:42 PM PDT 24	Jul 17 09:03:27 PM PDT 24	4526386730 ps
T325	/workspace/coverage/default/92.chip_sw_all_escalation_resets.3075528500			Jul 17 09:01:26 PM PDT 24	Jul 17 09:08:10 PM PDT 24	4497696140 ps
T354	/workspace/coverage/default/0.chip_sival_flash_info_access.2927482878			Jul 17 08:28:53 PM PDT 24	Jul 17 08:34:43 PM PDT 24	3714619800 ps
T473	/workspace/coverage/default/2.rom_e2e_static_critical.3379872861			Jul 17 08:57:16 PM PDT 24	Jul 17 09:55:59 PM PDT 24	17431161324 ps
T474	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.604764095			Jul 17 09:01:43 PM PDT 24	Jul 17 09:07:15 PM PDT 24	3480740668 ps
T242	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2918733987			Jul 17 08:54:39 PM PDT 24	Jul 17 09:05:37 PM PDT 24	5104302948 ps
T226	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.4115817749			Jul 17 08:45:29 PM PDT 24	Jul 17 09:06:17 PM PDT 24	7153586292 ps
T889	/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1048832436			Jul 17 08:32:23 PM PDT 24	Jul 17 08:38:03 PM PDT 24	3059699998 ps
T190	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.4011284054			Jul 17 08:51:52 PM PDT 24	Jul 17 09:09:25 PM PDT 24	12981645273 ps
T350	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.796316455			Jul 17 08:49:09 PM PDT 24	Jul 17 08:57:05 PM PDT 24	4513759108 ps
T890	/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3005346028			Jul 17 08:34:13 PM PDT 24	Jul 17 08:39:15 PM PDT 24	3254013996 ps
T147	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3301836818			Jul 17 08:28:23 PM PDT 24	Jul 17 08:39:53 PM PDT 24	4507178200 ps
T742	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2238991607			Jul 17 09:03:56 PM PDT 24	Jul 17 09:11:13 PM PDT 24	3839029880 ps
T3	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.379044843			Jul 17 08:49:38 PM PDT 24	Jul 17 08:56:17 PM PDT 24	7449143200 ps
T891	/workspace/coverage/default/2.chip_sw_csrng_smoketest.163341284			Jul 17 08:53:35 PM PDT 24	Jul 17 08:57:43 PM PDT 24	3290049352 ps
T892	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.3472146382			Jul 17 08:43:08 PM PDT 24	Jul 17 08:46:58 PM PDT 24	2783215460 ps
T893	/workspace/coverage/default/0.chip_sw_hmac_smoketest.1743666191			Jul 17 08:31:00 PM PDT 24	Jul 17 08:37:43 PM PDT 24	3313226280 ps
T894	/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3657503548			Jul 17 08:30:59 PM PDT 24	Jul 17 08:37:41 PM PDT 24	3209528120 ps
T745	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1270226388			Jul 17 08:38:55 PM PDT 24	Jul 17 08:45:26 PM PDT 24	4240696526 ps
T895	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.551090825			Jul 17 08:36:34 PM PDT 24	Jul 17 09:34:39 PM PDT 24	19075557398 ps
T372	/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1254338210			Jul 17 08:29:51 PM PDT 24	Jul 17 08:36:25 PM PDT 24	2996748148 ps
T55	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1984634946			Jul 17 08:36:31 PM PDT 24	Jul 17 10:05:43 PM PDT 24	23936863250 ps
T259	/workspace/coverage/default/67.chip_sw_all_escalation_resets.3054256688			Jul 17 09:00:17 PM PDT 24	Jul 17 09:12:46 PM PDT 24	4486356504 ps
T222	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.4271754057			Jul 17 08:32:24 PM PDT 24	Jul 17 09:20:28 PM PDT 24	13786157393 ps
T896	/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2039992230			Jul 17 08:53:57 PM PDT 24	Jul 17 10:27:31 PM PDT 24	20143084088 ps
T10	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3167128695			Jul 17 08:42:29 PM PDT 24	Jul 17 09:14:57 PM PDT 24	20690280332 ps
T114	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3837836438			Jul 17 08:52:16 PM PDT 24	Jul 17 09:54:25 PM PDT 24	27223630540 ps
T897	/workspace/coverage/default/0.rom_e2e_asm_init_rma.3588852165			Jul 17 08:35:13 PM PDT 24	Jul 17 09:52:15 PM PDT 24	14510115636 ps
T803	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1481824414			Jul 17 08:53:05 PM PDT 24	Jul 17 09:00:32 PM PDT 24	4077817210 ps
T56	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3507948605			Jul 17 08:36:39 PM PDT 24	Jul 17 10:07:52 PM PDT 24	23012215884 ps
T35	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.689171989			Jul 17 08:30:43 PM PDT 24	Jul 17 08:37:03 PM PDT 24	3354989160 ps
T166	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1992057538			Jul 17 08:55:30 PM PDT 24	Jul 17 10:25:39 PM PDT 24	46769903516 ps
T898	/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3057517627			Jul 17 08:53:32 PM PDT 24	Jul 17 08:58:53 PM PDT 24	2637747390 ps
T148	/workspace/coverage/default/2.chip_sw_power_idle_load.1468531029			Jul 17 08:49:53 PM PDT 24	Jul 17 08:59:06 PM PDT 24	4609623438 ps
T899	/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1560990958			Jul 17 08:56:00 PM PDT 24	Jul 17 09:07:44 PM PDT 24	9407610658 ps
T153	/workspace/coverage/default/1.chip_plic_all_irqs_10.2612310478			Jul 17 08:38:34 PM PDT 24	Jul 17 08:46:22 PM PDT 24	3676826216 ps
T900	/workspace/coverage/default/1.chip_sw_aes_smoketest.2528217625			Jul 17 08:44:16 PM PDT 24	Jul 17 08:50:44 PM PDT 24	2732171624 ps
T158	/workspace/coverage/default/79.chip_sw_all_escalation_resets.3850867373			Jul 17 09:02:19 PM PDT 24	Jul 17 09:13:08 PM PDT 24	4895361670 ps
T901	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.988887667			Jul 17 08:33:33 PM PDT 24	Jul 17 08:50:49 PM PDT 24	5590495866 ps
T143	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3835619863			Jul 17 08:35:19 PM PDT 24	Jul 18 12:08:51 AM PDT 24	79069566792 ps
T902	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.771100533			Jul 17 08:40:13 PM PDT 24	Jul 17 08:49:58 PM PDT 24	5359254252 ps
T253	/workspace/coverage/default/1.chip_sw_plic_sw_irq.872217898			Jul 17 08:40:39 PM PDT 24	Jul 17 08:43:54 PM PDT 24	2557893004 ps
T71	/workspace/coverage/default/4.chip_tap_straps_rma.4180610605			Jul 17 08:54:11 PM PDT 24	Jul 17 08:59:11 PM PDT 24	4393636528 ps
T36	/workspace/coverage/default/2.chip_jtag_csr_rw.1115333914			Jul 17 08:41:53 PM PDT 24	Jul 17 09:11:18 PM PDT 24	18627229962 ps
T344	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.842302052			Jul 17 08:35:41 PM PDT 24	Jul 17 08:51:14 PM PDT 24	5132918616 ps
T11	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.183267399			Jul 17 08:33:32 PM PDT 24	Jul 17 08:37:15 PM PDT 24	2786735004 ps
T443	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1348599240			Jul 17 08:30:07 PM PDT 24	Jul 17 08:42:19 PM PDT 24	4317008556 ps
T444	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.808879035			Jul 17 08:58:15 PM PDT 24	Jul 17 09:06:04 PM PDT 24	3649351160 ps
T445	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3056252745			Jul 17 08:36:06 PM PDT 24	Jul 17 09:32:05 PM PDT 24	14219618693 ps
T175	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3291475596			Jul 17 08:30:46 PM PDT 24	Jul 17 08:47:30 PM PDT 24	7395270160 ps
T321	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.3372980948			Jul 17 08:56:48 PM PDT 24	Jul 17 09:07:35 PM PDT 24	4109244792 ps
T225	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1510986737			Jul 17 08:30:33 PM PDT 24	Jul 17 09:20:06 PM PDT 24	12482263816 ps
T322	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.38952160			Jul 17 09:01:54 PM PDT 24	Jul 17 09:09:08 PM PDT 24	4182021180 ps
T120	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2265999475			Jul 17 08:33:10 PM PDT 24	Jul 17 08:46:11 PM PDT 24	5242113150 ps
T176	/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.451237538			Jul 17 08:50:15 PM PDT 24	Jul 17 08:55:04 PM PDT 24	2895643111 ps
T311	/workspace/coverage/default/2.rom_e2e_asm_init_rma.3413646258			Jul 17 08:55:55 PM PDT 24	Jul 17 09:55:52 PM PDT 24	14829920304 ps
T312	/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3155880903			Jul 17 08:35:59 PM PDT 24	Jul 17 08:54:11 PM PDT 24	7228596843 ps
T313	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3139924180			Jul 17 09:00:28 PM PDT 24	Jul 17 09:05:30 PM PDT 24	3057849384 ps
T37	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.3009630711			Jul 17 08:27:50 PM PDT 24	Jul 17 10:39:31 PM PDT 24	31603393060 ps
T314	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.4004089280			Jul 17 08:45:02 PM PDT 24	Jul 17 09:03:01 PM PDT 24	6137900754 ps
T315	/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.2887469116			Jul 17 08:38:06 PM PDT 24	Jul 17 08:59:09 PM PDT 24	4902262310 ps
T316	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.334592807			Jul 17 08:58:56 PM PDT 24	Jul 17 09:08:14 PM PDT 24	3629700310 ps
T317	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.253074386			Jul 17 08:44:12 PM PDT 24	Jul 17 08:57:06 PM PDT 24	3887037980 ps
T318	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2796595479			Jul 17 08:53:42 PM PDT 24	Jul 17 09:03:34 PM PDT 24	4504843672 ps
T115	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.427838268			Jul 17 08:32:31 PM PDT 24	Jul 17 09:35:17 PM PDT 24	22667105923 ps
T353	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1743039755			Jul 17 08:52:05 PM PDT 24	Jul 17 09:05:04 PM PDT 24	4492556914 ps
T328	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.249324505			Jul 17 08:29:14 PM PDT 24	Jul 17 08:54:00 PM PDT 24	11166856857 ps
T903	/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2003981755			Jul 17 08:33:18 PM PDT 24	Jul 17 08:37:17 PM PDT 24	3219918014 ps
T904	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.194184454			Jul 17 08:47:53 PM PDT 24	Jul 17 09:01:47 PM PDT 24	9547281280 ps
T255	/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1621511291			Jul 17 08:51:41 PM PDT 24	Jul 17 08:56:04 PM PDT 24	3130434308 ps
T87	/workspace/coverage/default/17.chip_sw_all_escalation_resets.1111509190			Jul 17 08:55:24 PM PDT 24	Jul 17 09:03:11 PM PDT 24	4631028650 ps
T93	/workspace/coverage/default/2.chip_sw_aes_smoketest.3522939909			Jul 17 08:52:17 PM PDT 24	Jul 17 08:58:51 PM PDT 24	2975187268 ps
T94	/workspace/coverage/default/85.chip_sw_all_escalation_resets.2771917319			Jul 17 09:01:30 PM PDT 24	Jul 17 09:11:10 PM PDT 24	4934827832 ps
T95	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1800099957			Jul 17 08:53:08 PM PDT 24	Jul 17 09:04:26 PM PDT 24	4520434172 ps
T96	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1915112283			Jul 17 08:32:00 PM PDT 24	Jul 17 08:40:40 PM PDT 24	7092472800 ps
T97	/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.70924374			Jul 17 08:45:04 PM PDT 24	Jul 17 09:06:11 PM PDT 24	5961497677 ps
T98	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.4140018782			Jul 17 08:35:39 PM PDT 24	Jul 17 08:37:39 PM PDT 24	2219961010 ps
T99	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.565753295			Jul 17 08:28:57 PM PDT 24	Jul 17 09:09:14 PM PDT 24	11057433660 ps
T100	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.545691919			Jul 17 08:30:37 PM PDT 24	Jul 17 08:40:57 PM PDT 24	4882809704 ps
T101	/workspace/coverage/default/14.chip_sw_all_escalation_resets.1286239991			Jul 17 08:56:16 PM PDT 24	Jul 17 09:06:37 PM PDT 24	4527222320 ps
T905	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.343455063			Jul 17 08:37:25 PM PDT 24	Jul 17 08:52:20 PM PDT 24	7101612488 ps
T906	/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.4277179949			Jul 17 08:40:33 PM PDT 24	Jul 17 08:51:16 PM PDT 24	4164603444 ps
T721	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3627390552			Jul 17 08:57:09 PM PDT 24	Jul 17 09:04:33 PM PDT 24	3884296520 ps
T907	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1166663589			Jul 17 08:29:51 PM PDT 24	Jul 17 08:35:43 PM PDT 24	2777617200 ps
T355	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2261938979			Jul 17 08:33:17 PM PDT 24	Jul 17 08:44:03 PM PDT 24	5097564289 ps
T690	/workspace/coverage/default/2.chip_sw_plic_sw_irq.3831592680			Jul 17 08:48:59 PM PDT 24	Jul 17 08:54:16 PM PDT 24	3579179548 ps
T287	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.1141439793			Jul 17 08:28:59 PM PDT 24	Jul 17 08:39:57 PM PDT 24	5436939700 ps
T681	/workspace/coverage/default/55.chip_sw_all_escalation_resets.97108754			Jul 17 08:59:04 PM PDT 24	Jul 17 09:08:25 PM PDT 24	6078033430 ps
T908	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.830351531			Jul 17 08:53:48 PM PDT 24	Jul 17 09:03:12 PM PDT 24	4274564776 ps
T232	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.3633109922			Jul 17 08:35:29 PM PDT 24	Jul 17 10:01:43 PM PDT 24	46318122094 ps
T273	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1777939118			Jul 17 08:45:12 PM PDT 24	Jul 17 08:47:08 PM PDT 24	2299055955 ps
T909	/workspace/coverage/default/0.chip_sw_uart_tx_rx.2280547123			Jul 17 08:29:55 PM PDT 24	Jul 17 08:38:54 PM PDT 24	4100238096 ps
T38	/workspace/coverage/default/0.chip_sw_usbdev_setuprx.3564523414			Jul 17 08:28:08 PM PDT 24	Jul 17 08:37:45 PM PDT 24	4158994678 ps
T229	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.2459721574			Jul 17 08:33:47 PM PDT 24	Jul 17 09:21:40 PM PDT 24	11843443850 ps
T910	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.767696488			Jul 17 08:30:49 PM PDT 24	Jul 17 08:46:52 PM PDT 24	9196769520 ps
T911	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.4123423158			Jul 17 08:40:25 PM PDT 24	Jul 17 10:00:54 PM PDT 24	15563502376 ps
T912	/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.113141314			Jul 17 08:30:48 PM PDT 24	Jul 17 08:36:54 PM PDT 24	4876474692 ps
T236	/workspace/coverage/default/0.chip_sw_flash_init.1531100603			Jul 17 08:29:05 PM PDT 24	Jul 17 09:01:34 PM PDT 24	17757686136 ps
T913	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2720095577			Jul 17 08:48:32 PM PDT 24	Jul 17 09:01:13 PM PDT 24	8242006412 ps
T482	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2599135383			Jul 17 08:39:50 PM PDT 24	Jul 17 08:55:27 PM PDT 24	6050306835 ps
T914	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2268930909			Jul 17 08:39:54 PM PDT 24	Jul 17 08:50:35 PM PDT 24	4132799820 ps
T483	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1059404855			Jul 17 08:39:09 PM PDT 24	Jul 17 08:56:56 PM PDT 24	7202608970 ps
T246	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2552028605			Jul 17 08:38:35 PM PDT 24	Jul 17 09:16:01 PM PDT 24	15488686400 ps
T484	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.916777669			Jul 17 08:49:02 PM PDT 24	Jul 17 09:09:49 PM PDT 24	5645541775 ps
T274	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1202950776			Jul 17 08:39:41 PM PDT 24	Jul 17 09:40:12 PM PDT 24	14913289967 ps
T915	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1601409948			Jul 17 08:31:07 PM PDT 24	Jul 17 08:43:19 PM PDT 24	4928371000 ps
T719	/workspace/coverage/default/39.chip_sw_all_escalation_resets.2842505955			Jul 17 08:57:07 PM PDT 24	Jul 17 09:07:24 PM PDT 24	4083259560 ps
T731	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.948597242			Jul 17 08:57:23 PM PDT 24	Jul 17 09:03:09 PM PDT 24	3719266280 ps
T916	/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.4293486734			Jul 17 08:54:16 PM PDT 24	Jul 17 09:08:02 PM PDT 24	10640268692 ps
T167	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3868459063			Jul 17 08:46:11 PM PDT 24	Jul 17 09:16:38 PM PDT 24	27834888892 ps