Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	509	1			T84	4		T572	2		T575	2
all_values[1]	474	1			T84	1		T570	2		T448	1
all_values[2]	462	1			T570	1		T575	1		T573	1
all_values[3]	467	1			T84	2		T572	4		T450	2
all_values[4]	467	1			T572	2		T450	1		T575	2
all_values[5]	471	1			T84	2		T251	1		T126	1
all_values[6]	466	1			T84	2		T251	1		T570	1
all_values[7]	472	1			T448	2		T450	1		T575	3
all_values[8]	474	1			T448	1		T572	1		T575	2
all_values[9]	479	1			T570	1		T572	2		T450	1
all_values[10]	496	1			T84	6		T251	1		T452	2
all_values[11]	477	1			T84	2		T572	1		T450	2
all_values[12]	486	1			T84	2		T452	1		T448	1
all_values[13]	461	1			T452	2		T450	1		T575	2
all_values[14]	479	1			T84	4		T452	1		T448	1
all_values[15]	475	1			T84	5		T126	1		T452	1
all_values[16]	468	1			T84	3		T448	1		T571	1
all_values[17]	479	1			T84	1		T452	1		T570	1
all_values[18]	513	1			T84	2		T126	1		T448	1
all_values[19]	452	1			T84	1		T251	1		T575	1
all_values[20]	477	1			T84	5		T570	1		T572	1
all_values[21]	486	1			T84	2		T572	2		T575	2
all_values[22]	480	1			T251	1		T452	1		T570	1
all_values[23]	452	1			T84	2		T251	1		T572	2
all_values[24]	493	1			T84	3		T452	1		T572	3
all_values[25]	507	1			T84	2		T570	1		T448	1
all_values[26]	471	1			T84	1		T251	1		T570	1
all_values[27]	522	1			T84	1		T452	1		T571	1
all_values[28]	484	1			T84	2		T126	1		T572	3
all_values[29]	486	1			T84	4		T572	2		T575	1
all_values[30]	455	1			T84	1		T570	1		T448	1
all_values[31]	500	1			T84	1		T450	1		T575	1
all_values[32]	443	1			T84	4		T571	1		T572	1
all_values[33]	476	1			T84	3		T570	1		T571	1
all_values[34]	496	1			T84	2		T251	1		T452	1
all_values[35]	499	1			T84	3		T251	1		T126	1
all_values[36]	495	1			T84	3		T452	1		T572	2
all_values[37]	452	1			T84	2		T126	1		T452	1
all_values[38]	476	1			T452	1		T448	1		T572	2
all_values[39]	461	1			T84	1		T570	1		T448	1
all_values[40]	505	1			T84	4		T251	1		T570	3
all_values[41]	475	1			T84	3		T251	1		T572	1
all_values[42]	448	1			T84	1		T251	1		T452	1
all_values[43]	447	1			T84	1		T575	2		T859	1
all_values[44]	482	1			T84	4		T452	1		T570	1
all_values[45]	482	1			T84	2		T572	1		T575	1
all_values[46]	462	1			T84	1		T452	1		T859	2
all_values[47]	496	1			T84	2		T126	1		T570	1
all_values[48]	502	1			T84	3		T251	1		T448	2
all_values[49]	462	1			T572	2		T449	1		T560	2