Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3663	1			T78	2		T84	21		T126	1
all_values[1]	3712	1			T78	3		T84	10		T126	1
all_values[2]	3745	1			T78	2		T84	17		T126	2
all_values[3]	3609	1			T78	1		T84	19		T126	1
all_values[4]	3611	1			T78	3		T84	17		T126	1
all_values[5]	3697	1			T78	3		T84	10		T126	3
all_values[6]	3677	1			T78	2		T84	13		T572	4
all_values[7]	3564	1			T78	4		T84	19		T126	2
all_values[8]	3656	1			T78	1		T84	17		T126	1
all_values[9]	3633	1			T78	2		T84	24		T126	2
all_values[10]	3703	1			T78	7		T84	21		T572	11
all_values[11]	3540	1			T84	15		T126	1		T572	7
all_values[12]	3734	1			T78	2		T84	17		T126	1
all_values[13]	3491	1			T84	14		T126	1		T572	9
all_values[14]	3676	1			T78	5		T84	22		T126	1
all_values[15]	3627	1			T78	2		T84	26		T126	1
all_values[16]	3630	1			T78	5		T84	13		T572	11
all_values[17]	3623	1			T78	3		T84	20		T126	2
all_values[18]	3751	1			T78	7		T84	27		T126	1
all_values[19]	3690	1			T78	2		T84	20		T126	1
all_values[20]	3782	1			T78	1		T84	18		T126	1
all_values[21]	3529	1			T78	3		T84	14		T572	11
all_values[22]	3641	1			T78	4		T84	21		T572	14
all_values[23]	3632	1			T78	2		T84	15		T126	1
all_values[24]	3707	1			T78	4		T84	17		T572	11
all_values[25]	3636	1			T78	5		T84	17		T126	2
all_values[26]	3801	1			T78	3		T84	20		T126	2
all_values[27]	3632	1			T78	4		T84	19		T126	2
all_values[28]	3556	1			T78	5		T84	12		T126	1
all_values[29]	3668	1			T78	1		T84	23		T572	6
all_values[30]	3697	1			T84	17		T126	1		T572	8
all_values[31]	3606	1			T78	7		T84	10		T572	6
all_values[32]	3625	1			T78	5		T84	17		T126	2
all_values[33]	3589	1			T78	7		T84	15		T572	4
all_values[34]	3618	1			T78	1		T84	17		T572	10
all_values[35]	3650	1			T78	2		T84	23		T572	8
all_values[36]	3770	1			T78	1		T84	22		T126	1
all_values[37]	3648	1			T78	6		T84	15		T126	1
all_values[38]	3590	1			T78	4		T84	21		T126	3
all_values[39]	3642	1			T78	1		T84	18		T126	2
all_values[40]	3614	1			T78	1		T84	10		T126	2
all_values[41]	3659	1			T78	3		T84	21		T126	2
all_values[42]	3571	1			T78	1		T84	19		T126	1
all_values[43]	3608	1			T78	2		T84	20		T126	2
all_values[44]	3737	1			T78	2		T84	23		T572	12
all_values[45]	3756	1			T78	2		T84	26		T126	1
all_values[46]	3633	1			T78	4		T84	17		T572	4
all_values[47]	3658	1			T78	2		T84	23		T126	2
all_values[48]	3619	1			T78	2		T84	21		T126	2
all_values[49]	3645	1			T78	2		T84	19		T126	1
all_values[50]	3696	1			T78	4		T84	17		T572	7
all_values[51]	3640	1			T78	2		T84	23		T126	1
all_values[52]	3488	1			T78	2		T84	14		T126	2
all_values[53]	3672	1			T84	12		T572	11		T575	12
all_values[54]	3656	1			T78	3		T84	25		T126	1
all_values[55]	3630	1			T78	4		T84	14		T126	1
all_values[56]	3653	1			T78	3		T84	17		T126	1
all_values[57]	3662	1			T78	3		T84	12		T126	3
all_values[58]	3564	1			T78	3		T84	19		T126	2
all_values[59]	3776	1			T78	7		T84	20		T126	2
all_values[60]	3740	1			T78	4		T84	11		T572	4
all_values[61]	3638	1			T78	2		T84	10		T126	3
all_values[62]	3700	1			T78	2		T84	19		T572	10
all_values[63]	3682	1			T78	5		T84	18		T126	3