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 LINE       60
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T78,T79,T80
1	1	Covered	T4,T5,T6

 LINE       72
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T87,T90,T91
1	0	Not Covered

 LINE       79
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T87,T90,T91
0	1	0	Covered	T126,T485,T486
1	0	0	Covered	T87,T90,T91

 LINE       121
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T6
0	0	1	Covered	T126,T485,T486
0	1	0	Covered	T78,T84,T389
1	0	0	Covered	T78,T79,T80

 LINE       5866
 EXPRESSION (mio_periph_insel_0_we & mio_periph_insel_regwen_0_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T383,T144
1	1	Covered	T2,T39,T12

 LINE       5898
 EXPRESSION (mio_periph_insel_1_we & mio_periph_insel_regwen_1_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T145,T384,T380
1	1	Covered	T2,T36,T39

 LINE       5930
 EXPRESSION (mio_periph_insel_2_we & mio_periph_insel_regwen_2_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T132,T384,T380
1	1	Covered	T2,T36,T39

 LINE       5962
 EXPRESSION (mio_periph_insel_3_we & mio_periph_insel_regwen_3_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T383,T144
1	1	Covered	T2,T39,T12

 LINE       5994
 EXPRESSION (mio_periph_insel_4_we & mio_periph_insel_regwen_4_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T132,T133,T145
1	1	Covered	T2,T36,T39

 LINE       6026
 EXPRESSION (mio_periph_insel_5_we & mio_periph_insel_regwen_5_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T380,T381,T487
1	1	Covered	T2,T36,T39

 LINE       6058
 EXPRESSION (mio_periph_insel_6_we & mio_periph_insel_regwen_6_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T383,T144,T384
1	1	Covered	T2,T36,T39

 LINE       6090
 EXPRESSION (mio_periph_insel_7_we & mio_periph_insel_regwen_7_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T380,T381,T487
1	1	Covered	T2,T36,T39

 LINE       6122
 EXPRESSION (mio_periph_insel_8_we & mio_periph_insel_regwen_8_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T145,T381,T420
1	1	Covered	T2,T36,T39

 LINE       6154
 EXPRESSION (mio_periph_insel_9_we & mio_periph_insel_regwen_9_qs)
             ----------1----------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T383,T144,T145
1	1	Covered	T36,T39,T40

 LINE       6186
 EXPRESSION (mio_periph_insel_10_we & mio_periph_insel_regwen_10_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T383,T144,T419
1	1	Covered	T36,T39,T40

 LINE       6218
 EXPRESSION (mio_periph_insel_11_we & mio_periph_insel_regwen_11_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T133,T383
1	1	Covered	T39,T40,T89

 LINE       6250
 EXPRESSION (mio_periph_insel_12_we & mio_periph_insel_regwen_12_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T383,T144
1	1	Covered	T39,T40,T89

 LINE       6282
 EXPRESSION (mio_periph_insel_13_we & mio_periph_insel_regwen_13_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T145,T380,T381
1	1	Covered	T36,T39,T40

 LINE       6314
 EXPRESSION (mio_periph_insel_14_we & mio_periph_insel_regwen_14_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T380,T381
1	1	Covered	T39,T40,T89

 LINE       6346
 EXPRESSION (mio_periph_insel_15_we & mio_periph_insel_regwen_15_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T383,T145,T380
1	1	Covered	T36,T39,T40

 LINE       6378
 EXPRESSION (mio_periph_insel_16_we & mio_periph_insel_regwen_16_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T419,T409
1	1	Covered	T39,T40,T89

 LINE       6410
 EXPRESSION (mio_periph_insel_17_we & mio_periph_insel_regwen_17_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T383,T144,T145
1	1	Covered	T36,T39,T40

 LINE       6442
 EXPRESSION (mio_periph_insel_18_we & mio_periph_insel_regwen_18_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T132,T383
1	1	Covered	T39,T40,T89

 LINE       6474
 EXPRESSION (mio_periph_insel_19_we & mio_periph_insel_regwen_19_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T133,T383,T145
1	1	Covered	T36,T39,T40

 LINE       6506
 EXPRESSION (mio_periph_insel_20_we & mio_periph_insel_regwen_20_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T133,T383,T144
1	1	Covered	T36,T39,T40

 LINE       6538
 EXPRESSION (mio_periph_insel_21_we & mio_periph_insel_regwen_21_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T132,T133,T145
1	1	Covered	T36,T39,T40

 LINE       6570
 EXPRESSION (mio_periph_insel_22_we & mio_periph_insel_regwen_22_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T383,T144
1	1	Covered	T4,T5,T6

 LINE       6602
 EXPRESSION (mio_periph_insel_23_we & mio_periph_insel_regwen_23_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T132,T380,T381
1	1	Covered	T4,T5,T6

 LINE       6634
 EXPRESSION (mio_periph_insel_24_we & mio_periph_insel_regwen_24_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T383,T145,T380
1	1	Covered	T4,T5,T6

 LINE       6666
 EXPRESSION (mio_periph_insel_25_we & mio_periph_insel_regwen_25_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T383,T380,T381
1	1	Covered	T36,T39,T40

 LINE       6698
 EXPRESSION (mio_periph_insel_26_we & mio_periph_insel_regwen_26_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T383,T384,T381
1	1	Covered	T36,T39,T40

 LINE       6730
 EXPRESSION (mio_periph_insel_27_we & mio_periph_insel_regwen_27_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T384,T381
1	1	Covered	T39,T40,T89

 LINE       6762
 EXPRESSION (mio_periph_insel_28_we & mio_periph_insel_regwen_28_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T133,T383
1	1	Covered	T39,T40,T89

 LINE       6794
 EXPRESSION (mio_periph_insel_29_we & mio_periph_insel_regwen_29_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T133,T384,T380
1	1	Covered	T36,T39,T40

 LINE       6826
 EXPRESSION (mio_periph_insel_30_we & mio_periph_insel_regwen_30_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T132,T133,T383
1	1	Covered	T36,T39,T40

 LINE       6858
 EXPRESSION (mio_periph_insel_31_we & mio_periph_insel_regwen_31_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T133,T383,T381
1	1	Covered	T36,T39,T40

 LINE       6890
 EXPRESSION (mio_periph_insel_32_we & mio_periph_insel_regwen_32_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T133,T383,T380
1	1	Covered	T36,T215,T346

 LINE       6922
 EXPRESSION (mio_periph_insel_33_we & mio_periph_insel_regwen_33_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T383,T144,T381
1	1	Covered	T36,T215,T346

 LINE       6954
 EXPRESSION (mio_periph_insel_34_we & mio_periph_insel_regwen_34_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T132,T383,T145
1	1	Covered	T219,T36,T366

 LINE       6986
 EXPRESSION (mio_periph_insel_35_we & mio_periph_insel_regwen_35_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T133,T383,T380
1	1	Covered	T219,T36,T366

 LINE       7018
 EXPRESSION (mio_periph_insel_36_we & mio_periph_insel_regwen_36_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T383,T380,T381
1	1	Covered	T220,T36,T344

 LINE       7050
 EXPRESSION (mio_periph_insel_37_we & mio_periph_insel_regwen_37_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T145,T381,T420
1	1	Covered	T220,T36,T344

 LINE       7082
 EXPRESSION (mio_periph_insel_38_we & mio_periph_insel_regwen_38_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T133,T383,T144
1	1	Covered	T36,T27,T46

 LINE       7114
 EXPRESSION (mio_periph_insel_39_we & mio_periph_insel_regwen_39_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T383,T144,T384
1	1	Covered	T36,T27,T46

 LINE       7146
 EXPRESSION (mio_periph_insel_40_we & mio_periph_insel_regwen_40_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T384,T380,T381
1	1	Covered	T36,T27,T46

 LINE       7178
 EXPRESSION (mio_periph_insel_41_we & mio_periph_insel_regwen_41_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T383,T144,T380
1	1	Covered	T26,T36,T27

 LINE       7210
 EXPRESSION (mio_periph_insel_42_we & mio_periph_insel_regwen_42_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T132,T383,T381
1	1	Covered	T4,T5,T6

 LINE       7242
 EXPRESSION (mio_periph_insel_43_we & mio_periph_insel_regwen_43_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T132,T380,T381
1	1	Covered	T4,T5,T6

 LINE       7274
 EXPRESSION (mio_periph_insel_44_we & mio_periph_insel_regwen_44_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T383,T381,T409
1	1	Covered	T146,T147,T143

 LINE       7306
 EXPRESSION (mio_periph_insel_45_we & mio_periph_insel_regwen_45_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T144,T380,T381
1	1	Covered	T29,T30,T31

 LINE       7338
 EXPRESSION (mio_periph_insel_46_we & mio_periph_insel_regwen_46_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T132,T383,T144
1	1	Covered	T51,T36,T52

 LINE       7370
 EXPRESSION (mio_periph_insel_47_we & mio_periph_insel_regwen_47_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T36,T383,T145
1	1	Covered	T132,T488,T133

 LINE       7402
 EXPRESSION (mio_periph_insel_48_we & mio_periph_insel_regwen_48_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T383,T380,T419
1	1	Covered	T36,T489,T132

 LINE       7434
 EXPRESSION (mio_periph_insel_49_we & mio_periph_insel_regwen_49_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T384,T380,T487
1	1	Covered	T36,T490,T132

 LINE       7466
 EXPRESSION (mio_periph_insel_50_we & mio_periph_insel_regwen_50_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T132,T381,T491
1	1	Covered	T48,T36,T207

 LINE       7498
 EXPRESSION (mio_periph_insel_51_we & mio_periph_insel_regwen_51_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T145,T384,T381
1	1	Covered	T34,T492,T35

 LINE       7530
 EXPRESSION (mio_periph_insel_52_we & mio_periph_insel_regwen_52_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T132,T383,T381
1	1	Covered	T34,T35,T36

 LINE       7562
 EXPRESSION (mio_periph_insel_53_we & mio_periph_insel_regwen_53_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T383,T144,T145
1	1	Covered	T34,T35,T36

 LINE       7594
 EXPRESSION (mio_periph_insel_54_we & mio_periph_insel_regwen_54_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T144,T380,T381
1	1	Covered	T48,T1,T34

 LINE       7626
 EXPRESSION (mio_periph_insel_55_we & mio_periph_insel_regwen_55_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T133,T383,T144
1	1	Covered	T48,T36,T207

 LINE       7658
 EXPRESSION (mio_periph_insel_56_we & mio_periph_insel_regwen_56_qs)
             -----------1----------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T133,T383,T144
1	1	Covered	T32,T33,T77

 LINE       9053
 EXPRESSION (mio_outsel_0_we & mio_outsel_regwen_0_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T2,T39,T12

 LINE       9085
 EXPRESSION (mio_outsel_1_we & mio_outsel_regwen_1_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T29,T30,T31

 LINE       9117
 EXPRESSION (mio_outsel_2_we & mio_outsel_regwen_2_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T2,T112,T148

 LINE       9149
 EXPRESSION (mio_outsel_3_we & mio_outsel_regwen_3_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T2,T39,T12

 LINE       9181
 EXPRESSION (mio_outsel_4_we & mio_outsel_regwen_4_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T2,T39,T12

 LINE       9213
 EXPRESSION (mio_outsel_5_we & mio_outsel_regwen_5_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T146,T2,T147

 LINE       9245
 EXPRESSION (mio_outsel_6_we & mio_outsel_regwen_6_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T2,T39,T12

 LINE       9277
 EXPRESSION (mio_outsel_7_we & mio_outsel_regwen_7_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T2,T39,T215

 LINE       9309
 EXPRESSION (mio_outsel_8_we & mio_outsel_regwen_8_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T39,T215,T346

 LINE       9341
 EXPRESSION (mio_outsel_9_we & mio_outsel_regwen_9_qs)
             -------1-------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T26,T27,T28

 LINE       9373
 EXPRESSION (mio_outsel_10_we & mio_outsel_regwen_10_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T26,T27,T28

 LINE       9405
 EXPRESSION (mio_outsel_11_we & mio_outsel_regwen_11_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T26,T28,T199

 LINE       9437
 EXPRESSION (mio_outsel_12_we & mio_outsel_regwen_12_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T26,T27,T28

 LINE       9469
 EXPRESSION (mio_outsel_13_we & mio_outsel_regwen_13_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9501
 EXPRESSION (mio_outsel_14_we & mio_outsel_regwen_14_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9533
 EXPRESSION (mio_outsel_15_we & mio_outsel_regwen_15_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T27,T39,T46

 LINE       9565
 EXPRESSION (mio_outsel_16_we & mio_outsel_regwen_16_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T48,T34,T35

 LINE       9597
 EXPRESSION (mio_outsel_17_we & mio_outsel_regwen_17_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T39,T40,T89

 LINE       9629
 EXPRESSION (mio_outsel_18_we & mio_outsel_regwen_18_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T34,T219,T35

 LINE       9661
 EXPRESSION (mio_outsel_19_we & mio_outsel_regwen_19_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T219,T112,T148

 LINE       9693
 EXPRESSION (mio_outsel_20_we & mio_outsel_regwen_20_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T220,T112,T148

 LINE       9725
 EXPRESSION (mio_outsel_21_we & mio_outsel_regwen_21_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T220,T112,T148

 LINE       9757
 EXPRESSION (mio_outsel_22_we & mio_outsel_regwen_22_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T463,T493,T488

 LINE       9789
 EXPRESSION (mio_outsel_23_we & mio_outsel_regwen_23_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T494,T495,T496

 LINE       9821
 EXPRESSION (mio_outsel_24_we & mio_outsel_regwen_24_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T84,T497,T495

 LINE       9853
 EXPRESSION (mio_outsel_25_we & mio_outsel_regwen_25_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9885
 EXPRESSION (mio_outsel_26_we & mio_outsel_regwen_26_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       9917
 EXPRESSION (mio_outsel_27_we & mio_outsel_regwen_27_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T450,T498,T494

 LINE       9949
 EXPRESSION (mio_outsel_28_we & mio_outsel_regwen_28_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T499,T500,T501

 LINE       9981
 EXPRESSION (mio_outsel_29_we & mio_outsel_regwen_29_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       10013
 EXPRESSION (mio_outsel_30_we & mio_outsel_regwen_30_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T449,T463,T447

 LINE       10045
 EXPRESSION (mio_outsel_31_we & mio_outsel_regwen_31_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T34,T35,T39

 LINE       10077
 EXPRESSION (mio_outsel_32_we & mio_outsel_regwen_32_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T112,T148,T39

 LINE       10109
 EXPRESSION (mio_outsel_33_we & mio_outsel_regwen_33_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T112,T148,T39

 LINE       10141
 EXPRESSION (mio_outsel_34_we & mio_outsel_regwen_34_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T112,T148,T39

 LINE       10173
 EXPRESSION (mio_outsel_35_we & mio_outsel_regwen_35_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T39,T40,T89

 LINE       10205
 EXPRESSION (mio_outsel_36_we & mio_outsel_regwen_36_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T39,T40,T89

 LINE       10237
 EXPRESSION (mio_outsel_37_we & mio_outsel_regwen_37_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T39,T40,T89

 LINE       10269
 EXPRESSION (mio_outsel_38_we & mio_outsel_regwen_38_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T39,T40,T89

 LINE       10301
 EXPRESSION (mio_outsel_39_we & mio_outsel_regwen_39_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T39,T40,T89

 LINE       10333
 EXPRESSION (mio_outsel_40_we & mio_outsel_regwen_40_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T34,T35,T39

 LINE       10365
 EXPRESSION (mio_outsel_41_we & mio_outsel_regwen_41_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T34,T35,T39

 LINE       10397
 EXPRESSION (mio_outsel_42_we & mio_outsel_regwen_42_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T39,T40,T89

 LINE       10429
 EXPRESSION (mio_outsel_43_we & mio_outsel_regwen_43_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T39,T40,T89

 LINE       10461
 EXPRESSION (mio_outsel_44_we & mio_outsel_regwen_44_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T39,T40,T89

 LINE       10493
 EXPRESSION (mio_outsel_45_we & mio_outsel_regwen_45_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T39,T40,T89

 LINE       10525
 EXPRESSION (mio_outsel_46_we & mio_outsel_regwen_46_qs)
             --------1-------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T39,T40,T89

 LINE       11923
 EXPRESSION (mio_pad_attr_0_we & mio_pad_attr_regwen_0_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T452,T466,T502

 LINE       12092
 EXPRESSION (mio_pad_attr_1_we & mio_pad_attr_regwen_1_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T448,T453,T503

 LINE       12261
 EXPRESSION (mio_pad_attr_2_we & mio_pad_attr_regwen_2_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T27,T46,T47

 LINE       12430
 EXPRESSION (mio_pad_attr_3_we & mio_pad_attr_regwen_3_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T503,T504,T505

 LINE       12599
 EXPRESSION (mio_pad_attr_4_we & mio_pad_attr_regwen_4_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T506,T488,T507

 LINE       12768
 EXPRESSION (mio_pad_attr_5_we & mio_pad_attr_regwen_5_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T508,T509,T510

 LINE       12937
 EXPRESSION (mio_pad_attr_6_we & mio_pad_attr_regwen_6_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T511,T512,T513

 LINE       13106
 EXPRESSION (mio_pad_attr_7_we & mio_pad_attr_regwen_7_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T51,T52,T53

 LINE       13275
 EXPRESSION (mio_pad_attr_8_we & mio_pad_attr_regwen_8_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T452,T514,T515

 LINE       13444
 EXPRESSION (mio_pad_attr_9_we & mio_pad_attr_regwen_9_qs)
             --------1--------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T27,T46,T47

 LINE       13613
 EXPRESSION (mio_pad_attr_10_we & mio_pad_attr_regwen_10_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T26,T27,T28

 LINE       13782
 EXPRESSION (mio_pad_attr_11_we & mio_pad_attr_regwen_11_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T447,T511,T516

 LINE       13951
 EXPRESSION (mio_pad_attr_12_we & mio_pad_attr_regwen_12_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T26,T27,T28

 LINE       14120
 EXPRESSION (mio_pad_attr_13_we & mio_pad_attr_regwen_13_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T27,T46,T47

 LINE       14289
 EXPRESSION (mio_pad_attr_14_we & mio_pad_attr_regwen_14_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T27,T46,T47

 LINE       14458
 EXPRESSION (mio_pad_attr_15_we & mio_pad_attr_regwen_15_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T27,T46,T47

 LINE       14627
 EXPRESSION (mio_pad_attr_16_we & mio_pad_attr_regwen_16_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T84,T450,T514

 LINE       14796
 EXPRESSION (mio_pad_attr_17_we & mio_pad_attr_regwen_17_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T517,T518,T519

 LINE       14965
 EXPRESSION (mio_pad_attr_18_we & mio_pad_attr_regwen_18_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T514,T503,T520

 LINE       15134
 EXPRESSION (mio_pad_attr_19_we & mio_pad_attr_regwen_19_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T521,T522,T505

 LINE       15303
 EXPRESSION (mio_pad_attr_20_we & mio_pad_attr_regwen_20_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T508,T515,T523

 LINE       15472
 EXPRESSION (mio_pad_attr_21_we & mio_pad_attr_regwen_21_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T449,T507,T511

 LINE       15641
 EXPRESSION (mio_pad_attr_22_we & mio_pad_attr_regwen_22_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T57,T58,T59

 LINE       15810
 EXPRESSION (mio_pad_attr_23_we & mio_pad_attr_regwen_23_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T57,T58,T59

 LINE       15979
 EXPRESSION (mio_pad_attr_24_we & mio_pad_attr_regwen_24_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T57,T58,T59

 LINE       16148
 EXPRESSION (mio_pad_attr_25_we & mio_pad_attr_regwen_25_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       16317
 EXPRESSION (mio_pad_attr_26_we & mio_pad_attr_regwen_26_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T450,T524,T525

 LINE       16486
 EXPRESSION (mio_pad_attr_27_we & mio_pad_attr_regwen_27_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T452,T466,T526

 LINE       16655
 EXPRESSION (mio_pad_attr_28_we & mio_pad_attr_regwen_28_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T527,T528,T529

 LINE       16824
 EXPRESSION (mio_pad_attr_29_we & mio_pad_attr_regwen_29_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T530,T531,T532

 LINE       16993
 EXPRESSION (mio_pad_attr_30_we & mio_pad_attr_regwen_30_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T533,T511,T505

 LINE       17162
 EXPRESSION (mio_pad_attr_31_we & mio_pad_attr_regwen_31_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T452,T453,T449

 LINE       17331
 EXPRESSION (mio_pad_attr_32_we & mio_pad_attr_regwen_32_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T534,T519,T535

 LINE       17500
 EXPRESSION (mio_pad_attr_33_we & mio_pad_attr_regwen_33_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T494,T536,T537

 LINE       17669
 EXPRESSION (mio_pad_attr_34_we & mio_pad_attr_regwen_34_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T538,T539,T540

 LINE       17838
 EXPRESSION (mio_pad_attr_35_we & mio_pad_attr_regwen_35_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T448,T488,T541

 LINE       18007
 EXPRESSION (mio_pad_attr_36_we & mio_pad_attr_regwen_36_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T500,T503,T511

 LINE       18176
 EXPRESSION (mio_pad_attr_37_we & mio_pad_attr_regwen_37_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T501,T542,T536

 LINE       18345
 EXPRESSION (mio_pad_attr_38_we & mio_pad_attr_regwen_38_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T543,T544,T541

 LINE       18514
 EXPRESSION (mio_pad_attr_39_we & mio_pad_attr_regwen_39_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T447,T508,T513

 LINE       18683
 EXPRESSION (mio_pad_attr_40_we & mio_pad_attr_regwen_40_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T545,T508,T546

 LINE       18852
 EXPRESSION (mio_pad_attr_41_we & mio_pad_attr_regwen_41_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T502,T547,T548

 LINE       19021
 EXPRESSION (mio_pad_attr_42_we & mio_pad_attr_regwen_42_qs)
             ---------1--------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T466,T549,T515