Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	141542	1			T81	3		T82	72		T83	9
values[2]	10092	1			T82	3		T550	5		T256	56
values[3]	4029	1			T82	1		T256	11		T551	99
values[4]	2348	1			T256	9		T551	54		T557	81
values[5]	1450	1			T256	3		T551	16		T557	41
values[6]	1002	1			T256	3		T551	12		T557	18
values[7]	724	1			T256	8		T551	13		T557	1
values[8]	580	1			T256	10		T551	30		T719	2
values[9]	517	1			T256	6		T551	13		T912	2
values[10]	467	1			T256	13		T551	11		T912	2
values[11]	415	1			T256	5		T551	6		T912	1
values[12]	400	1			T256	7		T912	1		T733	8
values[13]	280	1			T256	5		T912	1		T733	8
values[14]	304	1			T256	6		T912	2		T733	3
values[15]	298	1			T912	5		T733	11		T906	3
values[16]	309	1			T912	1		T733	6		T906	8
values[17]	270	1			T912	2		T733	6		T906	6
values[18]	287	1			T912	4		T733	10		T906	4
values[19]	243	1			T912	2		T733	14		T906	3
values[20]	318	1			T912	10		T733	10		T906	2
values[21]	310	1			T912	8		T733	7		T906	5
values[22]	309	1			T912	4		T733	5		T906	7
values[23]	255	1			T912	3		T733	2		T906	4
values[24]	284	1			T912	3		T733	3		T906	1
values[25]	242	1			T912	5		T733	5		T906	2
values[26]	235	1			T912	1		T733	3		T906	3
values[27]	263	1			T912	1		T906	3		T686	3
values[28]	269	1			T912	2		T906	5		T686	5
values[29]	316	1			T912	3		T906	3		T686	6
values[30]	254	1			T912	4		T906	6		T686	2
values[31]	248	1			T912	5		T906	8		T686	2
values[32]	265	1			T912	3		T906	2		T686	5
values[33]	267	1			T912	2		T906	5		T686	5
values[34]	240	1			T912	5		T906	3		T686	1
values[35]	247	1			T912	3		T906	1		T686	3
values[36]	266	1			T912	1		T906	2		T686	3
values[37]	280	1			T912	2		T906	1		T686	3
values[38]	225	1			T912	1		T906	5		T686	2
values[39]	204	1			T912	2		T906	2		T686	3
values[40]	234	1			T912	1		T906	1		T686	1
values[41]	230	1			T912	3		T906	2		T686	1
values[42]	259	1			T912	5		T906	9		T686	1
values[43]	235	1			T912	4		T906	6		T686	6
values[44]	264	1			T912	1		T906	6		T686	3
values[45]	265	1			T912	2		T906	3		T686	2
values[46]	282	1			T912	2		T906	2		T686	2
values[47]	246	1			T912	2		T906	2		T686	2
values[48]	307	1			T912	2		T906	3		T686	3
values[49]	232	1			T912	1		T906	2		T686	1
values[50]	208	1			T912	2		T906	4		T686	4
values[51]	216	1			T912	3		T906	3		T686	5
values[52]	195	1			T912	5		T906	4		T686	3
values[53]	227	1			T912	3		T906	1		T686	2
values[54]	251	1			T912	3		T906	1		T686	5
values[55]	217	1			T912	3		T906	2		T686	5
values[56]	206	1			T912	1		T906	1		T686	4
values[57]	199	1			T912	2		T906	4		T686	4
values[58]	205	1			T912	3		T906	1		T686	4
values[59]	187	1			T912	2		T906	2		T686	1
values[60]	171	1			T912	2		T906	6		T686	1
values[61]	141	1			T912	1		T906	3		T686	2
values[62]	149	1			T912	1		T906	3		T686	1
values[63]	141	1			T912	3		T906	1		T686	2
values[64]	167	1			T912	2		T906	2		T686	5
values[65]	123	1			T912	1		T906	2		T686	4
values[66]	153	1			T912	1		T906	5		T686	2
values[67]	123	1			T912	3		T906	1		T686	4
values[68]	126	1			T912	3		T906	1		T686	7
values[69]	104	1			T912	4		T906	2		T686	5
values[70]	79	1			T912	1		T906	2		T686	4
values[71]	99	1			T912	2		T906	2		T686	4
values[72]	85	1			T912	2		T906	1		T686	7
values[73]	71	1			T912	5		T906	2		T686	4
values[74]	40	1			T912	3		T906	1		T686	1
values[75]	43	1			T912	3		T906	2		T686	1
values[76]	57	1			T912	2		T906	2		T686	6
values[77]	60	1			T912	4		T906	5		T686	4
values[78]	52	1			T912	4		T906	5		T686	8
values[79]	72	1			T912	9		T906	2		T686	5
values[80]	62	1			T912	7		T906	1		T686	6
values[81]	62	1			T912	3		T906	5		T686	4
values[82]	59	1			T912	7		T906	9		T686	3
values[83]	48	1			T912	4		T906	3		T686	3
values[84]	56	1			T912	10		T906	1		T686	4
values[85]	48	1			T912	3		T906	2		T686	5
values[86]	65	1			T912	2		T906	1		T686	6
values[87]	66	1			T912	8		T906	4		T686	8
values[88]	78	1			T912	12		T906	7		T686	10
values[89]	92	1			T912	18		T906	2		T686	7
values[90]	95	1			T912	14		T906	1		T686	3
values[91]	90	1			T912	13		T906	2		T686	7
values[92]	71	1			T912	7		T906	1		T686	3
values[93]	98	1			T912	6		T906	2		T686	6
values[94]	97	1			T912	6		T906	7		T686	5
values[95]	77	1			T912	7		T906	4		T686	2
values[96]	69	1			T912	8		T906	1		T686	2
values[97]	76	1			T912	5		T906	2		T686	7
values[98]	69	1			T912	4		T906	2		T686	3
values[99]	55	1			T912	5		T906	1		T686	5
values[100]	66	1			T912	3		T906	1		T686	9
values[101]	47	1			T912	5		T906	2		T686	1
values[102]	53	1			T912	5		T906	1		T686	1
values[103]	54	1			T912	4		T906	2		T686	3
values[104]	53	1			T912	6		T906	3		T686	1
values[105]	76	1			T912	6		T906	3		T686	2
values[106]	66	1			T912	7		T906	2		T686	2
values[107]	82	1			T912	9		T906	6		T686	3
values[108]	69	1			T912	4		T906	8		T686	2
values[109]	67	1			T912	4		T906	5		T686	3
values[110]	81	1			T912	8		T906	10		T686	6
values[111]	89	1			T912	21		T906	7		T686	11
values[112]	71	1			T912	9		T906	8		T686	9
values[113]	79	1			T912	14		T906	3		T686	19
values[114]	76	1			T912	7		T906	4		T686	17
values[115]	73	1			T912	3		T906	6		T686	6
values[116]	62	1			T912	3		T906	3		T686	3
values[117]	63	1			T912	4		T906	6		T892	5
values[118]	63	1			T912	6		T906	2		T892	4
values[119]	55	1			T912	5		T906	2		T892	3
values[120]	81	1			T912	6		T906	9		T892	2
values[121]	74	1			T912	8		T906	7		T892	2
values[122]	60	1			T912	7		T906	4		T892	3
values[123]	58	1			T912	14		T906	2		T892	2
values[124]	65	1			T912	7		T906	11		T892	2
values[125]	91	1			T912	3		T906	13		T892	3
values[126]	146	1			T912	12		T906	24		T892	3
values[127]	704	1			T912	26		T906	57		T892	56
values[128]	5373	1			T912	11		T906	17		T892	640