Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.98	95.29	93.64	95.33		94.46	97.53	99.62

Total tests in report: 2932

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
43.19	43.19	55.92	55.92	49.94	49.94	26.44	26.44			67.78	67.78	58.92	58.92	0.13	0.13	/workspace/coverage/default/2.chip_plic_all_irqs_20.1406376630
52.66	9.47	62.05	6.13	63.66	13.71	27.04	0.61			77.57	9.79	84.09	25.17	1.53	1.40	/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.596459095
57.81	5.15	73.98	11.94	65.67	2.01	34.39	7.35			78.05	0.48	84.09	0.00	10.65	9.12	/workspace/coverage/cover_reg_top/4.xbar_random_large_delays.1995322161
61.38	3.57	73.98	0.00	65.82	0.15	34.39	0.00			78.07	0.02	84.09	0.00	31.91	21.27	/workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.2463724890
64.83	3.46	80.02	6.04	70.13	4.30	38.25	3.86			80.05	1.98	88.64	4.55	31.91	0.00	/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3444442978
67.81	2.98	80.03	0.01	70.15	0.02	56.04	17.79			80.06	0.02	88.64	0.00	31.96	0.05	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3168978075
70.51	2.70	81.11	1.08	71.06	0.91	69.28	13.23			80.67	0.61	88.99	0.35	31.97	0.01	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2588624600
73.02	2.51	81.11	0.00	71.06	0.00	69.28	0.00			80.67	0.00	88.99	0.00	47.02	15.05	/workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.843015111
75.10	2.08	81.22	0.11	73.89	2.83	70.04	0.76			80.89	0.22	88.99	0.00	55.55	8.53	/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.2258375043
76.77	1.67	83.23	2.01	76.61	2.72	71.70	1.66			82.85	1.96	88.99	0.00	57.22	1.67	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3404080241
78.40	1.63	85.39	2.16	78.86	2.25	74.41	2.71			85.52	2.67	88.99	0.00	57.22	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1811843985
80.03	1.63	85.39	0.00	78.86	0.00	74.41	0.00			85.52	0.00	88.99	0.00	67.01	9.79	/workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.4014637640
81.59	1.56	85.39	0.00	78.86	0.00	74.41	0.00			85.52	0.00	88.99	0.00	76.36	9.35	/workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.4116626896
83.14	1.56	85.68	0.29	79.02	0.16	82.59	8.19			85.70	0.18	89.51	0.52	76.36	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.263896491
84.69	1.54	88.02	2.34	82.44	3.43	82.86	0.26			88.92	3.23	89.51	0.00	76.36	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1017738580
85.65	0.96	89.35	1.32	83.52	1.08	83.29	0.44			90.09	1.16	91.26	1.75	76.40	0.04	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3354166512
86.59	0.94	89.35	0.00	84.21	0.69	83.29	0.00			90.33	0.24	91.26	0.00	81.12	4.72	/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.1362495205
87.43	0.84	90.07	0.72	84.42	0.20	83.31	0.01			90.56	0.23	95.10	3.85	81.12	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.530517608
88.15	0.72	90.07	0.00	84.42	0.00	83.31	0.00			90.56	0.00	95.10	0.00	85.44	4.32	/workspace/coverage/cover_reg_top/99.xbar_access_same_device.3021113926
88.78	0.63	91.22	1.15	85.57	1.15	83.74	0.43			91.61	1.05	95.10	0.00	85.44	0.00	/workspace/coverage/default/0.chip_sw_gpio.3559316014
89.39	0.61	91.22	0.00	85.69	0.13	83.74	0.00			91.61	0.00	95.10	0.00	88.98	3.54	/workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.2383783486
89.90	0.51	91.74	0.52	86.15	0.46	85.36	1.62			92.07	0.46	95.10	0.00	88.98	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.3476665174
90.40	0.50	91.75	0.01	88.71	2.55	85.36	0.00			92.07	0.00	95.10	0.00	89.39	0.41	/workspace/coverage/cover_reg_top/14.chip_tl_errors.1218686001
90.88	0.48	91.75	0.00	88.71	0.00	85.36	0.00			92.07	0.00	95.10	0.00	92.28	2.89	/workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.915522839
91.22	0.34	91.76	0.01	88.71	0.01	87.36	1.99			92.07	0.00	95.10	0.00	92.32	0.04	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.371867909
91.56	0.34	92.53	0.77	88.89	0.18	87.66	0.31			92.15	0.07	95.80	0.70	92.32	0.00	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.730842586
91.88	0.32	92.53	0.00	88.89	0.00	87.66	0.00			92.15	0.00	95.80	0.00	94.23	1.92	/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.445412862
92.18	0.30	92.58	0.05	88.95	0.06	89.10	1.44			92.19	0.04	95.98	0.17	94.27	0.04	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3969306536
92.43	0.26	92.58	0.00	88.97	0.01	89.10	0.00			92.19	0.00	95.98	0.00	95.79	1.53	/workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.1496260218
92.66	0.23	92.75	0.17	89.17	0.20	89.87	0.77			92.39	0.20	95.98	0.00	95.83	0.04	/workspace/coverage/default/1.chip_jtag_csr_rw.4046416673
92.87	0.21	92.83	0.08	89.71	0.53	89.89	0.02			92.99	0.60	95.98	0.00	95.83	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3452884544
93.06	0.19	92.83	0.00	89.71	0.00	89.89	0.00			92.99	0.00	95.98	0.00	96.96	1.13	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.317800175
93.23	0.17	93.19	0.36	90.03	0.32	90.25	0.35			92.99	0.00	95.98	0.00	96.96	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1614284377
93.38	0.15	93.19	0.00	90.03	0.00	91.14	0.90			92.99	0.00	95.98	0.00	96.96	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1999823967
93.52	0.14	93.44	0.25	90.31	0.28	91.15	0.01			93.30	0.31	95.98	0.00	96.96	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_rw.2673562585
93.66	0.14	93.49	0.05	90.37	0.06	91.63	0.48			93.30	0.00	95.98	0.00	97.18	0.22	/workspace/coverage/default/2.chip_sw_alert_test.2084645345
93.78	0.12	93.72	0.23	90.56	0.19	91.64	0.01			93.61	0.32	95.98	0.00	97.18	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1712856213
93.91	0.12	93.83	0.11	90.63	0.07	91.84	0.19			93.64	0.02	96.33	0.35	97.18	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1991309754
94.02	0.11	93.83	0.00	90.63	0.01	91.84	0.00			93.64	0.00	96.33	0.00	97.85	0.67	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.2955391471
94.12	0.10	94.01	0.18	90.70	0.07	91.95	0.11			93.68	0.04	96.50	0.17	97.86	0.01	/workspace/coverage/default/5.chip_sw_all_escalation_resets.135611050
94.21	0.09	94.02	0.01	90.96	0.26	91.95	0.00			93.97	0.29	96.50	0.00	97.86	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.31807529
94.30	0.09	94.02	0.00	90.96	0.00	92.48	0.53			93.97	0.00	96.50	0.00	97.86	0.00	/workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.3538716667
94.38	0.08	94.02	0.00	91.44	0.48	92.48	0.00			93.97	0.00	96.50	0.00	97.87	0.01	/workspace/coverage/cover_reg_top/20.chip_tl_errors.3482040912
94.46	0.08	94.02	0.00	91.44	0.00	92.94	0.45			93.97	0.00	96.50	0.00	97.87	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1496569966
94.52	0.06	94.02	0.00	91.44	0.00	93.30	0.36			93.97	0.00	96.50	0.00	97.87	0.00	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2676807724
94.57	0.06	94.03	0.01	91.50	0.06	93.37	0.07			94.00	0.02	96.68	0.17	97.87	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.618314398
94.63	0.05	94.11	0.08	91.52	0.01	93.38	0.01			94.02	0.02	96.85	0.17	97.89	0.01	/workspace/coverage/default/46.chip_sw_all_escalation_resets.3447115389
94.68	0.05	94.11	0.00	91.81	0.29	93.38	0.00			94.02	0.00	96.85	0.00	97.89	0.00	/workspace/coverage/cover_reg_top/3.chip_tl_errors.865634991
94.72	0.05	94.24	0.13	91.81	0.00	93.52	0.15			94.04	0.02	96.85	0.00	97.89	0.00	/workspace/coverage/default/2.chip_tap_straps_rma.3949180795
94.77	0.05	94.34	0.10	91.85	0.04	93.62	0.09			94.09	0.05	96.85	0.00	97.89	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.241968669
94.82	0.05	94.40	0.07	91.99	0.14	93.62	0.00			94.17	0.08	96.85	0.00	97.89	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1786448782
94.87	0.05	94.40	0.00	91.99	0.00	93.89	0.28			94.17	0.00	96.85	0.00	97.89	0.00	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.3320838519
94.91	0.04	94.40	0.00	91.99	0.00	93.89	0.00			94.17	0.00	96.85	0.00	98.13	0.25	/workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.3846378205
94.95	0.04	94.41	0.01	92.00	0.01	93.93	0.03			94.17	0.01	97.03	0.17	98.14	0.01	/workspace/coverage/default/64.chip_sw_all_escalation_resets.2563992010
94.99	0.04	94.42	0.01	92.02	0.01	93.93	0.00			94.20	0.02	97.20	0.17	98.16	0.01	/workspace/coverage/default/33.chip_sw_all_escalation_resets.4048872517
95.02	0.04	94.42	0.01	92.03	0.01	93.93	0.01			94.21	0.01	97.38	0.17	98.17	0.01	/workspace/coverage/default/87.chip_sw_all_escalation_resets.1339499032
95.06	0.04	94.42	0.00	92.03	0.00	93.97	0.04			94.21	0.00	97.55	0.17	98.17	0.00	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.2301009634
95.09	0.03	94.42	0.00	92.15	0.11	93.97	0.00			94.21	0.00	97.55	0.00	98.26	0.09	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.295471458
95.13	0.03	94.42	0.00	92.15	0.00	94.18	0.20			94.21	0.00	97.55	0.00	98.26	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.261633743
95.16	0.03	94.45	0.03	92.18	0.04	94.27	0.09			94.23	0.02	97.55	0.00	98.26	0.00	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3039074497
95.19	0.03	94.45	0.00	92.24	0.06	94.27	0.00			94.25	0.02	97.55	0.00	98.36	0.09	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.1033826557
95.21	0.03	94.45	0.00	92.24	0.00	94.43	0.16			94.25	0.00	97.55	0.00	98.36	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.4044078626
95.24	0.03	94.47	0.02	92.33	0.09	94.45	0.02			94.27	0.02	97.55	0.00	98.36	0.00	/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3250051607
95.26	0.03	94.47	0.00	92.33	0.00	94.60	0.15			94.27	0.00	97.55	0.00	98.36	0.00	/workspace/coverage/default/0.chip_sw_edn_sw_mode.269094851
95.29	0.02	94.47	0.00	92.48	0.14	94.60	0.00			94.27	0.00	97.55	0.00	98.36	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.623639272
95.31	0.02	94.49	0.02	92.49	0.01	94.71	0.11			94.28	0.01	97.55	0.00	98.36	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.3894028682
95.34	0.02	94.49	0.00	92.63	0.14	94.71	0.00			94.28	0.00	97.55	0.00	98.36	0.00	/workspace/coverage/cover_reg_top/4.chip_tl_errors.1042152824
95.36	0.02	94.55	0.07	92.68	0.05	94.71	0.00			94.30	0.02	97.55	0.00	98.36	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.698229835
95.38	0.02	94.55	0.00	92.70	0.02	94.71	0.00			94.31	0.02	97.55	0.00	98.44	0.08	/workspace/coverage/cover_reg_top/85.xbar_access_same_device.921410928
95.40	0.02	94.55	0.00	92.70	0.00	94.82	0.11			94.31	0.00	97.55	0.00	98.44	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.685571746
95.41	0.02	94.58	0.03	92.75	0.04	94.83	0.01			94.34	0.02	97.55	0.00	98.44	0.00	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.4246814228
95.43	0.01	94.58	0.00	92.83	0.09	94.83	0.00			94.34	0.00	97.55	0.00	98.44	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.787437560
95.44	0.01	94.58	0.00	92.85	0.02	94.83	0.00			94.34	0.00	97.55	0.00	98.51	0.07	/workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.2248006844
95.46	0.01	94.58	0.00	92.92	0.06	94.83	0.00			94.35	0.02	97.55	0.00	98.51	0.00	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.4168213051
95.47	0.01	94.58	0.00	92.99	0.07	94.83	0.00			94.35	0.00	97.55	0.00	98.51	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.839783680
95.48	0.01	94.58	0.00	92.99	0.00	94.90	0.07			94.35	0.00	97.55	0.00	98.51	0.00	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1475736909
95.49	0.01	94.59	0.01	93.01	0.03	94.90	0.01			94.37	0.02	97.55	0.00	98.51	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3057445542
95.50	0.01	94.59	0.00	93.07	0.05	94.90	0.00			94.37	0.00	97.55	0.00	98.52	0.01	/workspace/coverage/cover_reg_top/0.chip_tl_errors.1861997376
95.51	0.01	94.59	0.00	93.08	0.01	94.90	0.00			94.37	0.00	97.55	0.00	98.57	0.05	/workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.518710844
95.52	0.01	94.59	0.00	93.08	0.00	94.90	0.00			94.37	0.00	97.55	0.00	98.63	0.06	/workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.3866617836
95.53	0.01	94.62	0.02	93.10	0.02	94.92	0.01			94.37	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/default/0.chip_sw_power_sleep_load.1968299905
95.54	0.01	94.63	0.01	93.13	0.03	94.92	0.00			94.38	0.01	97.55	0.00	98.63	0.00	/workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.2321550271
95.55	0.01	94.63	0.00	93.13	0.00	94.97	0.05			94.38	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1518315367
95.56	0.01	94.63	0.00	93.15	0.01	95.00	0.03			94.39	0.01	97.55	0.00	98.63	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.155206678
95.56	0.01	94.65	0.02	93.15	0.01	95.01	0.01			94.40	0.02	97.55	0.00	98.63	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3251244639
95.57	0.01	94.67	0.02	93.16	0.01	95.01	0.01			94.42	0.02	97.55	0.00	98.63	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2965666576
95.58	0.01	94.67	0.00	93.19	0.03	95.01	0.00			94.43	0.02	97.55	0.00	98.63	0.00	/workspace/coverage/cover_reg_top/6.xbar_access_same_device.1777978646
95.59	0.01	94.67	0.00	93.19	0.00	95.01	0.00			94.43	0.00	97.55	0.00	98.67	0.05	/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2759395761
95.60	0.01	94.67	0.00	93.19	0.00	95.05	0.04			94.43	0.00	97.55	0.00	98.67	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.1290067769
95.60	0.01	94.67	0.00	93.19	0.00	95.05	0.00			94.43	0.00	97.55	0.00	98.71	0.04	/workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.877461635
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95.82	0.01	94.69	0.00	93.46	0.00	95.22	0.00			94.43	0.00	97.55	0.00	99.53	0.01	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3285029
95.82	0.01	94.69	0.00	93.46	0.00	95.22	0.00			94.43	0.00	97.55	0.00	99.54	0.01	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3254335469
95.82	0.01	94.69	0.00	93.46	0.00	95.22	0.00			94.43	0.00	97.55	0.00	99.55	0.01	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.433944802
95.82	0.01	94.69	0.00	93.46	0.00	95.22	0.00			94.43	0.00	97.55	0.00	99.57	0.01	/workspace/coverage/default/79.chip_sw_all_escalation_resets.3489949688
95.82	0.01	94.69	0.00	93.46	0.00	95.22	0.00			94.43	0.00	97.55	0.00	99.58	0.01	/workspace/coverage/default/8.chip_sw_all_escalation_resets.1847324229
95.82	0.01	94.69	0.00	93.46	0.00	95.22	0.00			94.43	0.00	97.55	0.00	99.59	0.01	/workspace/coverage/default/85.chip_sw_all_escalation_resets.1256922794
95.83	0.01	94.69	0.00	93.46	0.00	95.22	0.00			94.43	0.00	97.55	0.00	99.60	0.01	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1043560979
95.83	0.01	94.69	0.00	93.46	0.00	95.22	0.00			94.43	0.00	97.55	0.00	99.61	0.01	/workspace/coverage/default/91.chip_sw_all_escalation_resets.973981412
95.83	0.01	94.69	0.00	93.46	0.00	95.22	0.00			94.43	0.00	97.55	0.00	99.62	0.01	/workspace/coverage/default/99.chip_sw_all_escalation_resets.1313866668
95.83	0.01	94.69	0.00	93.46	0.00	95.24	0.01			94.43	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.410745580
95.83	0.01	94.69	0.00	93.46	0.00	95.25	0.01			94.43	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1797012573
95.84	0.01	94.69	0.00	93.46	0.01	95.25	0.00			94.44	0.01	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.394286116
95.84	0.01	94.69	0.00	93.47	0.01	95.25	0.00			94.44	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.2007296105
95.84	0.01	94.69	0.00	93.48	0.01	95.25	0.00			94.44	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.3339179883
95.84	0.01	94.69	0.00	93.49	0.01	95.25	0.00			94.44	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2436023839
95.84	0.01	94.69	0.00	93.51	0.01	95.25	0.00			94.44	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2286565122
95.85	0.01	94.69	0.00	93.52	0.01	95.25	0.00			94.44	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.360628240
95.85	0.01	94.69	0.00	93.53	0.01	95.25	0.00			94.44	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx.1838641660
95.85	0.01	94.69	0.00	93.54	0.01	95.25	0.00			94.44	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2444861995
95.85	0.01	94.70	0.01	93.54	0.01	95.25	0.00			94.44	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3048456497
95.85	0.01	94.71	0.01	93.54	0.00	95.25	0.00			94.44	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.1892031768
95.85	0.01	94.71	0.00	93.54	0.00	95.26	0.01			94.44	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.3221224083
95.86	0.01	94.71	0.00	93.54	0.00	95.27	0.01			94.44	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3169167172
95.86	0.01	94.71	0.00	93.54	0.00	95.28	0.01			94.44	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2295484164
95.86	0.01	94.71	0.00	93.54	0.00	95.29	0.01			94.44	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.3523390706
95.86	0.01	94.71	0.00	93.54	0.01	95.29	0.01			94.44	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3097465005
95.86	0.01	94.71	0.00	93.54	0.00	95.29	0.00			94.45	0.01	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.4287637859
95.86	0.01	94.71	0.00	93.54	0.00	95.29	0.00			94.46	0.01	97.55	0.00	99.62	0.00	/workspace/coverage/default/4.chip_tap_straps_dev.2189917376
95.86	0.01	94.71	0.00	93.55	0.01	95.29	0.00			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/cover_reg_top/20.xbar_access_same_device.2248211384
95.87	0.01	94.71	0.00	93.56	0.01	95.29	0.00			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.4148035962
95.87	0.01	94.71	0.00	93.57	0.01	95.29	0.00			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.4180818004
95.87	0.01	94.71	0.00	93.57	0.01	95.29	0.00			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/cover_reg_top/51.xbar_stress_all.3986830730
95.87	0.01	94.71	0.00	93.58	0.01	95.29	0.00			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.3316891755
95.87	0.01	94.71	0.00	93.59	0.01	95.29	0.00			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2006992077
95.87	0.01	94.71	0.00	93.59	0.00	95.30	0.01			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/2.chip_sw_kmac_entropy.2400313753
95.87	0.01	94.71	0.01	93.59	0.00	95.30	0.00			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2202568842
95.87	0.01	94.71	0.00	93.59	0.00	95.30	0.01			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.735102820
95.87	0.01	94.71	0.00	93.59	0.00	95.31	0.01			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.822511991
95.87	0.01	94.71	0.00	93.59	0.00	95.31	0.01			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2531634116
95.88	0.01	94.71	0.00	93.59	0.00	95.32	0.01			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2991218418
95.88	0.01	94.71	0.00	93.59	0.01	95.32	0.00			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.2806847619
95.88	0.01	94.71	0.00	93.59	0.01	95.32	0.00			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2515057944
95.88	0.01	94.71	0.00	93.60	0.01	95.32	0.00			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.1127228215
95.88	0.01	94.71	0.00	93.60	0.01	95.32	0.00			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.1443205049
95.88	0.01	94.71	0.00	93.60	0.01	95.32	0.00			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.4063403769
95.88	0.01	94.71	0.00	93.61	0.01	95.32	0.00			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/cover_reg_top/72.xbar_error_random.1852607792
95.88	0.01	94.71	0.00	93.61	0.01	95.32	0.00			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.2790493905
95.88	0.01	94.71	0.00	93.61	0.01	95.32	0.00			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.544515372
95.88	0.01	94.71	0.00	93.62	0.01	95.32	0.00			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.2750648170
95.88	0.01	94.71	0.00	93.62	0.01	95.32	0.00			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.2731261265
95.88	0.01	94.71	0.00	93.63	0.01	95.32	0.00			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1073525502
95.88	0.01	94.71	0.00	93.63	0.01	95.32	0.00			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1585601043
95.88	0.01	94.71	0.00	93.63	0.01	95.32	0.00			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2046905841
95.88	0.01	94.71	0.00	93.64	0.01	95.32	0.00			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1035586225
95.88	0.01	94.71	0.00	93.64	0.00	95.32	0.01			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.chip_tap_straps_testunlock0.3328845115
95.88	0.01	94.71	0.00	93.64	0.00	95.32	0.01			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.248843882
95.88	0.01	94.71	0.00	93.64	0.00	95.32	0.01			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.146978911
95.89	0.01	94.71	0.00	93.64	0.00	95.33	0.01			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.4076489605
95.89	0.01	94.71	0.00	93.64	0.00	95.33	0.01			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1613343246
95.89	0.01	94.71	0.00	93.64	0.00	95.33	0.01			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3638622121
95.89	0.01	94.71	0.00	93.64	0.00	95.33	0.01			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2711790698
95.89	0.01	94.71	0.00	93.64	0.00	95.33	0.01			94.46	0.00	97.55	0.00	99.62	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2549965888

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.4124813484
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.2830775403
/workspace/coverage/cover_reg_top/0.chip_csr_rw.713196181
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.128465544
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3201954462
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.521360066
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.587675241
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.1510107414
/workspace/coverage/cover_reg_top/0.xbar_error_random.704267830
/workspace/coverage/cover_reg_top/0.xbar_random.2536022055
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3004069197
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.2309051870
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.3085937282
/workspace/coverage/cover_reg_top/0.xbar_same_source.4072877723
/workspace/coverage/cover_reg_top/0.xbar_smoke.1754710732
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.67800453
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2721131190
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.715719319
/workspace/coverage/cover_reg_top/0.xbar_stress_all.2390547906
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2957678301
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.829447281
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3931927019
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1484553774
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3093372251
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.284276308
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3601984450
/workspace/coverage/cover_reg_top/1.chip_csr_rw.819217531
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2738148596
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3118753410
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1844643753
/workspace/coverage/cover_reg_top/1.chip_tl_errors.3841040866
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.607162028
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1005790791
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1248761825
/workspace/coverage/cover_reg_top/1.xbar_error_random.1818005347
/workspace/coverage/cover_reg_top/1.xbar_random.3238559382
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.3843145348
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1056182774
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1314190435
/workspace/coverage/cover_reg_top/1.xbar_same_source.1285925900
/workspace/coverage/cover_reg_top/1.xbar_smoke.4100239413
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3734528341
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3494652787
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.835082404
/workspace/coverage/cover_reg_top/1.xbar_stress_all.3195403330
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.2926127174
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2235134273
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.942435454
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1431440258
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.1616730118
/workspace/coverage/cover_reg_top/10.chip_csr_rw.3839554980
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.3150217352
/workspace/coverage/cover_reg_top/10.chip_tl_errors.2260096886
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1388805761
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3796687035
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3016081083
/workspace/coverage/cover_reg_top/10.xbar_error_random.2525964834
/workspace/coverage/cover_reg_top/10.xbar_random.2185713929
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.935080802
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1761063559
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.4215488737
/workspace/coverage/cover_reg_top/10.xbar_same_source.2185754268
/workspace/coverage/cover_reg_top/10.xbar_smoke.4120181499
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3218519922
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.190580620
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2935998016
/workspace/coverage/cover_reg_top/10.xbar_stress_all.1671359068
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2423648854
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2848141253
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1581832565
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.2200323834
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.2809553325
/workspace/coverage/cover_reg_top/11.chip_csr_rw.3428820316
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3076285073
/workspace/coverage/cover_reg_top/11.chip_tl_errors.3411118170
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.216674643
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.984717488
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3296645630
/workspace/coverage/cover_reg_top/11.xbar_error_random.1828064359
/workspace/coverage/cover_reg_top/11.xbar_random.1714199184
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.657410833
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.1258983763
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1941811353
/workspace/coverage/cover_reg_top/11.xbar_same_source.767866266
/workspace/coverage/cover_reg_top/11.xbar_smoke.67093529
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/workspace/coverage/default/2.rom_e2e_asm_init_dev.1124534710
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/workspace/coverage/default/2.rom_e2e_asm_init_rma.246688922
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2253804240
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.265263205
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2875649705
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/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1820916726
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.910185655
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/workspace/coverage/default/3.chip_sw_all_escalation_resets.2980033872
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.4292649812
/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2609027369
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.1624761997
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.561813877
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.904414087
/workspace/coverage/default/3.chip_sw_uart_tx_rx.3406721392
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2168797111
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1413999509
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3183090070
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2773264405
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2275165686
/workspace/coverage/default/3.chip_tap_straps_dev.971017258
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/workspace/coverage/default/3.chip_tap_straps_rma.2215013537
/workspace/coverage/default/3.chip_tap_straps_testunlock0.2987392488
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.689072699
/workspace/coverage/default/31.chip_sw_all_escalation_resets.700955362
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2552757204
/workspace/coverage/default/36.chip_sw_all_escalation_resets.3451392237
/workspace/coverage/default/39.chip_sw_all_escalation_resets.500758685
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3118424610
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.841109206
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3406604524
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.567771527
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.369864610
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.1399971381
/workspace/coverage/default/4.chip_sw_uart_tx_rx.3582041742
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1481085360
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3506045851
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2914221493
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1175222569
/workspace/coverage/default/4.chip_tap_straps_prod.739318142
/workspace/coverage/default/4.chip_tap_straps_rma.641112912
/workspace/coverage/default/41.chip_sw_all_escalation_resets.2314281166
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1278239843
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.4270346591
/workspace/coverage/default/44.chip_sw_all_escalation_resets.1617481600
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3100903882
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1465537098
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3330154114
/workspace/coverage/default/47.chip_sw_all_escalation_resets.670845062
/workspace/coverage/default/48.chip_sw_all_escalation_resets.3706984
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1646786499
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1617094326
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.989675362
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.532423130
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.419614961
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2162296736
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3934171258
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.205060848
/workspace/coverage/default/53.chip_sw_all_escalation_resets.95930849
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.20487666
/workspace/coverage/default/54.chip_sw_all_escalation_resets.3730647473
/workspace/coverage/default/55.chip_sw_all_escalation_resets.2058310964
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3262124903
/workspace/coverage/default/56.chip_sw_all_escalation_resets.2833773167
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3219595184
/workspace/coverage/default/58.chip_sw_all_escalation_resets.682488606
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2888461957
/workspace/coverage/default/59.chip_sw_all_escalation_resets.2952535957
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.925494377
/workspace/coverage/default/6.chip_sw_all_escalation_resets.1039852739
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.3478624094
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2407176259
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1017279602
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2335949693
/workspace/coverage/default/60.chip_sw_all_escalation_resets.477038157
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.1237822682
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2602650636
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.456812433
/workspace/coverage/default/62.chip_sw_all_escalation_resets.658428815
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.77258045
/workspace/coverage/default/63.chip_sw_all_escalation_resets.4217673379
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1945424911
/workspace/coverage/default/65.chip_sw_all_escalation_resets.418241738
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.688320663
/workspace/coverage/default/66.chip_sw_all_escalation_resets.2440938484
/workspace/coverage/default/67.chip_sw_all_escalation_resets.578943835
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1932097806
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.55084293
/workspace/coverage/default/69.chip_sw_all_escalation_resets.2619037522
/workspace/coverage/default/7.chip_sw_all_escalation_resets.3924264298
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2358101505
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3253405760
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1357139924
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.491207526
/workspace/coverage/default/70.chip_sw_all_escalation_resets.2720047380
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2340126096
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3804141541
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.374483020
/workspace/coverage/default/72.chip_sw_all_escalation_resets.223593649
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1003931521
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2570332714
/workspace/coverage/default/74.chip_sw_all_escalation_resets.36015680
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3387707363
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1669403956
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3312410569
/workspace/coverage/default/76.chip_sw_all_escalation_resets.28970148
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1495524613
/workspace/coverage/default/77.chip_sw_all_escalation_resets.1184473751
/workspace/coverage/default/78.chip_sw_all_escalation_resets.351033381
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.4089873445
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.1991131248
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.611251736
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3163658650
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1020852669
/workspace/coverage/default/80.chip_sw_all_escalation_resets.2175840214
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.807516203
/workspace/coverage/default/81.chip_sw_all_escalation_resets.3554726804
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.491283492
/workspace/coverage/default/82.chip_sw_all_escalation_resets.1953789402
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3799734877
/workspace/coverage/default/83.chip_sw_all_escalation_resets.3681228252
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1626126352
/workspace/coverage/default/84.chip_sw_all_escalation_resets.135454308
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2543948679
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1890791447
/workspace/coverage/default/86.chip_sw_all_escalation_resets.69218733
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2178191066
/workspace/coverage/default/88.chip_sw_all_escalation_resets.1868656175
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3605555685
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1915553051
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2998800227
/workspace/coverage/default/9.chip_sw_all_escalation_resets.1458118802
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.185606632
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.180201810
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3321426245
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2530289684
/workspace/coverage/default/92.chip_sw_all_escalation_resets.3095123624
/workspace/coverage/default/93.chip_sw_all_escalation_resets.2201874860
/workspace/coverage/default/94.chip_sw_all_escalation_resets.369025123
/workspace/coverage/default/95.chip_sw_all_escalation_resets.3583742286
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1885241586
/workspace/coverage/default/97.chip_sw_all_escalation_resets.955988448
/workspace/coverage/default/98.chip_sw_all_escalation_resets.3096595673
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3646443505
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2481726563
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1107348666
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1322016073
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2040208344
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.836086851
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2393179602

---

Total test records in report: 2932

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T4	/workspace/coverage/default/0.chip_sw_edn_sw_mode.269094851			Jul 18 08:18:01 PM PDT 24	Jul 18 09:06:14 PM PDT 24	10699630028 ps
T5	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3969306536			Jul 18 08:14:28 PM PDT 24	Jul 18 08:24:54 PM PDT 24	4797012936 ps
T6	/workspace/coverage/default/2.chip_plic_all_irqs_20.1406376630			Jul 18 08:35:39 PM PDT 24	Jul 18 08:49:44 PM PDT 24	4347581000 ps
T96	/workspace/coverage/default/0.chip_sw_aes_smoketest.265206113			Jul 18 08:19:22 PM PDT 24	Jul 18 08:24:30 PM PDT 24	2609682750 ps
T16	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2588624600			Jul 18 08:21:24 PM PDT 24	Jul 18 09:15:47 PM PDT 24	13769883285 ps
T15	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2202568842			Jul 18 08:14:05 PM PDT 24	Jul 18 08:30:13 PM PDT 24	5477162358 ps
T64	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.3925861381			Jul 18 08:28:07 PM PDT 24	Jul 18 08:35:43 PM PDT 24	5946580900 ps
T97	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3039074497			Jul 18 08:41:50 PM PDT 24	Jul 18 08:53:00 PM PDT 24	4258824864 ps
T41	/workspace/coverage/default/91.chip_sw_all_escalation_resets.973981412			Jul 18 08:51:04 PM PDT 24	Jul 18 09:00:09 PM PDT 24	5779449690 ps
T65	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2873932732			Jul 18 08:48:27 PM PDT 24	Jul 18 08:54:58 PM PDT 24	3334323096 ps
T201	/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.306686087			Jul 18 08:18:55 PM PDT 24	Jul 18 08:22:23 PM PDT 24	2509568096 ps
T43	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1991309754			Jul 18 08:13:44 PM PDT 24	Jul 18 08:18:55 PM PDT 24	3294739296 ps
T258	/workspace/coverage/default/2.chip_sw_plic_sw_irq.31112137			Jul 18 08:36:44 PM PDT 24	Jul 18 08:43:08 PM PDT 24	3473188432 ps
T260	/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.2572733821			Jul 18 08:40:31 PM PDT 24	Jul 18 08:45:31 PM PDT 24	2957303362 ps
T57	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1475736909			Jul 18 08:28:29 PM PDT 24	Jul 18 08:38:01 PM PDT 24	4864497716 ps
T42	/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3540432580			Jul 18 08:28:30 PM PDT 24	Jul 18 08:39:24 PM PDT 24	4730719534 ps
T454	/workspace/coverage/default/1.chip_sw_kmac_smoketest.2627323895			Jul 18 08:28:40 PM PDT 24	Jul 18 08:34:55 PM PDT 24	2699768400 ps
T58	/workspace/coverage/default/3.chip_tap_straps_prod.3784421508			Jul 18 08:41:32 PM PDT 24	Jul 18 08:44:03 PM PDT 24	2235472045 ps
T262	/workspace/coverage/default/2.chip_plic_all_irqs_0.1811843985			Jul 18 08:37:14 PM PDT 24	Jul 18 08:57:35 PM PDT 24	6308914700 ps
T225	/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3062014347			Jul 18 08:43:07 PM PDT 24	Jul 18 09:22:34 PM PDT 24	12620734176 ps
T160	/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1127417814			Jul 18 08:13:19 PM PDT 24	Jul 18 09:43:14 PM PDT 24	27912313802 ps
T339	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.239215091			Jul 18 08:53:12 PM PDT 24	Jul 18 08:59:21 PM PDT 24	3073919608 ps
T53	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.935857902			Jul 18 08:22:33 PM PDT 24	Jul 18 09:24:51 PM PDT 24	14694482904 ps
T17	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.647506405			Jul 18 08:24:26 PM PDT 24	Jul 18 10:02:39 PM PDT 24	23064277750 ps
T68	/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1072230007			Jul 18 08:32:41 PM PDT 24	Jul 18 09:01:28 PM PDT 24	10139858387 ps
T59	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1074708457			Jul 18 08:13:34 PM PDT 24	Jul 18 08:15:36 PM PDT 24	2416921786 ps
T263	/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1975676569			Jul 18 08:20:34 PM PDT 24	Jul 18 08:26:01 PM PDT 24	3744616562 ps
T132	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1702981799			Jul 18 08:26:32 PM PDT 24	Jul 18 09:08:27 PM PDT 24	12218082512 ps
T189	/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.477775403			Jul 18 08:31:59 PM PDT 24	Jul 18 08:38:17 PM PDT 24	4139922910 ps
T18	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.261633743			Jul 18 08:30:07 PM PDT 24	Jul 18 08:38:17 PM PDT 24	3928894678 ps
T221	/workspace/coverage/default/1.chip_sw_pattgen_ios.42216841			Jul 18 08:17:06 PM PDT 24	Jul 18 08:21:13 PM PDT 24	2538187430 ps
T156	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2410371921			Jul 18 08:43:05 PM PDT 24	Jul 18 09:06:05 PM PDT 24	8272601100 ps
T200	/workspace/coverage/default/5.chip_sw_all_escalation_resets.135611050			Jul 18 08:41:51 PM PDT 24	Jul 18 08:53:25 PM PDT 24	5017623160 ps
T54	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.2466390824			Jul 18 08:41:39 PM PDT 24	Jul 18 08:50:21 PM PDT 24	4553332696 ps
T116	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1071638698			Jul 18 08:24:22 PM PDT 24	Jul 18 08:32:52 PM PDT 24	19059713998 ps
T302	/workspace/coverage/default/0.chip_sw_csrng_kat_test.2798679266			Jul 18 08:15:11 PM PDT 24	Jul 18 08:20:37 PM PDT 24	2971090088 ps
T228	/workspace/coverage/default/76.chip_sw_all_escalation_resets.28970148			Jul 18 08:51:17 PM PDT 24	Jul 18 09:00:40 PM PDT 24	5267410200 ps
T124	/workspace/coverage/default/1.chip_sw_clkmgr_jitter.3153136401			Jul 18 08:26:36 PM PDT 24	Jul 18 08:31:12 PM PDT 24	2826819032 ps
T72	/workspace/coverage/default/3.chip_tap_straps_dev.971017258			Jul 18 08:40:05 PM PDT 24	Jul 18 08:46:03 PM PDT 24	4028707607 ps
T303	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.1571716979			Jul 18 08:33:47 PM PDT 24	Jul 18 09:29:04 PM PDT 24	14766328290 ps
T304	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2888461957			Jul 18 08:50:01 PM PDT 24	Jul 18 08:55:59 PM PDT 24	4061248040 ps
T122	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.371867909			Jul 18 08:36:19 PM PDT 24	Jul 18 08:55:53 PM PDT 24	7190099226 ps
T229	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.747948670			Jul 18 08:36:55 PM PDT 24	Jul 18 08:56:22 PM PDT 24	7630098104 ps
T230	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3168978075			Jul 18 08:25:38 PM PDT 24	Jul 18 09:26:10 PM PDT 24	14666313816 ps
T25	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2290908175			Jul 18 08:30:20 PM PDT 24	Jul 18 08:42:09 PM PDT 24	5019963296 ps
T953	/workspace/coverage/default/1.chip_sw_example_flash.2308293714			Jul 18 08:16:18 PM PDT 24	Jul 18 08:18:40 PM PDT 24	2946898664 ps
T450	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.4280086475			Jul 18 08:30:03 PM PDT 24	Jul 18 08:34:46 PM PDT 24	2179978440 ps
T28	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.241968669			Jul 18 08:20:44 PM PDT 24	Jul 18 09:14:12 PM PDT 24	20621255330 ps
T89	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3404080241			Jul 18 08:35:08 PM PDT 24	Jul 18 08:54:43 PM PDT 24	10314863384 ps
T126	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1413999509			Jul 18 08:42:21 PM PDT 24	Jul 18 08:52:43 PM PDT 24	5113447625 ps
T169	/workspace/coverage/default/4.chip_tap_straps_prod.739318142			Jul 18 08:40:59 PM PDT 24	Jul 18 08:43:52 PM PDT 24	2606933191 ps
T1	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.3348949104			Jul 18 08:26:57 PM PDT 24	Jul 18 08:32:19 PM PDT 24	3632969440 ps
T108	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2444861995			Jul 18 08:15:42 PM PDT 24	Jul 18 08:27:05 PM PDT 24	4593684024 ps
T109	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1043560979			Jul 18 08:50:10 PM PDT 24	Jul 18 08:56:48 PM PDT 24	4635155744 ps
T110	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.688320663			Jul 18 08:50:47 PM PDT 24	Jul 18 08:56:16 PM PDT 24	3303338382 ps
T111	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.804711899			Jul 18 08:20:51 PM PDT 24	Jul 18 08:28:03 PM PDT 24	5940516992 ps
T112	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3345220149			Jul 18 08:30:53 PM PDT 24	Jul 18 08:38:37 PM PDT 24	3227301416 ps
T55	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.263896491			Jul 18 08:21:53 PM PDT 24	Jul 18 09:55:01 PM PDT 24	49904381708 ps
T113	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3250766099			Jul 18 08:28:17 PM PDT 24	Jul 18 08:39:53 PM PDT 24	4891223406 ps
T114	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.169901831			Jul 18 08:36:21 PM PDT 24	Jul 18 08:40:40 PM PDT 24	2623967763 ps
T115	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.3320838519			Jul 18 08:23:28 PM PDT 24	Jul 18 10:07:34 PM PDT 24	25447477140 ps
T280	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3459674464			Jul 18 08:25:30 PM PDT 24	Jul 18 08:33:32 PM PDT 24	9453102542 ps
T158	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1457628165			Jul 18 08:34:33 PM PDT 24	Jul 18 09:28:30 PM PDT 24	17092007240 ps
T359	/workspace/coverage/default/0.chip_sw_flash_crash_alert.3102725374			Jul 18 08:14:51 PM PDT 24	Jul 18 08:24:29 PM PDT 24	5357857848 ps
T90	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.2225503711			Jul 18 08:47:42 PM PDT 24	Jul 18 08:54:49 PM PDT 24	4378683608 ps
T56	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1496569966			Jul 18 08:13:47 PM PDT 24	Jul 18 09:52:49 PM PDT 24	50194990223 ps
T101	/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1936450407			Jul 18 08:34:31 PM PDT 24	Jul 18 08:50:37 PM PDT 24	4869577196 ps
T91	/workspace/coverage/default/64.chip_sw_all_escalation_resets.2563992010			Jul 18 08:48:13 PM PDT 24	Jul 18 09:01:29 PM PDT 24	5136028948 ps
T102	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.989675362			Jul 18 08:41:26 PM PDT 24	Jul 18 08:52:19 PM PDT 24	5941018880 ps
T103	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1351081543			Jul 18 08:27:06 PM PDT 24	Jul 18 09:00:58 PM PDT 24	29411961480 ps
T104	/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2967900848			Jul 18 08:29:37 PM PDT 24	Jul 18 08:33:46 PM PDT 24	3549548748 ps
T105	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1254951464			Jul 18 08:23:52 PM PDT 24	Jul 18 08:29:03 PM PDT 24	3122621251 ps
T52	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2071006619			Jul 18 08:23:15 PM PDT 24	Jul 18 09:44:41 PM PDT 24	14635148392 ps
T106	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1172581590			Jul 18 08:31:35 PM PDT 24	Jul 18 08:36:57 PM PDT 24	3275163336 ps
T2	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.625138683			Jul 18 08:15:10 PM PDT 24	Jul 18 08:21:15 PM PDT 24	3232090002 ps
T297	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2912196270			Jul 18 08:29:42 PM PDT 24	Jul 18 08:46:53 PM PDT 24	7417820128 ps
T123	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2515324473			Jul 18 08:33:29 PM PDT 24	Jul 18 09:27:43 PM PDT 24	18117578826 ps
T298	/workspace/coverage/default/14.chip_sw_all_escalation_resets.4157038919			Jul 18 08:45:42 PM PDT 24	Jul 18 08:53:32 PM PDT 24	5225643328 ps
T49	/workspace/coverage/default/2.chip_sw_spi_device_tpm.1563224406			Jul 18 08:31:20 PM PDT 24	Jul 18 08:37:24 PM PDT 24	3512715266 ps
T73	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.4287637859			Jul 18 08:16:49 PM PDT 24	Jul 18 08:27:09 PM PDT 24	5672497112 ps
T954	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3198875614			Jul 18 08:26:33 PM PDT 24	Jul 18 08:34:28 PM PDT 24	4257045528 ps
T955	/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1372135960			Jul 18 08:39:09 PM PDT 24	Jul 18 08:42:42 PM PDT 24	3359809576 ps
T340	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.782778094			Jul 18 08:26:41 PM PDT 24	Jul 18 08:30:45 PM PDT 24	3452555022 ps
T250	/workspace/coverage/default/46.chip_sw_all_escalation_resets.3447115389			Jul 18 08:47:16 PM PDT 24	Jul 18 08:56:44 PM PDT 24	5501662056 ps
T272	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1626126352			Jul 18 08:50:59 PM PDT 24	Jul 18 08:56:52 PM PDT 24	4209796330 ps
T273	/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2385607107			Jul 18 08:12:05 PM PDT 24	Jul 18 08:24:05 PM PDT 24	4857446986 ps
T129	/workspace/coverage/default/0.chip_sw_edn_boot_mode.248843882			Jul 18 08:14:44 PM PDT 24	Jul 18 08:25:15 PM PDT 24	3531178840 ps
T67	/workspace/coverage/default/2.rom_volatile_raw_unlock.1038291323			Jul 18 08:39:01 PM PDT 24	Jul 18 08:41:05 PM PDT 24	3091119375 ps
T274	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1020852669			Jul 18 08:49:23 PM PDT 24	Jul 18 08:55:59 PM PDT 24	3638986536 ps
T275	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2468407975			Jul 18 08:22:57 PM PDT 24	Jul 18 08:28:54 PM PDT 24	3652357896 ps
T276	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.1006440278			Jul 18 08:28:50 PM PDT 24	Jul 18 08:39:50 PM PDT 24	5490076488 ps
T277	/workspace/coverage/default/0.chip_sw_example_concurrency.98329703			Jul 18 08:14:10 PM PDT 24	Jul 18 08:17:02 PM PDT 24	2807292872 ps
T26	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1102122599			Jul 18 08:43:58 PM PDT 24	Jul 18 09:04:38 PM PDT 24	8155202402 ps
T956	/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.4187404441			Jul 18 08:19:07 PM PDT 24	Jul 18 08:24:53 PM PDT 24	2969030356 ps
T410	/workspace/coverage/default/1.rom_e2e_smoke.2067982743			Jul 18 08:34:08 PM PDT 24	Jul 18 09:42:13 PM PDT 24	14949023888 ps
T351	/workspace/coverage/default/0.chip_sival_flash_info_access.2134983919			Jul 18 08:14:18 PM PDT 24	Jul 18 08:19:07 PM PDT 24	3480533772 ps
T232	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.1360585756			Jul 18 08:31:50 PM PDT 24	Jul 18 08:54:28 PM PDT 24	8808126616 ps
T957	/workspace/coverage/default/2.chip_sw_aes_smoketest.1442149911			Jul 18 08:40:24 PM PDT 24	Jul 18 08:44:35 PM PDT 24	3097763170 ps
T402	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1465537098			Jul 18 08:48:01 PM PDT 24	Jul 18 08:54:36 PM PDT 24	3903354130 ps
T346	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2436023839			Jul 18 08:15:22 PM PDT 24	Jul 18 08:21:47 PM PDT 24	4096718900 ps
T278	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1220607580			Jul 18 08:23:41 PM PDT 24	Jul 18 09:25:53 PM PDT 24	14269790990 ps
T364	/workspace/coverage/default/16.chip_sw_all_escalation_resets.1414288342			Jul 18 08:45:04 PM PDT 24	Jul 18 08:56:34 PM PDT 24	4651767772 ps
T958	/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1675389950			Jul 18 08:25:44 PM PDT 24	Jul 18 08:32:42 PM PDT 24	3056290100 ps
T29	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3019222886			Jul 18 08:14:31 PM PDT 24	Jul 18 09:23:01 PM PDT 24	20518664356 ps
T66	/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.567771527			Jul 18 08:40:37 PM PDT 24	Jul 18 08:50:15 PM PDT 24	6870906078 ps
T95	/workspace/coverage/default/1.chip_sw_inject_scramble_seed.563839502			Jul 18 08:21:03 PM PDT 24	Jul 18 11:48:11 PM PDT 24	65603562275 ps
T349	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2018134335			Jul 18 08:13:22 PM PDT 24	Jul 18 08:25:34 PM PDT 24	3763662245 ps
T362	/workspace/coverage/default/21.chip_sw_all_escalation_resets.723481898			Jul 18 08:52:19 PM PDT 24	Jul 18 09:04:51 PM PDT 24	5574612880 ps
T210	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.413713299			Jul 18 08:19:31 PM PDT 24	Jul 18 08:29:16 PM PDT 24	4766256888 ps
T117	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3505156015			Jul 18 08:34:27 PM PDT 24	Jul 18 08:45:39 PM PDT 24	18487702166 ps
T92	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1251651102			Jul 18 08:22:22 PM PDT 24	Jul 18 08:40:35 PM PDT 24	9389419048 ps
T959	/workspace/coverage/default/2.chip_sw_csrng_kat_test.266833072			Jul 18 08:35:09 PM PDT 24	Jul 18 08:40:12 PM PDT 24	3285968090 ps
T363	/workspace/coverage/default/95.chip_sw_all_escalation_resets.3583742286			Jul 18 08:49:31 PM PDT 24	Jul 18 08:57:41 PM PDT 24	5626099112 ps
T458	/workspace/coverage/default/2.chip_sw_otbn_randomness.3501159127			Jul 18 08:41:15 PM PDT 24	Jul 18 08:54:54 PM PDT 24	6124726580 ps
T383	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2991218418			Jul 18 08:22:20 PM PDT 24	Jul 18 09:28:04 PM PDT 24	15008886338 ps
T159	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.68496242			Jul 18 08:21:00 PM PDT 24	Jul 18 09:21:02 PM PDT 24	16489964452 ps
T8	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1737667529			Jul 18 08:28:47 PM PDT 24	Jul 18 08:34:08 PM PDT 24	4121471560 ps
T130	/workspace/coverage/default/1.chip_sw_edn_boot_mode.2982448862			Jul 18 08:21:45 PM PDT 24	Jul 18 08:33:35 PM PDT 24	3560141640 ps
T177	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2195737378			Jul 18 08:25:31 PM PDT 24	Jul 18 08:33:14 PM PDT 24	3681038032 ps
T74	/workspace/coverage/default/3.chip_tap_straps_testunlock0.2987392488			Jul 18 08:41:30 PM PDT 24	Jul 18 08:51:45 PM PDT 24	5637476464 ps
T251	/workspace/coverage/default/68.chip_sw_all_escalation_resets.932756890			Jul 18 08:49:27 PM PDT 24	Jul 18 09:00:03 PM PDT 24	5166418488 ps
T444	/workspace/coverage/default/38.chip_sw_all_escalation_resets.1122162441			Jul 18 08:46:13 PM PDT 24	Jul 18 08:58:02 PM PDT 24	5499670240 ps
T445	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2317046636			Jul 18 08:18:22 PM PDT 24	Jul 18 08:38:15 PM PDT 24	6826404796 ps
T231	/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1523619442			Jul 18 08:26:25 PM PDT 24	Jul 18 08:56:09 PM PDT 24	7895171696 ps
T446	/workspace/coverage/default/1.chip_sw_flash_crash_alert.1191626898			Jul 18 08:27:46 PM PDT 24	Jul 18 08:41:02 PM PDT 24	5895262304 ps
T447	/workspace/coverage/default/2.chip_sw_example_concurrency.1960493980			Jul 18 08:31:32 PM PDT 24	Jul 18 08:36:54 PM PDT 24	3403362480 ps
T199	/workspace/coverage/default/1.chip_tap_straps_dev.1631564151			Jul 18 08:26:15 PM PDT 24	Jul 18 08:29:42 PM PDT 24	2629183396 ps
T960	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.4108702104			Jul 18 08:15:09 PM PDT 24	Jul 18 08:25:04 PM PDT 24	4991285794 ps
T127	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3012285568			Jul 18 08:16:17 PM PDT 24	Jul 18 08:27:28 PM PDT 24	3918997914 ps
T168	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.471646715			Jul 18 08:30:48 PM PDT 24	Jul 18 09:57:55 PM PDT 24	48401005348 ps
T344	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3594436224			Jul 18 08:16:21 PM PDT 24	Jul 18 08:26:23 PM PDT 24	4773779712 ps
T555	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.463271068			Jul 18 08:38:38 PM PDT 24	Jul 18 08:47:51 PM PDT 24	7239784544 ps
T136	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1614284377			Jul 18 08:16:49 PM PDT 24	Jul 18 08:24:17 PM PDT 24	5233449388 ps
T771	/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2921360674			Jul 18 08:32:53 PM PDT 24	Jul 18 08:49:46 PM PDT 24	6080456760 ps
T961	/workspace/coverage/default/2.chip_sival_flash_info_access.2614164579			Jul 18 08:33:23 PM PDT 24	Jul 18 08:38:52 PM PDT 24	3129441382 ps
T318	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2340126096			Jul 18 08:49:52 PM PDT 24	Jul 18 08:55:28 PM PDT 24	3968625136 ps
T322	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.3052815993			Jul 18 08:18:06 PM PDT 24	Jul 18 08:36:34 PM PDT 24	5962962200 ps
T323	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2101994757			Jul 18 08:13:49 PM PDT 24	Jul 18 08:32:23 PM PDT 24	7756738750 ps
T324	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.456812433			Jul 18 08:48:29 PM PDT 24	Jul 18 08:56:00 PM PDT 24	3663565794 ps
T325	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1479226803			Jul 18 08:26:48 PM PDT 24	Jul 18 08:31:28 PM PDT 24	2414437566 ps
T164	/workspace/coverage/default/9.chip_sw_all_escalation_resets.1458118802			Jul 18 08:42:52 PM PDT 24	Jul 18 08:56:48 PM PDT 24	6758112328 ps
T326	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.476469590			Jul 18 08:40:09 PM PDT 24	Jul 18 08:44:41 PM PDT 24	3208679106 ps
T75	/workspace/coverage/default/3.chip_tap_straps_rma.2215013537			Jul 18 08:41:22 PM PDT 24	Jul 18 08:47:05 PM PDT 24	3867157069 ps
T192	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.611251736			Jul 18 08:43:01 PM PDT 24	Jul 18 08:55:09 PM PDT 24	5345066684 ps
T327	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1321423402			Jul 18 08:33:21 PM PDT 24	Jul 18 08:42:25 PM PDT 24	4746989782 ps
T962	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.4201910867			Jul 18 08:19:23 PM PDT 24	Jul 18 08:37:52 PM PDT 24	7591795992 ps
T772	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.649240765			Jul 18 08:31:22 PM PDT 24	Jul 18 08:43:51 PM PDT 24	7419650200 ps
T249	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.360628240			Jul 18 08:14:35 PM PDT 24	Jul 18 08:42:19 PM PDT 24	9435125724 ps
T963	/workspace/coverage/default/0.chip_sw_example_flash.544964609			Jul 18 08:12:58 PM PDT 24	Jul 18 08:16:01 PM PDT 24	2513878860 ps
T964	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3346488267			Jul 18 08:25:46 PM PDT 24	Jul 18 08:41:18 PM PDT 24	8422539100 ps
T137	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1712856213			Jul 18 08:38:00 PM PDT 24	Jul 18 08:53:45 PM PDT 24	7582436804 ps
T128	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2676249271			Jul 18 08:38:14 PM PDT 24	Jul 18 08:48:49 PM PDT 24	4499842000 ps
T118	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.155206678			Jul 18 08:14:13 PM PDT 24	Jul 18 08:22:47 PM PDT 24	19398262968 ps
T3	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3354166512			Jul 18 08:15:54 PM PDT 24	Jul 18 08:37:07 PM PDT 24	24569302280 ps
T119	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3338169613			Jul 18 08:29:16 PM PDT 24	Jul 18 09:43:19 PM PDT 24	27817446143 ps
T426	/workspace/coverage/default/13.chip_sw_all_escalation_resets.508818152			Jul 18 08:45:27 PM PDT 24	Jul 18 08:53:14 PM PDT 24	5657277276 ps
T427	/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1585307225			Jul 18 08:15:39 PM PDT 24	Jul 18 08:32:56 PM PDT 24	5950714924 ps
T428	/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3637750437			Jul 18 08:38:48 PM PDT 24	Jul 18 08:48:04 PM PDT 24	4720373736 ps
T384	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.833603661			Jul 18 08:23:26 PM PDT 24	Jul 18 09:23:40 PM PDT 24	15520505446 ps
T252	/workspace/coverage/default/40.chip_sw_all_escalation_resets.1310325285			Jul 18 08:48:01 PM PDT 24	Jul 18 08:55:15 PM PDT 24	5192014368 ps
T429	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2570332714			Jul 18 08:49:07 PM PDT 24	Jul 18 08:55:46 PM PDT 24	4382647952 ps
T430	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.424989898			Jul 18 08:46:31 PM PDT 24	Jul 18 08:54:15 PM PDT 24	4271775496 ps
T431	/workspace/coverage/default/53.chip_sw_all_escalation_resets.95930849			Jul 18 08:48:54 PM PDT 24	Jul 18 08:59:27 PM PDT 24	4654444800 ps
T965	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.455199919			Jul 18 08:26:05 PM PDT 24	Jul 18 08:31:01 PM PDT 24	2505207089 ps
T554	/workspace/coverage/default/4.chip_sw_all_escalation_resets.3359661657			Jul 18 08:40:43 PM PDT 24	Jul 18 08:50:58 PM PDT 24	4137038520 ps
T165	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1797012573			Jul 18 08:19:53 PM PDT 24	Jul 18 08:23:19 PM PDT 24	2368873866 ps
T176	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2295484164			Jul 18 08:20:30 PM PDT 24	Jul 18 08:37:17 PM PDT 24	11018497431 ps
T220	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.723908717			Jul 18 08:19:19 PM PDT 24	Jul 18 08:29:16 PM PDT 24	3837609632 ps
T779	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.138020250			Jul 18 08:47:30 PM PDT 24	Jul 18 08:56:10 PM PDT 24	3864623640 ps
T766	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2335949693			Jul 18 08:49:00 PM PDT 24	Jul 18 08:55:03 PM PDT 24	3713343400 ps
T211	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.415702987			Jul 18 08:33:11 PM PDT 24	Jul 18 08:44:12 PM PDT 24	4711498925 ps
T224	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.678235421			Jul 18 08:31:56 PM PDT 24	Jul 18 08:46:52 PM PDT 24	4960342200 ps
T455	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.146978911			Jul 18 08:18:46 PM PDT 24	Jul 18 08:44:15 PM PDT 24	6281105772 ps
T966	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4104616934			Jul 18 08:19:55 PM PDT 24	Jul 18 09:09:51 PM PDT 24	35740512896 ps
T967	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1911364982			Jul 18 08:34:16 PM PDT 24	Jul 18 08:39:06 PM PDT 24	2668205240 ps
T968	/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3178002859			Jul 18 08:28:23 PM PDT 24	Jul 18 08:48:00 PM PDT 24	6033068926 ps
T226	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1357139924			Jul 18 08:41:41 PM PDT 24	Jul 18 09:20:17 PM PDT 24	13059321272 ps
T763	/workspace/coverage/default/17.chip_sw_all_escalation_resets.1252837640			Jul 18 08:44:55 PM PDT 24	Jul 18 08:55:38 PM PDT 24	5079963890 ps
T212	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.4168793678			Jul 18 08:16:39 PM PDT 24	Jul 18 08:27:08 PM PDT 24	4465151056 ps
T795	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3967550816			Jul 18 08:53:27 PM PDT 24	Jul 18 09:01:02 PM PDT 24	3688720230 ps
T969	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2754240204			Jul 18 08:44:36 PM PDT 24	Jul 18 09:38:04 PM PDT 24	14970464006 ps
T970	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.4167006027			Jul 18 08:32:53 PM PDT 24	Jul 18 09:29:09 PM PDT 24	14872841216 ps
T33	/workspace/coverage/default/0.chip_sw_gpio.3559316014			Jul 18 08:11:53 PM PDT 24	Jul 18 08:21:10 PM PDT 24	3728343548 ps
T971	/workspace/coverage/default/2.rom_e2e_smoke.1260608332			Jul 18 08:44:33 PM PDT 24	Jul 18 09:40:27 PM PDT 24	14809553972 ps
T222	/workspace/coverage/default/0.chip_sw_pattgen_ios.3814092238			Jul 18 08:12:38 PM PDT 24	Jul 18 08:16:45 PM PDT 24	2991886008 ps
T972	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1077544582			Jul 18 08:18:39 PM PDT 24	Jul 18 08:37:14 PM PDT 24	5848479332 ps
T973	/workspace/coverage/default/0.chip_sw_otbn_smoketest.2567966253			Jul 18 08:19:47 PM PDT 24	Jul 18 08:35:41 PM PDT 24	6104288960 ps
T7	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1910837024			Jul 18 08:27:42 PM PDT 24	Jul 18 08:55:04 PM PDT 24	21156101518 ps
T974	/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.11425425			Jul 18 08:45:14 PM PDT 24	Jul 18 08:52:37 PM PDT 24	7657439236 ps
T93	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1434483576			Jul 18 08:22:27 PM PDT 24	Jul 18 08:29:25 PM PDT 24	4088894072 ps
T975	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.114896835			Jul 18 08:28:42 PM PDT 24	Jul 18 09:35:08 PM PDT 24	15360707116 ps
T94	/workspace/coverage/default/2.chip_sw_alert_handler_entropy.2119519439			Jul 18 08:36:49 PM PDT 24	Jul 18 08:42:33 PM PDT 24	3153981673 ps
T796	/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3312410569			Jul 18 08:50:55 PM PDT 24	Jul 18 08:56:49 PM PDT 24	3494328956 ps
T77	/workspace/coverage/default/2.chip_tap_straps_dev.982719485			Jul 18 08:37:57 PM PDT 24	Jul 18 08:46:08 PM PDT 24	5331057960 ps
T279	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.3237312212			Jul 18 08:19:40 PM PDT 24	Jul 18 09:18:43 PM PDT 24	15083417850 ps
T180	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.530517608			Jul 18 08:38:21 PM PDT 24	Jul 18 08:43:10 PM PDT 24	3079723292 ps
T308	/workspace/coverage/default/36.chip_sw_all_escalation_resets.3451392237			Jul 18 08:45:47 PM PDT 24	Jul 18 08:54:15 PM PDT 24	4391574634 ps
T309	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.3414313349			Jul 18 08:29:32 PM PDT 24	Jul 18 08:33:35 PM PDT 24	2680596476 ps
T149	/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.1554995140			Jul 18 08:34:53 PM PDT 24	Jul 18 08:39:08 PM PDT 24	3036783501 ps
T310	/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2438423067			Jul 18 08:18:21 PM PDT 24	Jul 18 08:22:20 PM PDT 24	3122536440 ps
T173	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.4044078626			Jul 18 08:14:28 PM PDT 24	Jul 18 08:17:28 PM PDT 24	3131218430 ps
T311	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.929105160			Jul 18 08:21:45 PM PDT 24	Jul 18 08:41:38 PM PDT 24	6175622558 ps
T312	/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2232379771			Jul 18 08:41:31 PM PDT 24	Jul 18 08:47:53 PM PDT 24	3559844668 ps
T313	/workspace/coverage/default/1.chip_sw_hmac_oneshot.2075527783			Jul 18 08:25:20 PM PDT 24	Jul 18 08:30:11 PM PDT 24	3227375930 ps
T314	/workspace/coverage/default/29.chip_sw_all_escalation_resets.2114687453			Jul 18 08:47:02 PM PDT 24	Jul 18 08:58:22 PM PDT 24	5518921072 ps
T976	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.315751355			Jul 18 08:21:26 PM PDT 24	Jul 18 09:29:40 PM PDT 24	15433027702 ps
T361	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3353735081			Jul 18 08:23:56 PM PDT 24	Jul 18 08:28:12 PM PDT 24	2879579690 ps
T394	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3206351957			Jul 18 08:20:32 PM PDT 24	Jul 18 09:35:35 PM PDT 24	18613004492 ps
T227	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.755599665			Jul 18 08:44:53 PM PDT 24	Jul 18 09:10:22 PM PDT 24	8100151450 ps
T27	/workspace/coverage/default/0.chip_sw_usbdev_stream.3736020094			Jul 18 08:12:14 PM PDT 24	Jul 18 09:24:16 PM PDT 24	18741560224 ps
T30	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.311513395			Jul 18 08:20:59 PM PDT 24	Jul 18 08:28:01 PM PDT 24	3381857160 ps
T977	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2101574751			Jul 18 08:16:17 PM PDT 24	Jul 18 09:21:38 PM PDT 24	19103968808 ps
T978	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1334877800			Jul 18 08:45:49 PM PDT 24	Jul 18 08:54:42 PM PDT 24	3945846480 ps
T783	/workspace/coverage/default/34.chip_sw_all_escalation_resets.242153288			Jul 18 08:47:33 PM PDT 24	Jul 18 08:57:10 PM PDT 24	5290066184 ps
T979	/workspace/coverage/default/3.chip_sw_uart_tx_rx.3406721392			Jul 18 08:39:57 PM PDT 24	Jul 18 08:50:03 PM PDT 24	4522571182 ps
T61	/workspace/coverage/default/2.chip_sw_alert_test.2084645345			Jul 18 08:41:43 PM PDT 24	Jul 18 08:46:51 PM PDT 24	3468287952 ps
T980	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.3691859018			Jul 18 08:18:07 PM PDT 24	Jul 18 08:21:45 PM PDT 24	3230304924 ps
T981	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.4090854736			Jul 18 08:38:01 PM PDT 24	Jul 18 08:44:32 PM PDT 24	7393269294 ps
T223	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3066291234			Jul 18 08:13:56 PM PDT 24	Jul 18 08:27:57 PM PDT 24	4890199164 ps
T174	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1841616950			Jul 18 08:16:11 PM PDT 24	Jul 18 08:18:54 PM PDT 24	3800154176 ps
T982	/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.501860272			Jul 18 08:41:10 PM PDT 24	Jul 18 08:53:21 PM PDT 24	5871212924 ps
T50	/workspace/coverage/default/1.chip_sw_spi_device_tpm.1558781401			Jul 18 08:18:23 PM PDT 24	Jul 18 08:23:10 PM PDT 24	3020444444 ps
T253	/workspace/coverage/default/2.chip_sw_all_escalation_resets.3443193506			Jul 18 08:31:27 PM PDT 24	Jul 18 08:41:53 PM PDT 24	4855806980 ps
T983	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2077613137			Jul 18 08:30:31 PM PDT 24	Jul 18 08:42:54 PM PDT 24	4842708144 ps
T19	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1017738580			Jul 18 08:13:14 PM PDT 24	Jul 18 08:18:54 PM PDT 24	3022672482 ps
T984	/workspace/coverage/default/2.chip_sw_aes_idle.2351049028			Jul 18 08:40:26 PM PDT 24	Jul 18 08:45:01 PM PDT 24	2746671242 ps
T985	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.4076489605			Jul 18 08:16:19 PM PDT 24	Jul 18 08:42:47 PM PDT 24	9688442120 ps
T175	/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3119835714			Jul 18 08:20:17 PM PDT 24	Jul 18 08:22:49 PM PDT 24	3100767788 ps
T725	/workspace/coverage/default/0.chip_sw_aes_masking_off.2172161048			Jul 18 08:14:16 PM PDT 24	Jul 18 08:19:25 PM PDT 24	3258819086 ps
T84	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1474875901			Jul 18 08:14:43 PM PDT 24	Jul 18 08:23:16 PM PDT 24	4573826260 ps
T986	/workspace/coverage/default/0.chip_sw_alert_handler_escalation.3711035667			Jul 18 08:14:06 PM PDT 24	Jul 18 08:23:50 PM PDT 24	5545448888 ps
T884	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2241236969			Jul 18 08:51:29 PM PDT 24	Jul 18 09:01:30 PM PDT 24	3721276608 ps
T98	/workspace/coverage/default/67.chip_sw_all_escalation_resets.578943835			Jul 18 08:49:10 PM PDT 24	Jul 18 08:59:03 PM PDT 24	6138172082 ps
T727	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3939522927			Jul 18 08:25:41 PM PDT 24	Jul 18 09:35:09 PM PDT 24	19114969800 ps
T987	/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.3070373236			Jul 18 08:42:58 PM PDT 24	Jul 18 08:59:33 PM PDT 24	10110607104 ps
T765	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.2270622357			Jul 18 08:18:08 PM PDT 24	Jul 18 08:29:01 PM PDT 24	7278545920 ps
T186	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1999823967			Jul 18 08:20:01 PM PDT 24	Jul 18 09:47:55 PM PDT 24	42958868266 ps
T254	/workspace/coverage/default/62.chip_sw_all_escalation_resets.658428815			Jul 18 08:47:47 PM PDT 24	Jul 18 08:57:25 PM PDT 24	4944722308 ps
T267	/workspace/coverage/default/43.chip_sw_all_escalation_resets.244999183			Jul 18 08:55:49 PM PDT 24	Jul 18 09:04:18 PM PDT 24	4676315256 ps
T785	/workspace/coverage/default/39.chip_sw_all_escalation_resets.500758685			Jul 18 08:48:13 PM PDT 24	Jul 18 08:57:38 PM PDT 24	5842579976 ps
T988	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1900879406			Jul 18 08:14:15 PM PDT 24	Jul 18 08:23:44 PM PDT 24	7367982710 ps
T236	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2150571398			Jul 18 08:37:14 PM PDT 24	Jul 18 09:03:28 PM PDT 24	8762225700 ps
T774	/workspace/coverage/default/72.chip_sw_all_escalation_resets.223593649			Jul 18 08:49:23 PM PDT 24	Jul 18 08:59:30 PM PDT 24	6104799528 ps
T342	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3315913698			Jul 18 08:14:24 PM PDT 24	Jul 18 08:24:02 PM PDT 24	3599224212 ps
T143	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2965666576			Jul 18 08:42:16 PM PDT 24	Jul 18 08:52:31 PM PDT 24	4933502742 ps
T989	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2646974091			Jul 18 08:15:53 PM PDT 24	Jul 18 08:44:24 PM PDT 24	7695218352 ps
T131	/workspace/coverage/default/1.chip_sw_edn_kat.3990521849			Jul 18 08:22:45 PM PDT 24	Jul 18 08:33:15 PM PDT 24	3122651216 ps
T990	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2875649705			Jul 18 08:42:53 PM PDT 24	Jul 18 09:35:02 PM PDT 24	14704526390 ps
T178	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.618314398			Jul 18 08:15:00 PM PDT 24	Jul 18 08:23:23 PM PDT 24	5022904636 ps
T991	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1803085479			Jul 18 08:28:31 PM PDT 24	Jul 18 08:31:46 PM PDT 24	2784038681 ps