Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	140735	1			T81	7		T82	72		T83	6
values[2]	9648	1			T81	1		T82	3		T135	1
values[3]	3455	1			T551	96		T557	2		T928	1
values[4]	1960	1			T551	61		T557	1		T440	16
values[5]	1436	1			T551	39		T557	5		T440	15
values[6]	1124	1			T551	47		T557	9		T440	9
values[7]	846	1			T551	48		T557	6		T440	13
values[8]	668	1			T551	25		T557	1		T440	4
values[9]	557	1			T551	12		T557	7		T929	13
values[10]	492	1			T551	5		T557	2		T929	11
values[11]	450	1			T557	3		T929	4		T560	1
values[12]	420	1			T557	4		T929	15		T560	1
values[13]	392	1			T557	1		T929	9		T560	1
values[14]	327	1			T557	4		T929	7		T560	1
values[15]	406	1			T557	5		T929	7		T560	1
values[16]	366	1			T557	3		T929	10		T560	1
values[17]	352	1			T557	3		T929	7		T560	1
values[18]	389	1			T557	2		T929	10		T560	1
values[19]	357	1			T557	2		T929	9		T560	1
values[20]	355	1			T557	3		T929	4		T560	1
values[21]	335	1			T557	1		T929	9		T560	1
values[22]	373	1			T557	4		T929	8		T560	1
values[23]	360	1			T557	1		T929	10		T560	1
values[24]	306	1			T557	1		T929	10		T560	1
values[25]	317	1			T557	2		T929	10		T560	2
values[26]	280	1			T557	1		T929	7		T560	1
values[27]	335	1			T557	1		T929	7		T560	1
values[28]	352	1			T557	2		T929	8		T560	1
values[29]	388	1			T557	1		T929	5		T560	1
values[30]	330	1			T557	1		T929	5		T560	1
values[31]	410	1			T557	2		T929	33		T560	1
values[32]	349	1			T557	3		T929	7		T560	1
values[33]	323	1			T557	2		T929	3		T560	1
values[34]	335	1			T557	2		T929	4		T560	1
values[35]	333	1			T557	2		T929	3		T560	1
values[36]	322	1			T557	5		T929	7		T560	1
values[37]	302	1			T557	2		T929	3		T560	1
values[38]	279	1			T557	6		T929	7		T560	1
values[39]	290	1			T557	6		T929	8		T560	1
values[40]	291	1			T557	6		T929	10		T560	1
values[41]	273	1			T557	3		T929	6		T560	1
values[42]	293	1			T557	1		T929	3		T560	1
values[43]	304	1			T557	1		T929	4		T560	1
values[44]	290	1			T557	1		T929	4		T560	1
values[45]	259	1			T557	3		T929	13		T560	1
values[46]	245	1			T557	1		T929	4		T560	1
values[47]	347	1			T557	1		T929	8		T560	1
values[48]	276	1			T557	1		T929	5		T560	1
values[49]	251	1			T557	2		T929	8		T560	1
values[50]	257	1			T557	1		T929	10		T560	1
values[51]	282	1			T557	1		T929	8		T560	1
values[52]	283	1			T557	5		T929	6		T560	1
values[53]	294	1			T557	2		T929	3		T560	1
values[54]	294	1			T557	3		T929	17		T560	1
values[55]	233	1			T557	10		T929	8		T560	1
values[56]	243	1			T557	5		T560	1		T906	8
values[57]	259	1			T557	4		T560	1		T906	4
values[58]	260	1			T557	2		T560	1		T906	4
values[59]	192	1			T557	3		T560	1		T906	3
values[60]	221	1			T557	1		T560	1		T906	5
values[61]	266	1			T557	6		T560	1		T906	4
values[62]	204	1			T557	11		T560	1		T906	6
values[63]	214	1			T557	8		T560	1		T906	7
values[64]	193	1			T557	6		T560	1		T906	4
values[65]	219	1			T557	5		T560	1		T906	8
values[66]	164	1			T557	1		T560	1		T906	2
values[67]	193	1			T557	3		T560	1		T906	4
values[68]	140	1			T557	2		T560	1		T906	5
values[69]	175	1			T557	1		T560	1		T906	4
values[70]	194	1			T557	2		T560	1		T906	6
values[71]	160	1			T557	4		T560	1		T906	3
values[72]	137	1			T560	1		T906	5		T892	1
values[73]	130	1			T560	1		T906	3		T892	1
values[74]	137	1			T560	1		T906	5		T892	1
values[75]	153	1			T560	1		T906	4		T892	1
values[76]	119	1			T560	1		T906	10		T892	1
values[77]	151	1			T560	1		T906	10		T892	1
values[78]	159	1			T560	1		T906	3		T892	1
values[79]	140	1			T560	1		T906	7		T892	1
values[80]	103	1			T560	1		T906	8		T892	1
values[81]	111	1			T560	1		T906	6		T892	1
values[82]	93	1			T560	1		T906	9		T892	1
values[83]	151	1			T560	1		T906	4		T892	1
values[84]	108	1			T560	1		T906	7		T892	1
values[85]	93	1			T560	1		T906	4		T892	1
values[86]	127	1			T560	1		T906	6		T892	1
values[87]	128	1			T560	1		T906	8		T892	1
values[88]	116	1			T560	1		T906	10		T892	1
values[89]	118	1			T560	1		T906	14		T892	1
values[90]	113	1			T560	1		T906	8		T892	1
values[91]	99	1			T560	1		T906	6		T892	1
values[92]	93	1			T560	1		T906	5		T892	1
values[93]	101	1			T560	1		T906	7		T892	1
values[94]	105	1			T560	1		T906	11		T892	1
values[95]	87	1			T560	1		T906	4		T892	1
values[96]	111	1			T560	1		T906	6		T892	1
values[97]	118	1			T560	1		T906	8		T892	1
values[98]	98	1			T560	1		T906	4		T892	1
values[99]	117	1			T560	1		T906	8		T892	1
values[100]	93	1			T560	1		T906	3		T892	1
values[101]	93	1			T560	1		T906	2		T892	1
values[102]	82	1			T560	1		T906	4		T892	1
values[103]	73	1			T560	1		T906	2		T892	1
values[104]	81	1			T560	1		T906	6		T892	1
values[105]	95	1			T560	1		T906	3		T892	1
values[106]	111	1			T560	1		T906	12		T892	1
values[107]	107	1			T560	1		T906	5		T892	1
values[108]	130	1			T560	1		T906	8		T892	1
values[109]	114	1			T560	1		T906	4		T892	1
values[110]	71	1			T560	1		T906	4		T892	1
values[111]	65	1			T560	1		T906	4		T892	1
values[112]	67	1			T560	1		T906	4		T892	3
values[113]	61	1			T560	1		T906	5		T892	1
values[114]	76	1			T560	1		T906	7		T892	2
values[115]	66	1			T560	1		T906	9		T892	2
values[116]	63	1			T560	1		T906	12		T892	2
values[117]	78	1			T560	1		T906	12		T892	1
values[118]	63	1			T560	1		T906	7		T892	1
values[119]	55	1			T560	4		T906	8		T892	1
values[120]	70	1			T560	4		T906	10		T892	1
values[121]	91	1			T560	3		T906	19		T892	2
values[122]	102	1			T560	1		T906	14		T892	2
values[123]	67	1			T560	3		T906	13		T892	2
values[124]	69	1			T560	1		T906	14		T892	1
values[125]	108	1			T560	8		T906	22		T892	3
values[126]	184	1			T560	2		T906	40		T892	1
values[127]	862	1			T560	31		T906	79		T892	31
values[128]	5616	1			T560	395		T906	36		T892	317