Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	160034	1			T81	5		T82	72		T83	3
values[2]	4237	1			T82	1		T135	1		T552	1
values[3]	2037	1			T551	47		T733	6		T422	10
values[4]	1584	1			T551	47		T733	6		T422	3
values[5]	1352	1			T551	36		T733	2		T422	2
values[6]	1094	1			T551	26		T733	1		T422	5
values[7]	927	1			T551	20		T733	5		T422	2
values[8]	875	1			T551	30		T733	12		T422	4
values[9]	806	1			T551	30		T733	9		T422	9
values[10]	692	1			T551	21		T733	4		T422	12
values[11]	624	1			T551	23		T733	5		T422	7
values[12]	559	1			T551	33		T733	5		T422	5
values[13]	423	1			T551	21		T733	2		T422	5
values[14]	390	1			T551	8		T733	4		T422	5
values[15]	366	1			T551	7		T733	4		T422	15
values[16]	367	1			T551	6		T733	4		T422	35
values[17]	329	1			T551	6		T733	6		T422	27
values[18]	289	1			T551	4		T733	12		T422	25
values[19]	284	1			T551	11		T733	17		T422	17
values[20]	291	1			T551	11		T733	5		T422	16
values[21]	321	1			T551	4		T733	11		T422	15
values[22]	308	1			T551	7		T733	9		T422	8
values[23]	282	1			T551	7		T422	7		T906	20
values[24]	253	1			T551	5		T422	7		T906	17
values[25]	192	1			T551	1		T422	7		T906	22
values[26]	218	1			T551	2		T422	8		T906	34
values[27]	221	1			T551	3		T422	11		T906	35
values[28]	199	1			T551	3		T422	9		T906	20
values[29]	202	1			T551	5		T422	13		T906	12
values[30]	183	1			T551	2		T422	7		T906	25
values[31]	202	1			T551	1		T422	5		T906	25
values[32]	202	1			T551	5		T422	4		T906	17
values[33]	192	1			T551	2		T422	2		T906	22
values[34]	186	1			T551	4		T422	7		T906	31
values[35]	223	1			T551	4		T422	24		T906	35
values[36]	177	1			T551	4		T422	23		T906	18
values[37]	180	1			T551	6		T422	19		T906	6
values[38]	158	1			T551	4		T422	12		T906	1
values[39]	131	1			T551	1		T422	14		T482	5
values[40]	109	1			T551	2		T422	4		T482	5
values[41]	103	1			T551	1		T422	5		T892	1
values[42]	106	1			T551	2		T422	11		T892	1
values[43]	99	1			T551	3		T422	10		T892	1
values[44]	95	1			T551	4		T422	4		T892	1
values[45]	96	1			T551	3		T422	8		T892	1
values[46]	98	1			T551	2		T422	10		T892	1
values[47]	92	1			T551	3		T422	8		T892	1
values[48]	85	1			T551	3		T422	11		T892	1
values[49]	88	1			T551	3		T422	16		T892	1
values[50]	82	1			T551	1		T422	15		T892	1
values[51]	85	1			T551	3		T422	5		T892	1
values[52]	77	1			T551	5		T892	1		T502	1
values[53]	76	1			T551	1		T892	1		T502	1
values[54]	95	1			T551	4		T892	1		T502	1
values[55]	78	1			T551	2		T892	1		T502	1
values[56]	97	1			T551	2		T892	1		T502	1
values[57]	113	1			T551	3		T892	1		T502	1
values[58]	122	1			T551	7		T892	1		T502	1
values[59]	96	1			T551	2		T892	1		T502	1
values[60]	84	1			T551	4		T892	1		T502	1
values[61]	94	1			T551	1		T892	1		T502	1
values[62]	87	1			T551	3		T892	1		T502	1
values[63]	83	1			T551	2		T892	1		T502	1
values[64]	78	1			T551	2		T892	1		T502	1
values[65]	72	1			T551	2		T892	1		T502	1
values[66]	78	1			T551	2		T892	1		T502	1
values[67]	89	1			T551	2		T892	1		T502	1
values[68]	85	1			T551	1		T892	1		T502	1
values[69]	74	1			T551	1		T892	1		T502	1
values[70]	65	1			T551	3		T892	1		T502	1
values[71]	52	1			T551	2		T892	1		T502	1
values[72]	68	1			T551	3		T892	1		T502	1
values[73]	75	1			T551	2		T892	1		T502	1
values[74]	83	1			T551	2		T892	1		T502	1
values[75]	72	1			T551	1		T892	1		T502	1
values[76]	78	1			T551	1		T892	1		T502	1
values[77]	99	1			T551	2		T892	2		T502	1
values[78]	79	1			T551	5		T892	1		T502	1
values[79]	74	1			T551	1		T892	1		T502	1
values[80]	92	1			T551	2		T892	3		T502	1
values[81]	69	1			T551	2		T892	1		T502	1
values[82]	75	1			T551	1		T892	1		T502	1
values[83]	79	1			T551	1		T892	2		T502	1
values[84]	85	1			T551	1		T892	2		T502	2
values[85]	81	1			T551	3		T892	3		T502	1
values[86]	109	1			T551	6		T892	1		T502	1
values[87]	81	1			T551	5		T892	1		T502	1
values[88]	111	1			T551	3		T892	4		T502	1
values[89]	90	1			T551	5		T892	4		T502	1
values[90]	115	1			T551	2		T892	10		T502	1
values[91]	89	1			T551	2		T892	7		T502	1
values[92]	93	1			T551	3		T892	5		T502	1
values[93]	86	1			T551	1		T892	3		T502	1
values[94]	108	1			T551	1		T892	1		T502	1
values[95]	104	1			T551	4		T892	3		T502	1
values[96]	105	1			T551	2		T892	2		T502	1
values[97]	126	1			T551	3		T892	3		T502	1
values[98]	110	1			T551	5		T892	6		T502	1
values[99]	97	1			T551	1		T892	3		T502	1
values[100]	129	1			T551	2		T892	4		T502	1
values[101]	112	1			T551	2		T892	1		T502	5
values[102]	113	1			T551	1		T892	3		T502	6
values[103]	117	1			T551	1		T892	1		T502	1
values[104]	115	1			T551	3		T892	1		T502	1
values[105]	128	1			T551	3		T892	1		T502	3
values[106]	119	1			T551	4		T892	3		T502	1
values[107]	139	1			T551	4		T892	2		T502	1
values[108]	139	1			T551	4		T892	3		T502	1
values[109]	123	1			T551	4		T892	3		T502	1
values[110]	112	1			T551	2		T892	5		T502	2
values[111]	114	1			T551	1		T892	1		T502	1
values[112]	125	1			T551	5		T892	1		T502	3
values[113]	99	1			T551	4		T892	1		T502	1
values[114]	109	1			T551	5		T892	1		T502	4
values[115]	110	1			T551	6		T892	4		T502	5
values[116]	137	1			T551	3		T892	3		T502	4
values[117]	118	1			T551	10		T892	2		T502	1
values[118]	113	1			T551	6		T892	2		T502	1
values[119]	122	1			T551	4		T892	1		T502	4
values[120]	144	1			T551	6		T892	2		T502	1
values[121]	131	1			T551	6		T892	1		T502	2
values[122]	135	1			T551	7		T892	2		T502	1
values[123]	177	1			T551	5		T892	2		T502	1
values[124]	268	1			T551	16		T892	1		T502	3
values[125]	539	1			T551	36		T892	1		T502	3
values[126]	808	1			T551	73		T892	9		T502	13
values[127]	2064	1			T551	51		T892	95		T502	99
values[128]	3282	1			T551	2		T892	199		T502	257