Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	437	1			T551	1		T557	2		T440	1
all_values[1]	491	1			T134	2		T551	2		T523	4
all_values[2]	469	1			T134	1		T523	1		T557	2
all_values[3]	452	1			T134	2		T551	1		T523	1
all_values[4]	454	1			T551	1		T909	1		T557	3
all_values[5]	444	1			T134	4		T551	1		T523	3
all_values[6]	458	1			T134	2		T551	2		T523	4
all_values[7]	475	1			T134	2		T523	2		T557	5
all_values[8]	460	1			T134	4		T255	2		T256	1
all_values[9]	444	1			T134	2		T256	1		T523	3
all_values[10]	478	1			T134	4		T255	1		T523	2
all_values[11]	480	1			T134	2		T256	1		T551	1
all_values[12]	510	1			T134	4		T255	1		T551	1
all_values[13]	418	1			T551	1		T523	1		T557	4
all_values[14]	456	1			T134	3		T523	3		T557	1
all_values[15]	456	1			T134	4		T551	2		T523	3
all_values[16]	488	1			T134	3		T256	1		T551	1
all_values[17]	474	1			T134	1		T255	2		T551	1
all_values[18]	474	1			T134	2		T256	1		T551	1
all_values[19]	431	1			T134	3		T551	1		T557	1
all_values[20]	482	1			T134	3		T255	2		T551	1
all_values[21]	430	1			T134	1		T256	1		T557	6
all_values[22]	482	1			T134	2		T255	1		T551	1
all_values[23]	460	1			T134	4		T551	1		T523	2
all_values[24]	461	1			T134	2		T255	1		T557	3
all_values[25]	474	1			T256	1		T523	2		T583	2
all_values[26]	444	1			T256	1		T551	2		T523	2
all_values[27]	463	1			T134	3		T551	1		T557	1
all_values[28]	455	1			T523	4		T557	3		T559	1
all_values[29]	470	1			T134	2		T255	1		T256	1
all_values[30]	460	1			T255	2		T523	4		T557	2
all_values[31]	460	1			T134	1		T551	3		T523	1
all_values[32]	473	1			T256	1		T551	1		T523	2
all_values[33]	480	1			T255	2		T256	1		T551	1
all_values[34]	491	1			T134	3		T551	1		T557	3
all_values[35]	433	1			T134	2		T523	1		T557	1
all_values[36]	462	1			T134	4		T255	1		T523	4
all_values[37]	495	1			T134	1		T256	1		T523	3
all_values[38]	461	1			T134	3		T255	2		T551	3
all_values[39]	475	1			T134	1		T523	2		T557	1
all_values[40]	452	1			T134	1		T909	1		T557	2
all_values[41]	418	1			T134	5		T523	2		T557	1
all_values[42]	473	1			T134	1		T255	3		T551	2
all_values[43]	458	1			T134	1		T551	2		T523	1
all_values[44]	503	1			T134	3		T523	4		T557	1
all_values[45]	471	1			T134	2		T255	1		T551	2
all_values[46]	493	1			T134	2		T551	1		T523	4
all_values[47]	450	1			T134	1		T523	1		T557	3
all_values[48]	446	1			T134	4		T551	1		T523	4
all_values[49]	468	1			T134	2		T255	1		T523	2