Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3785	1			T134	6		T255	9		T256	4
all_values[1]	3669	1			T134	20		T255	10		T256	1
all_values[2]	3601	1			T134	13		T255	2		T256	1
all_values[3]	3621	1			T134	16		T255	3		T256	1
all_values[4]	3556	1			T134	13		T255	8		T256	2
all_values[5]	3570	1			T134	4		T255	3		T549	2
all_values[6]	3605	1			T134	7		T255	11		T256	5
all_values[7]	3643	1			T134	13		T255	8		T256	4
all_values[8]	3531	1			T134	8		T255	9		T256	1
all_values[9]	3680	1			T134	10		T255	5		T256	3
all_values[10]	3571	1			T134	14		T255	3		T256	1
all_values[11]	3670	1			T134	5		T255	8		T256	1
all_values[12]	3675	1			T134	15		T255	8		T256	1
all_values[13]	3556	1			T134	12		T255	7		T256	3
all_values[14]	3742	1			T134	9		T255	12		T256	1
all_values[15]	3650	1			T134	10		T255	3		T256	3
all_values[16]	3679	1			T134	18		T255	6		T256	1
all_values[17]	3632	1			T134	14		T255	8		T256	2
all_values[18]	3587	1			T134	12		T255	2		T256	2
all_values[19]	3542	1			T134	16		T255	7		T551	8
all_values[20]	3595	1			T134	13		T255	9		T256	1
all_values[21]	3650	1			T134	9		T255	7		T256	2
all_values[22]	3638	1			T134	5		T255	7		T551	7
all_values[23]	3674	1			T134	12		T255	4		T256	2
all_values[24]	3470	1			T134	9		T255	6		T256	3
all_values[25]	3684	1			T134	9		T255	6		T256	5
all_values[26]	3631	1			T134	12		T255	5		T256	3
all_values[27]	3460	1			T134	9		T255	4		T256	1
all_values[28]	3580	1			T134	13		T255	5		T256	1
all_values[29]	3568	1			T134	11		T255	6		T256	3
all_values[30]	3579	1			T134	16		T255	5		T256	2
all_values[31]	3491	1			T134	11		T255	5		T256	1
all_values[32]	3664	1			T134	16		T255	5		T256	3
all_values[33]	3665	1			T134	14		T255	6		T256	1
all_values[34]	3591	1			T134	13		T255	6		T256	3
all_values[35]	3635	1			T134	8		T255	5		T549	5
all_values[36]	3599	1			T134	5		T255	4		T549	1
all_values[37]	3588	1			T134	8		T255	9		T256	5
all_values[38]	3635	1			T134	18		T255	5		T256	1
all_values[39]	3591	1			T134	11		T255	4		T256	4
all_values[40]	3599	1			T134	7		T255	7		T256	2
all_values[41]	3698	1			T134	9		T255	6		T256	1
all_values[42]	3701	1			T134	10		T255	7		T256	3
all_values[43]	3423	1			T134	7		T255	7		T256	2
all_values[44]	3692	1			T134	11		T255	4		T256	5
all_values[45]	3612	1			T134	14		T255	8		T256	1
all_values[46]	3579	1			T134	16		T255	5		T256	1
all_values[47]	3573	1			T134	8		T255	5		T256	2
all_values[48]	3705	1			T134	13		T255	6		T256	1
all_values[49]	3566	1			T134	10		T255	4		T256	1
all_values[50]	3618	1			T134	5		T255	3		T256	3
all_values[51]	3673	1			T134	4		T255	6		T256	2
all_values[52]	3629	1			T134	12		T255	6		T256	2
all_values[53]	3576	1			T134	7		T255	8		T256	1
all_values[54]	3638	1			T134	13		T255	4		T256	2
all_values[55]	3618	1			T134	20		T255	1		T256	3
all_values[56]	3615	1			T134	7		T255	6		T551	8
all_values[57]	3514	1			T134	6		T255	5		T549	1
all_values[58]	3599	1			T134	10		T255	8		T256	2
all_values[59]	3512	1			T134	9		T255	4		T256	3
all_values[60]	3493	1			T134	8		T255	11		T256	2
all_values[61]	3715	1			T134	13		T255	9		T256	2
all_values[62]	3638	1			T134	14		T255	5		T256	2
all_values[63]	3531	1			T134	4		T255	7		T256	3