Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sensor_ctrl_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	141919	1			T76	53		T77	17		T78	7
values[2]	9036	1			T76	4		T78	1		T152	1
values[3]	3309	1			T443	12		T554	2		T503	18
values[4]	2261	1			T443	2		T554	5		T503	3
values[5]	1541	1			T554	5		T503	9		T712	3
values[6]	1084	1			T554	5		T503	6		T712	14
values[7]	902	1			T554	2		T503	7		T712	5
values[8]	786	1			T554	2		T503	4		T712	5
values[9]	625	1			T554	2		T503	8		T712	17
values[10]	568	1			T554	3		T503	12		T712	6
values[11]	462	1			T554	5		T503	6		T712	3
values[12]	445	1			T554	2		T503	3		T712	5
values[13]	419	1			T554	1		T503	9		T712	3
values[14]	474	1			T554	2		T503	7		T712	3
values[15]	446	1			T554	1		T503	6		T712	12
values[16]	441	1			T554	7		T503	6		T712	12
values[17]	366	1			T554	3		T503	13		T712	5
values[18]	416	1			T554	5		T503	6		T712	4
values[19]	451	1			T554	2		T503	20		T712	7
values[20]	438	1			T554	2		T503	6		T712	4
values[21]	361	1			T554	1		T503	7		T712	5
values[22]	386	1			T554	1		T503	2		T712	5
values[23]	395	1			T554	2		T503	15		T712	19
values[24]	426	1			T554	1		T503	10		T712	7
values[25]	395	1			T554	1		T503	8		T712	4
values[26]	363	1			T554	2		T503	4		T712	3
values[27]	388	1			T554	2		T503	8		T712	6
values[28]	355	1			T554	1		T503	4		T712	6
values[29]	375	1			T554	1		T503	9		T712	20
values[30]	382	1			T554	3		T503	3		T712	5
values[31]	424	1			T554	2		T503	14		T712	7
values[32]	326	1			T554	1		T503	4		T712	4
values[33]	325	1			T554	3		T503	3		T712	4
values[34]	343	1			T554	2		T503	4		T712	8
values[35]	371	1			T554	1		T503	12		T712	19
values[36]	402	1			T554	2		T503	12		T712	11
values[37]	354	1			T554	2		T503	24		T712	4
values[38]	342	1			T554	2		T503	12		T712	4
values[39]	367	1			T554	9		T503	6		T712	4
values[40]	347	1			T554	3		T503	5		T712	4
values[41]	357	1			T554	3		T503	8		T712	11
values[42]	352	1			T554	1		T503	3		T712	6
values[43]	327	1			T554	1		T503	3		T712	3
values[44]	325	1			T554	1		T503	2		T712	7
values[45]	348	1			T554	2		T503	3		T712	14
values[46]	363	1			T554	3		T503	3		T712	6
values[47]	318	1			T554	1		T712	5		T876	1
values[48]	316	1			T554	7		T712	4		T876	1
values[49]	329	1			T554	2		T712	5		T876	1
values[50]	326	1			T554	9		T712	5		T876	1
values[51]	376	1			T554	7		T712	9		T876	1
values[52]	364	1			T554	1		T712	14		T876	1
values[53]	305	1			T554	2		T712	8		T876	1
values[54]	324	1			T554	1		T712	9		T876	1
values[55]	352	1			T554	4		T712	4		T876	1
values[56]	308	1			T554	2		T712	9		T876	1
values[57]	294	1			T554	4		T712	12		T876	1
values[58]	285	1			T554	3		T712	5		T876	1
values[59]	245	1			T554	3		T712	4		T876	1
values[60]	222	1			T554	2		T712	3		T876	2
values[61]	217	1			T554	1		T712	5		T876	1
values[62]	200	1			T554	2		T712	4		T876	1
values[63]	246	1			T554	4		T712	4		T876	1
values[64]	236	1			T554	3		T712	4		T876	1
values[65]	246	1			T554	4		T712	13		T876	1
values[66]	224	1			T554	12		T712	7		T876	1
values[67]	217	1			T554	14		T712	6		T876	1
values[68]	208	1			T554	12		T876	1		T860	3
values[69]	172	1			T554	11		T876	1		T860	3
values[70]	151	1			T554	9		T876	1		T860	11
values[71]	207	1			T554	7		T876	1		T860	11
values[72]	185	1			T554	11		T876	1		T860	19
values[73]	148	1			T554	3		T876	1		T860	12
values[74]	154	1			T554	9		T876	1		T860	3
values[75]	108	1			T554	8		T876	1		T860	7
values[76]	104	1			T554	6		T876	1		T860	4
values[77]	110	1			T554	8		T876	1		T860	4
values[78]	98	1			T554	4		T876	1		T860	4
values[79]	104	1			T554	3		T876	1		T860	10
values[80]	103	1			T554	5		T876	1		T860	6
values[81]	124	1			T554	4		T876	1		T860	7
values[82]	97	1			T554	5		T876	1		T860	5
values[83]	101	1			T554	6		T876	3		T860	1
values[84]	95	1			T554	3		T876	8		T860	3
values[85]	118	1			T554	4		T876	3		T860	6
values[86]	109	1			T554	5		T876	6		T860	3
values[87]	88	1			T554	6		T876	3		T860	2
values[88]	98	1			T554	5		T876	5		T860	6
values[89]	117	1			T554	11		T876	2		T860	12
values[90]	94	1			T554	7		T876	2		T860	6
values[91]	99	1			T554	9		T876	3		T860	7
values[92]	118	1			T554	2		T876	2		T860	3
values[93]	96	1			T554	2		T876	3		T860	4
values[94]	93	1			T554	4		T876	1		T860	2
values[95]	87	1			T554	4		T876	3		T860	2
values[96]	111	1			T554	5		T876	6		T860	2
values[97]	91	1			T554	5		T876	1		T860	8
values[98]	103	1			T554	3		T876	3		T860	9
values[99]	75	1			T876	1		T860	4		T889	1
values[100]	70	1			T876	1		T860	9		T889	1
values[101]	74	1			T876	1		T860	7		T889	2
values[102]	65	1			T876	1		T860	8		T889	1
values[103]	86	1			T876	2		T860	11		T889	1
values[104]	85	1			T876	1		T860	22		T889	1
values[105]	83	1			T876	1		T860	18		T889	1
values[106]	90	1			T876	4		T860	4		T889	1
values[107]	101	1			T876	1		T860	6		T889	1
values[108]	100	1			T876	1		T860	17		T889	1
values[109]	81	1			T876	5		T860	5		T889	1
values[110]	89	1			T876	2		T860	1		T889	1
values[111]	90	1			T876	3		T860	2		T889	1
values[112]	62	1			T876	2		T860	3		T889	1
values[113]	65	1			T876	3		T860	2		T889	1
values[114]	62	1			T876	2		T860	4		T889	1
values[115]	56	1			T876	6		T860	4		T889	1
values[116]	60	1			T876	1		T860	3		T889	3
values[117]	59	1			T876	1		T860	4		T889	1
values[118]	48	1			T876	2		T889	1		T890	1
values[119]	46	1			T876	1		T889	2		T890	1
values[120]	55	1			T876	1		T889	2		T890	1
values[121]	63	1			T876	7		T889	4		T890	1
values[122]	57	1			T876	4		T889	1		T890	1
values[123]	48	1			T876	1		T889	4		T890	1
values[124]	51	1			T876	1		T889	1		T890	2
values[125]	64	1			T876	1		T889	2		T890	1
values[126]	122	1			T876	1		T889	2		T890	6
values[127]	796	1			T876	27		T889	40		T890	43
values[128]	6582	1			T876	272		T889	356		T890	392