Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.25 95.48 94.26 95.49 95.20 97.53 99.52


Total tests in report: 2932
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
39.50 39.50 44.62 44.62 42.96 42.96 31.71 31.71 57.86 57.86 59.44 59.44 0.39 0.39 /workspace/coverage/default/33.chip_sw_all_escalation_resets.2595161287
50.56 11.07 55.05 10.44 59.36 16.40 36.19 4.49 68.54 10.69 82.52 23.08 1.70 1.32 /workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.4190348363
56.08 5.52 66.77 11.72 67.25 7.89 39.20 3.01 79.07 10.52 82.52 0.00 1.70 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_0.129135832
60.86 4.78 73.00 6.23 68.21 0.96 42.69 3.49 79.16 0.10 82.52 0.00 19.60 17.89 /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.550671107
65.26 4.39 73.00 0.00 68.59 0.38 42.69 0.00 79.33 0.16 82.52 0.00 45.42 25.83 /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.12699406
68.76 3.51 79.07 6.07 73.03 4.44 46.65 3.96 81.35 2.03 87.06 4.55 45.42 0.00 /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.207814563
72.22 3.45 83.09 4.02 76.59 3.56 52.74 6.09 84.70 3.34 90.38 3.32 45.80 0.38 /workspace/coverage/default/0.chip_jtag_csr_rw.3362936665
74.63 2.42 85.66 2.57 79.26 2.68 59.39 6.65 86.78 2.09 90.91 0.52 45.80 0.00 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1077240967
77.01 2.37 85.66 0.00 79.46 0.19 59.39 0.00 86.83 0.05 90.91 0.00 59.79 13.99 /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.2220542716
79.03 2.02 85.66 0.00 79.46 0.00 71.53 12.14 86.83 0.00 90.91 0.00 59.79 0.00 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2439317437
80.80 1.77 85.66 0.00 80.07 0.61 71.53 0.00 86.95 0.11 90.91 0.00 69.70 9.90 /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.1729249884
82.22 1.42 85.66 0.00 80.27 0.20 71.53 0.00 86.95 0.00 90.91 0.00 78.03 8.33 /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.1999101419
83.38 1.15 85.69 0.03 80.27 0.00 78.43 6.90 86.95 0.00 90.91 0.00 78.03 0.00 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.495268168
84.43 1.05 85.69 0.00 80.27 0.00 78.43 0.00 86.95 0.00 90.91 0.00 84.33 6.30 /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.1549074997
85.32 0.90 86.98 1.29 82.02 1.76 78.71 0.28 88.65 1.70 91.26 0.35 84.33 0.00 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.407977462
86.03 0.71 87.14 0.15 82.13 0.11 78.72 0.01 88.76 0.11 95.10 3.85 84.33 0.00 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1987194543
86.69 0.66 87.24 0.10 82.13 0.00 82.18 3.46 88.76 0.00 95.10 0.00 84.73 0.40 /workspace/coverage/default/2.chip_jtag_csr_rw.93724595
87.32 0.63 87.24 0.00 82.35 0.21 82.18 0.00 88.78 0.02 95.10 0.00 88.27 3.55 /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.4129258152
87.89 0.57 88.06 0.82 83.01 0.67 82.81 0.63 89.74 0.97 95.45 0.35 88.29 0.01 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.4070110845
88.46 0.57 89.09 1.04 83.93 0.92 83.51 0.70 90.43 0.69 95.45 0.00 88.34 0.06 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2229977943
88.97 0.51 89.09 0.00 83.93 0.00 83.51 0.00 90.43 0.00 95.45 0.00 91.40 3.05 /workspace/coverage/cover_reg_top/3.xbar_access_same_device.3999355436
89.47 0.50 89.69 0.60 84.43 0.50 84.90 1.39 90.95 0.51 95.45 0.00 91.40 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_10.986350269
89.97 0.50 90.60 0.91 85.27 0.84 85.37 0.47 91.70 0.75 95.45 0.00 91.40 0.00 /workspace/coverage/default/2.chip_sw_gpio.3818547904
90.39 0.42 90.61 0.01 85.28 0.01 87.83 2.46 91.70 0.00 95.45 0.00 91.45 0.05 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3048308534
90.79 0.40 91.16 0.55 85.75 0.48 88.04 0.21 92.28 0.58 95.98 0.52 91.49 0.05 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1800061348
91.18 0.40 91.59 0.43 87.11 1.35 88.15 0.11 92.39 0.11 95.98 0.00 91.87 0.38 /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.747181361
91.55 0.37 91.59 0.00 87.51 0.41 88.15 0.01 92.43 0.04 95.98 0.00 93.62 1.75 /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.3762392358
91.91 0.36 92.34 0.75 88.12 0.61 88.31 0.16 93.09 0.66 95.98 0.00 93.62 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_20.530689283
92.19 0.28 93.10 0.76 88.13 0.01 88.46 0.15 93.10 0.01 95.98 0.00 94.35 0.73 /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.817736165
92.46 0.27 93.11 0.01 89.70 1.57 88.46 0.00 93.10 0.00 95.98 0.00 94.38 0.04 /workspace/coverage/cover_reg_top/0.chip_tl_errors.1027844267
92.72 0.26 93.11 0.00 89.70 0.00 89.48 1.01 93.10 0.00 95.98 0.00 94.95 0.56 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.207265941
92.93 0.21 93.11 0.00 89.71 0.01 89.48 0.00 93.10 0.00 95.98 0.00 96.18 1.23 /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.1569489487
93.11 0.19 93.15 0.03 90.23 0.53 89.48 0.01 93.66 0.57 95.98 0.00 96.18 0.00 /workspace/coverage/default/1.chip_jtag_csr_rw.1835772670
93.30 0.18 93.20 0.05 90.24 0.01 90.52 1.04 93.67 0.01 95.98 0.00 96.18 0.00 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3958901292
93.44 0.15 93.40 0.21 90.56 0.32 90.87 0.35 93.67 0.00 95.98 0.00 96.18 0.00 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.454060386
93.59 0.14 93.59 0.18 90.74 0.18 91.17 0.29 93.87 0.20 95.98 0.00 96.18 0.00 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.273220633
93.71 0.13 93.74 0.16 90.83 0.09 91.23 0.06 93.97 0.10 96.33 0.35 96.18 0.00 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1697569717
93.83 0.12 93.74 0.00 90.83 0.00 91.23 0.00 93.97 0.00 96.33 0.00 96.90 0.72 /workspace/coverage/cover_reg_top/1.xbar_access_same_device.2716934150
93.94 0.11 93.74 0.00 90.83 0.00 91.83 0.60 93.97 0.00 96.33 0.00 96.95 0.05 /workspace/coverage/default/42.chip_sw_all_escalation_resets.377565272
94.05 0.11 93.89 0.15 90.97 0.14 92.03 0.20 94.12 0.15 96.33 0.00 96.95 0.00 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2730631347
94.15 0.10 93.89 0.00 90.97 0.00 92.63 0.60 94.12 0.00 96.33 0.00 96.97 0.02 /workspace/coverage/default/0.chip_sw_flash_init.2166056586
94.25 0.10 93.89 0.00 91.54 0.57 92.63 0.00 94.12 0.00 96.33 0.00 96.98 0.01 /workspace/coverage/cover_reg_top/5.chip_tl_errors.3529868296
94.34 0.09 94.02 0.12 91.71 0.17 92.69 0.06 94.29 0.17 96.33 0.00 96.98 0.00 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3088253819
94.41 0.08 94.02 0.01 91.93 0.22 92.70 0.01 94.53 0.24 96.33 0.00 96.98 0.00 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3249765418
94.49 0.08 94.03 0.01 91.95 0.02 92.96 0.26 94.53 0.00 96.50 0.17 96.99 0.01 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1324562086
94.57 0.07 94.04 0.02 91.98 0.04 92.98 0.02 94.53 0.00 96.50 0.00 97.36 0.36 /workspace/coverage/default/0.chip_sw_alert_test.3387762688
94.64 0.07 94.17 0.13 92.11 0.13 93.02 0.04 94.65 0.12 96.50 0.00 97.36 0.00 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.676592701
94.71 0.07 94.17 0.00 92.11 0.00 93.44 0.41 94.65 0.00 96.50 0.00 97.36 0.00 /workspace/coverage/default/2.chip_sw_edn_auto_mode.4015845236
94.77 0.07 94.32 0.15 92.15 0.04 93.45 0.01 94.68 0.02 96.68 0.17 97.37 0.01 /workspace/coverage/default/79.chip_sw_all_escalation_resets.2561208912
94.84 0.06 94.32 0.00 92.15 0.00 93.45 0.00 94.68 0.00 96.68 0.00 97.76 0.39 /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.756473655
94.90 0.06 94.39 0.07 92.27 0.11 93.56 0.11 94.74 0.06 96.68 0.00 97.76 0.00 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1488659031
94.96 0.06 94.39 0.00 92.27 0.00 93.91 0.35 94.74 0.00 96.68 0.00 97.76 0.00 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3589123672
95.01 0.05 94.39 0.00 92.41 0.14 93.91 0.01 94.90 0.16 96.68 0.00 97.76 0.00 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1733221097
95.06 0.05 94.39 0.01 92.42 0.01 94.00 0.09 94.91 0.01 96.85 0.17 97.77 0.01 /workspace/coverage/default/68.chip_sw_all_escalation_resets.2722889560
95.11 0.05 94.39 0.00 92.70 0.28 94.00 0.00 94.91 0.00 96.85 0.00 97.78 0.01 /workspace/coverage/cover_reg_top/19.chip_tl_errors.724979812
95.15 0.04 94.39 0.00 92.70 0.00 94.27 0.27 94.91 0.00 96.85 0.00 97.78 0.00 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.2590871580
95.19 0.04 94.44 0.04 92.90 0.20 94.27 0.01 94.92 0.01 96.85 0.00 97.78 0.00 /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.2670820385
95.23 0.04 94.45 0.01 92.91 0.01 94.27 0.00 94.95 0.02 97.03 0.17 97.79 0.01 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1009195868
95.27 0.04 94.45 0.00 92.93 0.02 94.27 0.00 94.95 0.00 97.03 0.00 98.00 0.21 /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.985877376
95.31 0.04 94.47 0.03 92.93 0.01 94.27 0.01 94.95 0.01 97.20 0.17 98.01 0.01 /workspace/coverage/default/63.chip_sw_all_escalation_resets.3399248686
95.34 0.04 94.48 0.01 92.94 0.01 94.28 0.01 94.96 0.01 97.38 0.17 98.03 0.01 /workspace/coverage/default/32.chip_sw_all_escalation_resets.2716662120
95.38 0.03 94.53 0.05 93.05 0.11 94.28 0.00 95.01 0.05 97.38 0.00 98.03 0.00 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.3558905006
95.41 0.03 94.53 0.00 93.05 0.00 94.28 0.00 95.01 0.00 97.38 0.00 98.23 0.20 /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.584565195
95.44 0.03 94.53 0.00 93.05 0.00 94.47 0.19 95.01 0.00 97.38 0.00 98.23 0.00 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.766535331
95.47 0.03 94.53 0.00 93.05 0.00 94.48 0.01 95.01 0.00 97.55 0.17 98.23 0.00 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.3331157500
95.50 0.03 94.60 0.07 93.08 0.03 94.49 0.01 95.06 0.05 97.55 0.00 98.23 0.00 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.619245509
95.53 0.03 94.67 0.07 93.08 0.00 94.57 0.08 95.07 0.01 97.55 0.00 98.23 0.00 /workspace/coverage/default/4.chip_tap_straps_rma.2832432605
95.55 0.03 94.67 0.00 93.16 0.08 94.57 0.00 95.08 0.02 97.55 0.00 98.28 0.06 /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.4205304938
95.58 0.03 94.67 0.00 93.31 0.15 94.57 0.00 95.08 0.00 97.55 0.00 98.28 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_0.2929795601
95.60 0.02 94.67 0.00 93.31 0.00 94.72 0.15 95.08 0.00 97.55 0.00 98.28 0.00 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1800025082
95.63 0.02 94.68 0.01 93.32 0.01 94.85 0.13 95.09 0.01 97.55 0.00 98.28 0.00 /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.3310686319
95.65 0.02 94.68 0.00 93.34 0.02 94.85 0.00 95.09 0.00 97.55 0.00 98.40 0.12 /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.545176663
95.67 0.02 94.73 0.06 93.39 0.05 94.85 0.00 95.12 0.02 97.55 0.00 98.40 0.00 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.3900793420
95.69 0.02 94.73 0.00 93.46 0.07 94.85 0.00 95.12 0.00 97.55 0.00 98.45 0.05 /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.635964847
95.71 0.02 94.73 0.00 93.57 0.11 94.85 0.00 95.12 0.00 97.55 0.00 98.45 0.00 /workspace/coverage/cover_reg_top/22.chip_tl_errors.3341810460
95.73 0.02 94.74 0.01 93.59 0.02 94.91 0.06 95.13 0.02 97.55 0.00 98.45 0.00 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.1926176501
95.74 0.02 94.74 0.00 93.59 0.00 95.00 0.09 95.13 0.00 97.55 0.00 98.45 0.00 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.420060460
95.76 0.01 94.74 0.00 93.68 0.09 95.00 0.00 95.13 0.00 97.55 0.00 98.45 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_0.1168410001
95.77 0.01 94.74 0.00 93.68 0.00 95.00 0.00 95.13 0.00 97.55 0.00 98.53 0.08 /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.3358037538
95.79 0.01 94.78 0.03 93.70 0.02 95.00 0.00 95.15 0.02 97.55 0.00 98.53 0.00 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.3377120345
95.80 0.01 94.78 0.00 93.70 0.00 95.07 0.07 95.15 0.00 97.55 0.00 98.53 0.00 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3215534080
95.81 0.01 94.78 0.00 93.76 0.05 95.07 0.00 95.16 0.02 97.55 0.00 98.53 0.00 /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.1486467994
95.82 0.01 94.78 0.00 93.76 0.00 95.07 0.00 95.16 0.00 97.55 0.00 98.59 0.06 /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.3942734819
95.83 0.01 94.78 0.00 93.81 0.06 95.07 0.00 95.16 0.00 97.55 0.00 98.59 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_20.2792066706
95.84 0.01 94.80 0.02 93.82 0.01 95.08 0.01 95.18 0.02 97.55 0.00 98.59 0.00 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2376473960
95.85 0.01 94.80 0.00 93.87 0.05 95.08 0.00 95.18 0.00 97.55 0.00 98.59 0.00 /workspace/coverage/cover_reg_top/29.chip_tl_errors.3854638098
95.85 0.01 94.80 0.00 93.87 0.00 95.08 0.00 95.18 0.00 97.55 0.00 98.64 0.05 /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.3555512624
95.86 0.01 94.82 0.02 93.88 0.01 95.09 0.01 95.18 0.00 97.55 0.00 98.64 0.00 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1115640888
95.87 0.01 94.84 0.01 93.90 0.02 95.09 0.00 95.19 0.01 97.55 0.00 98.64 0.00 /workspace/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.2793045151
95.87 0.01 94.84 0.00 93.90 0.00 95.13 0.04 95.19 0.00 97.55 0.00 98.64 0.00 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2741379636
95.88 0.01 94.84 0.00 93.90 0.00 95.17 0.04 95.19 0.00 97.55 0.00 98.64 0.00 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3215043656
95.89 0.01 94.84 0.00 93.90 0.00 95.21 0.04 95.19 0.00 97.55 0.00 98.64 0.00 /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2801577784
95.89 0.01 94.84 0.00 93.92 0.01 95.21 0.00 95.19 0.00 97.55 0.00 98.66 0.02 /workspace/coverage/cover_reg_top/2.xbar_stress_all.146856337
95.90 0.01 94.84 0.00 93.92 0.00 95.24 0.04 95.19 0.00 97.55 0.00 98.66 0.00 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1433198924
95.91 0.01 94.84 0.00 93.95 0.04 95.24 0.00 95.19 0.00 97.55 0.00 98.66 0.00 /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.103035996
95.91 0.01 94.84 0.00 93.96 0.01 95.24 0.00 95.19 0.00 97.55 0.00 98.68 0.02 /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.2655106023
95.92 0.01 94.84 0.00 93.99 0.03 95.24 0.00 95.19 0.00 97.55 0.00 98.68 0.00 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2071115881
95.92 0.01 94.84 0.00 93.99 0.01 95.27 0.02 95.19 0.00 97.55 0.00 98.68 0.00 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3708002180
95.92 0.01 94.84 0.00 93.99 0.00 95.27 0.00 95.19 0.00 97.55 0.00 98.71 0.02 /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.349890602
95.93 0.01 94.84 0.00 93.99 0.00 95.27 0.00 95.19 0.00 97.55 0.00 98.73 0.02 /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.2014024524
95.93 0.01 94.84 0.00 93.99 0.00 95.27 0.00 95.19 0.00 97.55 0.00 98.75 0.02 /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.1999999584
95.94 0.01 94.84 0.00 93.99 0.00 95.29 0.02 95.19 0.00 97.55 0.00 98.75 0.00 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2292319705
95.94 0.01 94.84 0.00 94.00 0.01 95.29 0.00 95.19 0.00 97.55 0.00 98.77 0.01 /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.1269241879
95.94 0.01 94.84 0.00 94.01 0.01 95.29 0.00 95.19 0.00 97.55 0.00 98.78 0.01 /workspace/coverage/cover_reg_top/7.chip_tl_errors.1403249935
95.95 0.01 94.84 0.01 94.03 0.01 95.30 0.01 95.19 0.00 97.55 0.00 98.78 0.00 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1355586697
95.95 0.01 94.84 0.00 94.05 0.02 95.30 0.00 95.19 0.00 97.55 0.00 98.78 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_10.3428443354
95.95 0.01 94.84 0.00 94.07 0.02 95.30 0.00 95.19 0.00 97.55 0.00 98.78 0.00 /workspace/coverage/default/1.chip_sw_gpio.2593509025
95.96 0.01 94.84 0.00 94.07 0.00 95.32 0.02 95.19 0.00 97.55 0.00 98.78 0.00 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.391065861
95.96 0.01 94.84 0.00 94.07 0.00 95.34 0.02 95.19 0.00 97.55 0.00 98.78 0.00 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2672817462
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96.15 0.01 94.90 0.01 94.26 0.00 95.47 0.00 95.20 0.00 97.55 0.00 99.52 0.00 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3236536541
96.15 0.01 94.90 0.00 94.26 0.00 95.48 0.01 95.20 0.00 97.55 0.00 99.52 0.00 /workspace/coverage/default/0.chip_sw_edn_boot_mode.2600832884
96.15 0.01 94.90 0.00 94.26 0.00 95.48 0.01 95.20 0.00 97.55 0.00 99.52 0.00 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1107549720
96.15 0.01 94.90 0.00 94.26 0.00 95.48 0.01 95.20 0.00 97.55 0.00 99.52 0.00 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2586227417
96.15 0.01 94.90 0.00 94.26 0.00 95.48 0.01 95.20 0.00 97.55 0.00 99.52 0.00 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1614056632
96.15 0.01 94.90 0.00 94.26 0.00 95.49 0.01 95.20 0.00 97.55 0.00 99.52 0.00 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2282602986

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3713254638
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3821107469
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.2818468090
/workspace/coverage/cover_reg_top/0.chip_csr_rw.1987467749
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1472518783
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1943053561
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2765460152
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2468851275
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2675902146
/workspace/coverage/cover_reg_top/0.xbar_error_random.2735978518
/workspace/coverage/cover_reg_top/0.xbar_random.21688919
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2609678647
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.4128314616
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.4277416114
/workspace/coverage/cover_reg_top/0.xbar_same_source.1821092336
/workspace/coverage/cover_reg_top/0.xbar_smoke.542153982
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.4247531618
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2269344921
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.4043930541
/workspace/coverage/cover_reg_top/0.xbar_stress_all.1536586124
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.70657318
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.74975480
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3874712989
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3872729523
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.4280535443
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3164297876
/workspace/coverage/cover_reg_top/1.chip_csr_rw.4209241142
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.823317539
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1739099785
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.2616933423
/workspace/coverage/cover_reg_top/1.chip_tl_errors.3213055646
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.4161850884
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1018206865
/workspace/coverage/cover_reg_top/1.xbar_error_random.2380594331
/workspace/coverage/cover_reg_top/1.xbar_random.3586549837
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2701078532
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1448752945
/workspace/coverage/cover_reg_top/1.xbar_same_source.32082394
/workspace/coverage/cover_reg_top/1.xbar_smoke.1199664348
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1795699408
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.319895070
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.728280004
/workspace/coverage/cover_reg_top/1.xbar_stress_all.2924348109
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.688008209
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2274006275
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2985936922
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.108094221
/workspace/coverage/cover_reg_top/10.chip_csr_rw.368575357
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2690225130
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.531142183
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1207237248
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2115131924
/workspace/coverage/cover_reg_top/10.xbar_error_random.4203496753
/workspace/coverage/cover_reg_top/10.xbar_random.423685474
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3119153787
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1314852862
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1784984416
/workspace/coverage/cover_reg_top/10.xbar_same_source.1059130122
/workspace/coverage/cover_reg_top/10.xbar_smoke.2635710175
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.973743026
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2202839633
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2612547205
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3645420746
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.851184152
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.4248310040
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.3931964540
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.2541489905
/workspace/coverage/cover_reg_top/11.chip_csr_rw.78018898
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.1674443373
/workspace/coverage/cover_reg_top/11.chip_tl_errors.2062633831
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.4119134447
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2909655492
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3992873065
/workspace/coverage/cover_reg_top/11.xbar_error_random.1978668021
/workspace/coverage/cover_reg_top/11.xbar_random.2784707634
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3958364304
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.790642332
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3408302010
/workspace/coverage/cover_reg_top/11.xbar_same_source.3393244577
/workspace/coverage/cover_reg_top/11.xbar_smoke.1963036322
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.920098164
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.953963167
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.324528602
/workspace/coverage/cover_reg_top/11.xbar_stress_all.3261584794
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1487959430
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1439638060
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1155661724
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.2763398402
/workspace/coverage/cover_reg_top/12.chip_csr_rw.20253863
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3068684097
/workspace/coverage/cover_reg_top/12.chip_tl_errors.4068187846
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.3287441129
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3962319758
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2808480741
/workspace/coverage/cover_reg_top/12.xbar_error_random.1714236536
/workspace/coverage/cover_reg_top/12.xbar_random.142902815
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3995004443
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2907393327
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1735867461
/workspace/coverage/cover_reg_top/12.xbar_same_source.3789973449
/workspace/coverage/cover_reg_top/12.xbar_smoke.3497414616
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2843354264
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3042539990
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.240515323
/workspace/coverage/cover_reg_top/12.xbar_stress_all.3341992230
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.510985513
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.53013431
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1196206607
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.4130035602
/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.3889413287
/workspace/coverage/cover_reg_top/13.chip_csr_rw.423470569
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.1059850101
/workspace/coverage/cover_reg_top/13.chip_tl_errors.1223909739
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.3373308580
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2456806309
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3252216888
/workspace/coverage/cover_reg_top/13.xbar_error_random.2544219377
/workspace/coverage/cover_reg_top/13.xbar_random.761397078
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1949196136
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2607118305
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.870511493
/workspace/coverage/cover_reg_top/13.xbar_same_source.4031710573
/workspace/coverage/cover_reg_top/13.xbar_smoke.4069116592
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2999619040
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.2805813044
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3267949003
/workspace/coverage/cover_reg_top/13.xbar_stress_all.3801569786
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.2951016569
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3577724135
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.904787579
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.599770792
/workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.2493843762
/workspace/coverage/cover_reg_top/14.chip_csr_rw.2029378493
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.3531818645
/workspace/coverage/cover_reg_top/14.chip_tl_errors.472948375
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.3074777908
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1941800782
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.1068677871
/workspace/coverage/cover_reg_top/14.xbar_error_random.932044153
/workspace/coverage/cover_reg_top/14.xbar_random.2536610481
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.1853174780
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.875387017
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.780161948
/workspace/coverage/cover_reg_top/14.xbar_same_source.2064874418
/workspace/coverage/cover_reg_top/14.xbar_smoke.749018171
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.280278380
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.2869981548
/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.2455077316
/workspace/coverage/cover_reg_top/14.xbar_stress_all.4241456768
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.3506173440
/workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.2257042315
/workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.1288952324
/workspace/coverage/cover_reg_top/15.chip_csr_rw.939454791
/workspace/coverage/cover_reg_top/15.chip_tl_errors.1927720084
/workspace/coverage/cover_reg_top/15.xbar_access_same_device.3424854048
/workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.27820401
/workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.4113139866
/workspace/coverage/cover_reg_top/15.xbar_error_random.1919476430
/workspace/coverage/cover_reg_top/15.xbar_random.874283570
/workspace/coverage/cover_reg_top/15.xbar_random_large_delays.784718694
/workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.3131963814
/workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.3385560277
/workspace/coverage/cover_reg_top/15.xbar_same_source.2981901643
/workspace/coverage/cover_reg_top/15.xbar_smoke.1953902791
/workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.3365005252
/workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.2167192096
/workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.567123032
/workspace/coverage/cover_reg_top/15.xbar_stress_all.2632442517
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.663700248
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.3764429124
/workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.1122020403
/workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.1406812623
/workspace/coverage/cover_reg_top/16.chip_csr_rw.2078546393
/workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.1229026509
/workspace/coverage/cover_reg_top/16.chip_tl_errors.2472169492
/workspace/coverage/cover_reg_top/16.xbar_access_same_device.2929318836
/workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.4009818460
/workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.497233349
/workspace/coverage/cover_reg_top/16.xbar_error_random.3476628276
/workspace/coverage/cover_reg_top/16.xbar_random.1992329204
/workspace/coverage/cover_reg_top/16.xbar_random_large_delays.2481356256
/workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.3597598168
/workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.3994287051
/workspace/coverage/cover_reg_top/16.xbar_same_source.3560758434
/workspace/coverage/cover_reg_top/16.xbar_smoke.1523912756
/workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.3639837728
/workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.4270923250
/workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.3102786739
/workspace/coverage/cover_reg_top/16.xbar_stress_all.3313538771
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.1074491542
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.2553180168
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.2497720767
/workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.1005014678
/workspace/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.851155078
/workspace/coverage/cover_reg_top/17.chip_csr_rw.586250739
/workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.2847895034
/workspace/coverage/cover_reg_top/17.chip_tl_errors.1794730760
/workspace/coverage/cover_reg_top/17.xbar_access_same_device.4240698290
/workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.589562212
/workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.1392415429
/workspace/coverage/cover_reg_top/17.xbar_error_random.3754746079
/workspace/coverage/cover_reg_top/17.xbar_random.2571483699
/workspace/coverage/cover_reg_top/17.xbar_random_large_delays.1916083253
/workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.820509127
/workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.3101306534
/workspace/coverage/cover_reg_top/17.xbar_same_source.3499392728
/workspace/coverage/cover_reg_top/17.xbar_smoke.2399273366
/workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.233103792
/workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.147125495
/workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.1023027015
/workspace/coverage/cover_reg_top/17.xbar_stress_all.2770726163
/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.1909809995
/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.2169882359
/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.881504643
/workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.1882781571
/workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.1019183078
/workspace/coverage/cover_reg_top/18.chip_csr_rw.3908327768
/workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.1820057037
/workspace/coverage/cover_reg_top/18.chip_tl_errors.3098451975
/workspace/coverage/cover_reg_top/18.xbar_access_same_device.445101749
/workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.2487924163
/workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.2473174816
/workspace/coverage/cover_reg_top/18.xbar_error_random.344236026
/workspace/coverage/cover_reg_top/18.xbar_random.2732315822
/workspace/coverage/cover_reg_top/18.xbar_random_large_delays.1931060187
/workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.1894810564
/workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.3302574034
/workspace/coverage/cover_reg_top/18.xbar_same_source.3958234990
/workspace/coverage/cover_reg_top/18.xbar_smoke.3882714446
/workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.440870847
/workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.2354519946
/workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.2666012295
/workspace/coverage/cover_reg_top/18.xbar_stress_all.3015843729
/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.1288256578
/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.378167324
/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.2928600015
/workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.3753621258
/workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.4002866872
/workspace/coverage/cover_reg_top/19.chip_csr_rw.2730683775
/workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.165700642
/workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.1695706163
/workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.453015835
/workspace/coverage/cover_reg_top/19.xbar_error_random.3647126976
/workspace/coverage/cover_reg_top/19.xbar_random.4178076284
/workspace/coverage/cover_reg_top/19.xbar_random_large_delays.2083256437
/workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.1517105539
/workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.2094886482
/workspace/coverage/cover_reg_top/19.xbar_same_source.2350471192
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/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1463852694
/workspace/coverage/default/40.chip_sw_all_escalation_resets.257731164
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2769233475
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3010986621
/workspace/coverage/default/43.chip_sw_all_escalation_resets.1326916209
/workspace/coverage/default/44.chip_sw_all_escalation_resets.561539210
/workspace/coverage/default/45.chip_sw_all_escalation_resets.2246098251
/workspace/coverage/default/46.chip_sw_all_escalation_resets.3516686594
/workspace/coverage/default/47.chip_sw_all_escalation_resets.3295066957
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.459822646
/workspace/coverage/default/49.chip_sw_all_escalation_resets.2547921788
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1520270293
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2539324735
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1768372113
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2591837382
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1519323042
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.2441341334
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.704769192
/workspace/coverage/default/50.chip_sw_all_escalation_resets.3043701126
/workspace/coverage/default/51.chip_sw_all_escalation_resets.3657734853
/workspace/coverage/default/52.chip_sw_all_escalation_resets.1948990544
/workspace/coverage/default/53.chip_sw_all_escalation_resets.1490952368
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3001543232
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3447310315
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3859362968
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2931960891
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3552206452
/workspace/coverage/default/58.chip_sw_all_escalation_resets.719776584
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.828804521
/workspace/coverage/default/59.chip_sw_all_escalation_resets.130003813
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1579531430
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1562848825
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.932136873
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2454036173
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3460688983
/workspace/coverage/default/61.chip_sw_all_escalation_resets.3686377173
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.869446121
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3982228354
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.4152032983
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2455163096
/workspace/coverage/default/67.chip_sw_all_escalation_resets.2068912927
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2725672110
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.4194959650
/workspace/coverage/default/69.chip_sw_all_escalation_resets.3377873322
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3658134656
/workspace/coverage/default/7.chip_sw_all_escalation_resets.4266520473
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3858384600
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1416449461
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.439343643
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.4279727299
/workspace/coverage/default/70.chip_sw_all_escalation_resets.3606090643
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2862196173
/workspace/coverage/default/71.chip_sw_all_escalation_resets.1657303505
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1809745559
/workspace/coverage/default/72.chip_sw_all_escalation_resets.949962063
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3021346348
/workspace/coverage/default/73.chip_sw_all_escalation_resets.2729227796
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3491705263
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1667787655
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2917349181
/workspace/coverage/default/75.chip_sw_all_escalation_resets.2142437256
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3318979652
/workspace/coverage/default/76.chip_sw_all_escalation_resets.1277025411
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.4120578479
/workspace/coverage/default/77.chip_sw_all_escalation_resets.2404725847
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.922951640
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1019306677
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3068031982
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2879928341
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2962417308
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.930323361
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1308492754
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.526759493
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2767300552
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1408579053
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2278073634
/workspace/coverage/default/81.chip_sw_all_escalation_resets.3246697595
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.4242544580
/workspace/coverage/default/82.chip_sw_all_escalation_resets.6246501
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2587599747
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2383175367
/workspace/coverage/default/84.chip_sw_all_escalation_resets.3865842241
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2536594636
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2562002077
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1785248491
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3950900378
/workspace/coverage/default/87.chip_sw_all_escalation_resets.1716763247
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3483759658
/workspace/coverage/default/88.chip_sw_all_escalation_resets.323661837
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1219828690
/workspace/coverage/default/89.chip_sw_all_escalation_resets.2255936540
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1066894640
/workspace/coverage/default/9.chip_sw_all_escalation_resets.1207482096
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.836559491
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1749035998
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3592369239
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2418515949
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2523709184
/workspace/coverage/default/92.chip_sw_all_escalation_resets.811384292
/workspace/coverage/default/93.chip_sw_all_escalation_resets.3882108614
/workspace/coverage/default/94.chip_sw_all_escalation_resets.1189282362
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2161887463
/workspace/coverage/default/96.chip_sw_all_escalation_resets.2435459882
/workspace/coverage/default/97.chip_sw_all_escalation_resets.145449058
/workspace/coverage/default/98.chip_sw_all_escalation_resets.3060219978
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1452800166
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.747808695
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.4039200814
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.264792659
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.4027032859
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.268207362
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2860518876
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1140481835



Total test records in report: 2932
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html | tests61.html | tests62.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1077240967 Jul 20 08:01:03 PM PDT 24 Jul 20 09:47:34 PM PDT 24 23969747456 ps
T5 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2517199882 Jul 20 07:50:55 PM PDT 24 Jul 20 07:58:55 PM PDT 24 4470823450 ps
T6 /workspace/coverage/default/1.chip_tap_straps_prod.4226135809 Jul 20 08:03:11 PM PDT 24 Jul 20 08:06:08 PM PDT 24 2758885093 ps
T17 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2730631347 Jul 20 08:00:23 PM PDT 24 Jul 20 08:10:11 PM PDT 24 4414983156 ps
T60 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2741379636 Jul 20 07:58:42 PM PDT 24 Jul 20 08:02:29 PM PDT 24 3104682770 ps
T18 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3897645736 Jul 20 08:00:34 PM PDT 24 Jul 20 08:09:23 PM PDT 24 4113873944 ps
T41 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3708002180 Jul 20 08:09:27 PM PDT 24 Jul 20 08:17:42 PM PDT 24 6275140252 ps
T42 /workspace/coverage/default/33.chip_sw_all_escalation_resets.2595161287 Jul 20 08:21:47 PM PDT 24 Jul 20 08:31:43 PM PDT 24 5181778044 ps
T59 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.4050545524 Jul 20 07:57:18 PM PDT 24 Jul 20 08:05:17 PM PDT 24 7134670728 ps
T19 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3958901292 Jul 20 08:18:24 PM PDT 24 Jul 20 08:27:03 PM PDT 24 7443114752 ps
T20 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2672817462 Jul 20 08:08:58 PM PDT 24 Jul 20 09:05:22 PM PDT 24 14831776330 ps
T124 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2534682933 Jul 20 08:10:33 PM PDT 24 Jul 20 08:14:49 PM PDT 24 2751959000 ps
T54 /workspace/coverage/default/0.chip_tap_straps_prod.2734349218 Jul 20 07:53:10 PM PDT 24 Jul 20 07:56:32 PM PDT 24 2667506797 ps
T209 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2229977943 Jul 20 08:17:41 PM PDT 24 Jul 20 08:24:52 PM PDT 24 3466257954 ps
T125 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2149265762 Jul 20 08:16:10 PM PDT 24 Jul 20 08:24:32 PM PDT 24 3426172298 ps
T63 /workspace/coverage/default/56.chip_sw_all_escalation_resets.1962853788 Jul 20 08:26:16 PM PDT 24 Jul 20 08:36:06 PM PDT 24 4087849200 ps
T52 /workspace/coverage/default/2.rom_e2e_asm_init_dev.1936321531 Jul 20 08:18:20 PM PDT 24 Jul 20 09:17:32 PM PDT 24 14855989366 ps
T21 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.199129288 Jul 20 07:56:25 PM PDT 24 Jul 20 09:34:36 PM PDT 24 23326454115 ps
T172 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1577106535 Jul 20 07:58:36 PM PDT 24 Jul 20 08:55:58 PM PDT 24 11431055956 ps
T29 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.1926176501 Jul 20 07:49:00 PM PDT 24 Jul 20 09:41:22 PM PDT 24 31306497624 ps
T188 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.2496195252 Jul 20 08:12:31 PM PDT 24 Jul 20 08:22:23 PM PDT 24 9019515790 ps
T64 /workspace/coverage/default/68.chip_sw_all_escalation_resets.2722889560 Jul 20 08:25:11 PM PDT 24 Jul 20 08:33:06 PM PDT 24 5783522100 ps
T301 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1889576734 Jul 20 08:22:01 PM PDT 24 Jul 20 08:28:21 PM PDT 24 4025117790 ps
T225 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3726913370 Jul 20 08:09:51 PM PDT 24 Jul 20 08:22:10 PM PDT 24 5371544824 ps
T302 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.377623464 Jul 20 08:02:02 PM PDT 24 Jul 20 08:09:36 PM PDT 24 4543899220 ps
T303 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1870878297 Jul 20 07:57:58 PM PDT 24 Jul 20 08:58:24 PM PDT 24 15976788692 ps
T178 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.273220633 Jul 20 07:57:01 PM PDT 24 Jul 20 08:32:36 PM PDT 24 12338106586 ps
T155 /workspace/coverage/default/2.rom_keymgr_functest.2675824358 Jul 20 08:14:02 PM PDT 24 Jul 20 08:22:43 PM PDT 24 4421860400 ps
T304 /workspace/coverage/default/0.chip_sw_kmac_entropy.969952843 Jul 20 07:49:17 PM PDT 24 Jul 20 07:55:23 PM PDT 24 3352191816 ps
T112 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.225909748 Jul 20 08:04:06 PM PDT 24 Jul 20 09:05:44 PM PDT 24 25232139433 ps
T51 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1986793368 Jul 20 07:56:10 PM PDT 24 Jul 20 08:42:18 PM PDT 24 10518831540 ps
T428 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.1025205354 Jul 20 08:03:29 PM PDT 24 Jul 20 08:09:03 PM PDT 24 3367724776 ps
T768 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2327191286 Jul 20 08:24:08 PM PDT 24 Jul 20 08:31:19 PM PDT 24 3534934770 ps
T113 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3048308534 Jul 20 08:09:00 PM PDT 24 Jul 20 08:19:09 PM PDT 24 6556088584 ps
T269 /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.3936521955 Jul 20 08:17:13 PM PDT 24 Jul 20 09:21:25 PM PDT 24 17066144348 ps
T115 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1895282247 Jul 20 08:03:14 PM PDT 24 Jul 20 08:06:41 PM PDT 24 2541582204 ps
T444 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.264290684 Jul 20 08:13:39 PM PDT 24 Jul 20 08:22:15 PM PDT 24 6689915577 ps
T173 /workspace/coverage/default/0.rom_e2e_shutdown_output.260765937 Jul 20 07:58:31 PM PDT 24 Jul 20 09:01:55 PM PDT 24 27832468020 ps
T414 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1206992293 Jul 20 08:07:18 PM PDT 24 Jul 20 08:27:41 PM PDT 24 6125819154 ps
T698 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2714686220 Jul 20 08:22:29 PM PDT 24 Jul 20 08:29:14 PM PDT 24 3226956288 ps
T171 /workspace/coverage/default/42.chip_sw_all_escalation_resets.377565272 Jul 20 08:21:39 PM PDT 24 Jul 20 08:31:26 PM PDT 24 4598178222 ps
T198 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1968626025 Jul 20 08:07:52 PM PDT 24 Jul 20 08:19:47 PM PDT 24 4053045658 ps
T732 /workspace/coverage/default/2.chip_sw_aes_idle.1703326566 Jul 20 08:09:35 PM PDT 24 Jul 20 08:15:09 PM PDT 24 3520378856 ps
T271 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1477531481 Jul 20 07:57:22 PM PDT 24 Jul 20 08:15:21 PM PDT 24 5986097192 ps
T1 /workspace/coverage/default/0.chip_jtag_csr_rw.3362936665 Jul 20 07:43:34 PM PDT 24 Jul 20 08:08:36 PM PDT 24 14529222165 ps
T377 /workspace/coverage/default/0.chip_sw_aes_enc.1703738062 Jul 20 07:51:42 PM PDT 24 Jul 20 07:57:30 PM PDT 24 2844048886 ps
T150 /workspace/coverage/default/2.chip_sw_power_idle_load.3143441818 Jul 20 08:15:41 PM PDT 24 Jul 20 08:27:29 PM PDT 24 4914864740 ps
T127 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1748992518 Jul 20 08:08:07 PM PDT 24 Jul 20 08:16:33 PM PDT 24 10191514067 ps
T222 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2705433390 Jul 20 08:10:51 PM PDT 24 Jul 20 08:40:15 PM PDT 24 7829897064 ps
T226 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.4055179313 Jul 20 07:55:51 PM PDT 24 Jul 20 08:05:07 PM PDT 24 3672975334 ps
T68 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.4125912812 Jul 20 07:51:02 PM PDT 24 Jul 20 07:56:45 PM PDT 24 6271757280 ps
T179 /workspace/coverage/default/0.chip_sw_flash_init.2166056586 Jul 20 07:48:28 PM PDT 24 Jul 20 08:30:55 PM PDT 24 19994899016 ps
T62 /workspace/coverage/default/2.rom_volatile_raw_unlock.2904906973 Jul 20 08:15:00 PM PDT 24 Jul 20 08:16:43 PM PDT 24 2219627049 ps
T156 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.3673429698 Jul 20 07:50:22 PM PDT 24 Jul 20 07:56:15 PM PDT 24 3414260303 ps
T148 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.526759493 Jul 20 08:18:28 PM PDT 24 Jul 20 08:26:48 PM PDT 24 4275462648 ps
T401 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.13945628 Jul 20 08:24:53 PM PDT 24 Jul 20 08:31:22 PM PDT 24 3895513642 ps
T374 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3447310315 Jul 20 08:22:44 PM PDT 24 Jul 20 08:29:58 PM PDT 24 3632263548 ps
T751 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1604906716 Jul 20 07:52:45 PM PDT 24 Jul 20 08:00:01 PM PDT 24 4673710900 ps
T174 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.169908574 Jul 20 07:58:33 PM PDT 24 Jul 20 09:10:37 PM PDT 24 18230277500 ps
T699 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2862196173 Jul 20 08:25:36 PM PDT 24 Jul 20 08:31:50 PM PDT 24 4179393024 ps
T61 /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1433821828 Jul 20 07:52:30 PM PDT 24 Jul 20 08:00:37 PM PDT 24 4144237510 ps
T2 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.761739406 Jul 20 07:49:07 PM PDT 24 Jul 20 07:55:55 PM PDT 24 3595516880 ps
T25 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.1901860648 Jul 20 07:49:51 PM PDT 24 Jul 20 07:57:45 PM PDT 24 5556565031 ps
T101 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3215534080 Jul 20 08:11:11 PM PDT 24 Jul 20 08:20:58 PM PDT 24 3786423172 ps
T53 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2682114488 Jul 20 08:16:25 PM PDT 24 Jul 20 08:29:04 PM PDT 24 11045238781 ps
T102 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1738637703 Jul 20 07:54:39 PM PDT 24 Jul 20 08:13:02 PM PDT 24 5472814677 ps
T103 /workspace/coverage/default/2.chip_sw_aes_enc.1823754907 Jul 20 08:12:44 PM PDT 24 Jul 20 08:19:56 PM PDT 24 2876550790 ps
T104 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3343087098 Jul 20 08:05:53 PM PDT 24 Jul 20 08:10:37 PM PDT 24 3087144870 ps
T105 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.2468363150 Jul 20 07:55:35 PM PDT 24 Jul 20 08:11:11 PM PDT 24 5974350180 ps
T106 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.4129768123 Jul 20 08:14:54 PM PDT 24 Jul 20 08:19:03 PM PDT 24 2536711504 ps
T107 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3855730872 Jul 20 07:57:41 PM PDT 24 Jul 20 09:07:29 PM PDT 24 15841333446 ps
T162 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.862317553 Jul 20 07:56:00 PM PDT 24 Jul 20 08:26:40 PM PDT 24 12400891974 ps
T284 /workspace/coverage/default/9.chip_sw_all_escalation_resets.1207482096 Jul 20 08:19:29 PM PDT 24 Jul 20 08:30:31 PM PDT 24 5241404878 ps
T285 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1952500919 Jul 20 08:21:58 PM PDT 24 Jul 20 08:28:59 PM PDT 24 3262814488 ps
T85 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.4070110845 Jul 20 08:00:54 PM PDT 24 Jul 20 11:41:12 PM PDT 24 78050669079 ps
T72 /workspace/coverage/default/3.chip_tap_straps_dev.3262398266 Jul 20 08:15:45 PM PDT 24 Jul 20 08:34:20 PM PDT 24 8683227186 ps
T286 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.16071900 Jul 20 08:14:33 PM PDT 24 Jul 20 08:27:01 PM PDT 24 4872487320 ps
T287 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2413620631 Jul 20 07:56:23 PM PDT 24 Jul 20 08:33:37 PM PDT 24 21586959899 ps
T116 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1324562086 Jul 20 08:01:34 PM PDT 24 Jul 20 08:12:20 PM PDT 24 4124936214 ps
T296 /workspace/coverage/default/0.chip_sw_otbn_randomness.50079594 Jul 20 07:51:31 PM PDT 24 Jul 20 08:10:10 PM PDT 24 5660348856 ps
T261 /workspace/coverage/default/0.chip_sw_plic_sw_irq.2918929083 Jul 20 07:54:31 PM PDT 24 Jul 20 07:59:44 PM PDT 24 2969583808 ps
T297 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4157368361 Jul 20 08:01:20 PM PDT 24 Jul 20 08:56:05 PM PDT 24 25584793840 ps
T73 /workspace/coverage/default/2.chip_tap_straps_dev.3284375253 Jul 20 08:11:54 PM PDT 24 Jul 20 08:32:33 PM PDT 24 11453726809 ps
T149 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.1921969817 Jul 20 08:16:04 PM PDT 24 Jul 20 08:57:19 PM PDT 24 13128343400 ps
T232 /workspace/coverage/default/51.chip_sw_all_escalation_resets.3657734853 Jul 20 08:24:28 PM PDT 24 Jul 20 08:34:15 PM PDT 24 5076039064 ps
T298 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.2237450154 Jul 20 08:03:07 PM PDT 24 Jul 20 08:27:05 PM PDT 24 7180999220 ps
T208 /workspace/coverage/default/1.chip_tap_straps_dev.4258519249 Jul 20 08:01:58 PM PDT 24 Jul 20 08:04:10 PM PDT 24 2916823610 ps
T228 /workspace/coverage/default/4.chip_sw_uart_tx_rx.3888357890 Jul 20 08:16:19 PM PDT 24 Jul 20 08:27:28 PM PDT 24 4024326510 ps
T119 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.676592701 Jul 20 08:15:23 PM PDT 24 Jul 20 08:40:59 PM PDT 24 7834168498 ps
T31 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3857653090 Jul 20 07:54:34 PM PDT 24 Jul 20 08:00:58 PM PDT 24 3303039024 ps
T928 /workspace/coverage/default/2.chip_sw_csrng_kat_test.296583302 Jul 20 08:10:12 PM PDT 24 Jul 20 08:14:52 PM PDT 24 3019882280 ps
T734 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.837475180 Jul 20 08:21:14 PM PDT 24 Jul 20 08:26:33 PM PDT 24 4101668920 ps
T331 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1400280339 Jul 20 07:56:37 PM PDT 24 Jul 20 08:07:28 PM PDT 24 4792521730 ps
T190 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3578202040 Jul 20 08:02:48 PM PDT 24 Jul 20 08:08:15 PM PDT 24 2738505608 ps
T229 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2439317437 Jul 20 08:02:15 PM PDT 24 Jul 20 08:23:10 PM PDT 24 6965301592 ps
T308 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1295017242 Jul 20 08:21:00 PM PDT 24 Jul 20 08:26:53 PM PDT 24 3933960520 ps
T309 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3702846359 Jul 20 07:49:29 PM PDT 24 Jul 20 07:55:47 PM PDT 24 5762447680 ps
T310 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.4289293230 Jul 20 07:57:35 PM PDT 24 Jul 20 08:03:25 PM PDT 24 3452700256 ps
T217 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3307014062 Jul 20 07:50:11 PM PDT 24 Jul 20 07:54:53 PM PDT 24 3098686602 ps
T311 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.352280774 Jul 20 08:04:09 PM PDT 24 Jul 20 08:08:32 PM PDT 24 3166822714 ps
T86 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.195145873 Jul 20 07:56:44 PM PDT 24 Jul 20 11:10:14 PM PDT 24 64294743679 ps
T270 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.241705153 Jul 20 08:20:15 PM PDT 24 Jul 20 10:02:55 PM PDT 24 27794461624 ps
T230 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.4090986180 Jul 20 07:55:18 PM PDT 24 Jul 20 08:15:43 PM PDT 24 7524372844 ps
T339 /workspace/coverage/default/2.chip_sw_uart_tx_rx.3824563161 Jul 20 08:05:51 PM PDT 24 Jul 20 08:16:13 PM PDT 24 4164122954 ps
T26 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.785298749 Jul 20 07:48:46 PM PDT 24 Jul 20 07:54:29 PM PDT 24 2830084360 ps
T32 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2767946661 Jul 20 07:58:40 PM PDT 24 Jul 20 08:53:43 PM PDT 24 20010652350 ps
T929 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.674476181 Jul 20 08:19:46 PM PDT 24 Jul 20 09:17:23 PM PDT 24 15121502048 ps
T65 /workspace/coverage/default/4.chip_tap_straps_rma.2832432605 Jul 20 08:17:24 PM PDT 24 Jul 20 08:22:41 PM PDT 24 3752313344 ps
T199 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.206442360 Jul 20 08:03:56 PM PDT 24 Jul 20 08:13:13 PM PDT 24 6589647400 ps
T733 /workspace/coverage/default/13.chip_sw_all_escalation_resets.1509022320 Jul 20 08:17:58 PM PDT 24 Jul 20 08:29:06 PM PDT 24 5705560182 ps
T170 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.589807003 Jul 20 08:00:16 PM PDT 24 Jul 20 08:02:14 PM PDT 24 2738793447 ps
T740 /workspace/coverage/default/1.chip_sw_hmac_smoketest.370588666 Jul 20 08:05:19 PM PDT 24 Jul 20 08:11:07 PM PDT 24 3244040000 ps
T930 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2537642898 Jul 20 07:49:09 PM PDT 24 Jul 20 07:58:55 PM PDT 24 3904018552 ps
T411 /workspace/coverage/default/17.chip_sw_all_escalation_resets.739452230 Jul 20 08:20:04 PM PDT 24 Jul 20 08:30:23 PM PDT 24 4274742688 ps
T365 /workspace/coverage/default/81.chip_sw_all_escalation_resets.3246697595 Jul 20 08:24:45 PM PDT 24 Jul 20 08:33:58 PM PDT 24 4804518712 ps
T253 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2448282977 Jul 20 08:02:05 PM PDT 24 Jul 20 08:17:03 PM PDT 24 5592465760 ps
T200 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2466393945 Jul 20 08:05:01 PM PDT 24 Jul 20 08:15:30 PM PDT 24 5298570686 ps
T547 /workspace/coverage/default/62.chip_sw_all_escalation_resets.1141033913 Jul 20 08:25:26 PM PDT 24 Jul 20 08:33:59 PM PDT 24 5418531088 ps
T931 /workspace/coverage/default/1.chip_sw_example_flash.1524308801 Jul 20 07:59:24 PM PDT 24 Jul 20 08:02:43 PM PDT 24 2939418772 ps
T932 /workspace/coverage/default/0.chip_sw_example_manufacturer.2370222498 Jul 20 07:48:05 PM PDT 24 Jul 20 07:51:41 PM PDT 24 2849594648 ps
T434 /workspace/coverage/default/2.chip_sw_kmac_smoketest.241743665 Jul 20 08:15:04 PM PDT 24 Jul 20 08:21:10 PM PDT 24 3276271680 ps
T825 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1066894640 Jul 20 08:19:24 PM PDT 24 Jul 20 08:25:39 PM PDT 24 3722864808 ps
T400 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.4196691716 Jul 20 07:50:14 PM PDT 24 Jul 20 07:55:26 PM PDT 24 2535101100 ps
T66 /workspace/coverage/default/2.chip_tap_straps_testunlock0.1411998834 Jul 20 08:12:18 PM PDT 24 Jul 20 08:16:02 PM PDT 24 2634332771 ps
T933 /workspace/coverage/default/1.chip_sw_example_concurrency.1976045993 Jul 20 07:55:53 PM PDT 24 Jul 20 08:00:29 PM PDT 24 3071402360 ps
T22 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.407977462 Jul 20 07:59:05 PM PDT 24 Jul 20 08:04:04 PM PDT 24 2875156621 ps
T412 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3491705263 Jul 20 08:25:31 PM PDT 24 Jul 20 08:32:01 PM PDT 24 3857829910 ps
T117 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.600098972 Jul 20 08:13:18 PM PDT 24 Jul 20 08:26:35 PM PDT 24 5575700282 ps
T934 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.511008428 Jul 20 07:49:33 PM PDT 24 Jul 20 08:08:41 PM PDT 24 7422287500 ps
T435 /workspace/coverage/default/1.chip_sw_kmac_smoketest.668586780 Jul 20 08:04:56 PM PDT 24 Jul 20 08:11:21 PM PDT 24 2577399952 ps
T327 /workspace/coverage/default/12.chip_sw_all_escalation_resets.767483334 Jul 20 08:18:43 PM PDT 24 Jul 20 08:28:41 PM PDT 24 4721077154 ps
T935 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2129882805 Jul 20 07:54:32 PM PDT 24 Jul 20 07:58:43 PM PDT 24 2642700448 ps
T936 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.153641908 Jul 20 08:00:00 PM PDT 24 Jul 20 09:09:47 PM PDT 24 15392878800 ps
T738 /workspace/coverage/default/45.chip_sw_all_escalation_resets.2246098251 Jul 20 08:22:39 PM PDT 24 Jul 20 08:32:13 PM PDT 24 5070438596 ps
T937 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1454036995 Jul 20 08:02:03 PM PDT 24 Jul 20 08:08:18 PM PDT 24 2541532332 ps
T48 /workspace/coverage/default/1.chip_sw_spi_device_tpm.1312048572 Jul 20 07:58:08 PM PDT 24 Jul 20 08:06:19 PM PDT 24 3844299885 ps
T749 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.4074139555 Jul 20 07:53:03 PM PDT 24 Jul 20 08:12:18 PM PDT 24 8573533160 ps
T264 /workspace/coverage/default/1.chip_sw_rv_timer_irq.904518250 Jul 20 07:58:43 PM PDT 24 Jul 20 08:03:10 PM PDT 24 2972849720 ps
T392 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.3278760841 Jul 20 08:19:11 PM PDT 24 Jul 20 09:16:21 PM PDT 24 15805993659 ps
T938 /workspace/coverage/default/0.chip_sw_example_rom.1863719421 Jul 20 07:48:51 PM PDT 24 Jul 20 07:50:55 PM PDT 24 2274281464 ps
T180 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2691102704 Jul 20 07:58:08 PM PDT 24 Jul 20 09:00:18 PM PDT 24 14768240756 ps
T118 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3571379056 Jul 20 07:57:16 PM PDT 24 Jul 20 08:16:53 PM PDT 24 11517032216 ps
T376 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1242663481 Jul 20 07:52:32 PM PDT 24 Jul 20 08:02:55 PM PDT 24 6348339893 ps
T353 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2005935923 Jul 20 07:54:38 PM PDT 24 Jul 20 07:58:43 PM PDT 24 2534285745 ps
T28 /workspace/coverage/default/1.chip_sw_gpio_smoketest.2466507119 Jul 20 08:08:12 PM PDT 24 Jul 20 08:13:55 PM PDT 24 3126404595 ps
T939 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.3403923366 Jul 20 08:10:59 PM PDT 24 Jul 20 08:15:02 PM PDT 24 3516256144 ps
T842 /workspace/coverage/default/46.chip_sw_all_escalation_resets.3516686594 Jul 20 08:22:20 PM PDT 24 Jul 20 08:35:24 PM PDT 24 5799938748 ps
T433 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1192750344 Jul 20 07:52:25 PM PDT 24 Jul 20 08:09:03 PM PDT 24 5396600052 ps
T349 /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2394811898 Jul 20 07:52:02 PM PDT 24 Jul 20 07:58:19 PM PDT 24 4061585832 ps
T393 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3252514900 Jul 20 08:01:19 PM PDT 24 Jul 20 08:58:25 PM PDT 24 15729410408 ps
T545 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2845897371 Jul 20 07:52:46 PM PDT 24 Jul 20 08:14:11 PM PDT 24 9371212228 ps
T120 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.399495352 Jul 20 08:06:04 PM PDT 24 Jul 20 08:17:24 PM PDT 24 4043907320 ps
T183 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.417640509 Jul 20 08:20:26 PM PDT 24 Jul 20 08:37:01 PM PDT 24 9222511138 ps
T940 /workspace/coverage/default/3.chip_sw_uart_tx_rx.1135035783 Jul 20 08:16:56 PM PDT 24 Jul 20 08:30:16 PM PDT 24 4686535746 ps
T231 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3382416996 Jul 20 07:49:06 PM PDT 24 Jul 20 08:11:09 PM PDT 24 6960143170 ps
T693 /workspace/coverage/default/0.chip_sw_aes_masking_off.2894750872 Jul 20 07:52:51 PM PDT 24 Jul 20 07:56:45 PM PDT 24 3098491324 ps
T234 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3982228354 Jul 20 08:24:17 PM PDT 24 Jul 20 08:30:51 PM PDT 24 3081755062 ps
T254 /workspace/coverage/default/63.chip_sw_all_escalation_resets.3399248686 Jul 20 08:31:03 PM PDT 24 Jul 20 08:40:02 PM PDT 24 4745985984 ps
T276 /workspace/coverage/default/89.chip_sw_all_escalation_resets.2255936540 Jul 20 08:26:46 PM PDT 24 Jul 20 08:37:16 PM PDT 24 5591358340 ps
T277 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.4279727299 Jul 20 08:22:38 PM PDT 24 Jul 20 08:28:11 PM PDT 24 3478967288 ps
T233 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.2389430575 Jul 20 08:09:15 PM PDT 24 Jul 20 08:18:35 PM PDT 24 4459454550 ps
T278 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.442780746 Jul 20 08:15:13 PM PDT 24 Jul 20 08:20:11 PM PDT 24 2853867116 ps
T279 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.814598088 Jul 20 08:16:43 PM PDT 24 Jul 20 08:22:59 PM PDT 24 5938499120 ps
T163 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.4284223348 Jul 20 08:20:55 PM PDT 24 Jul 20 08:26:44 PM PDT 24 3630377052 ps
T157 /workspace/coverage/default/1.chip_plic_all_irqs_10.986350269 Jul 20 08:02:15 PM PDT 24 Jul 20 08:13:21 PM PDT 24 3698294736 ps
T280 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.828804521 Jul 20 08:31:04 PM PDT 24 Jul 20 08:38:57 PM PDT 24 3764896420 ps
T224 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4202373662 Jul 20 08:07:26 PM PDT 24 Jul 20 08:13:44 PM PDT 24 3702237929 ps
T941 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3682366821 Jul 20 07:50:09 PM PDT 24 Jul 20 08:09:38 PM PDT 24 14021430654 ps
T942 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.2960477350 Jul 20 08:09:38 PM PDT 24 Jul 20 08:16:42 PM PDT 24 6655017983 ps
T313 /workspace/coverage/default/79.chip_sw_all_escalation_resets.2561208912 Jul 20 08:25:14 PM PDT 24 Jul 20 08:33:21 PM PDT 24 5299728196 ps
T321 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2310413715 Jul 20 08:01:44 PM PDT 24 Jul 20 09:14:10 PM PDT 24 15055334160 ps
T322 /workspace/coverage/default/1.chip_plic_all_irqs_0.129135832 Jul 20 08:02:11 PM PDT 24 Jul 20 08:26:13 PM PDT 24 5879058154 ps
T181 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.495268168 Jul 20 08:08:10 PM PDT 24 Jul 20 09:32:58 PM PDT 24 48702135766 ps
T323 /workspace/coverage/default/2.rom_e2e_smoke.4176939096 Jul 20 08:19:31 PM PDT 24 Jul 20 09:15:59 PM PDT 24 15712495160 ps
T324 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1431572953 Jul 20 08:07:01 PM PDT 24 Jul 20 08:13:27 PM PDT 24 3512681888 ps
T325 /workspace/coverage/default/1.rom_e2e_smoke.4283227646 Jul 20 08:11:27 PM PDT 24 Jul 20 09:07:25 PM PDT 24 14987834674 ps
T69 /workspace/coverage/default/0.chip_tap_straps_testunlock0.3389890398 Jul 20 07:49:58 PM PDT 24 Jul 20 08:03:01 PM PDT 24 7934003707 ps
T326 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2352862988 Jul 20 08:07:55 PM PDT 24 Jul 20 08:23:34 PM PDT 24 6072801763 ps
T236 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3522110741 Jul 20 08:21:30 PM PDT 24 Jul 20 08:29:18 PM PDT 24 3772733736 ps
T843 /workspace/coverage/default/38.chip_sw_all_escalation_resets.2787292143 Jul 20 08:22:22 PM PDT 24 Jul 20 08:35:19 PM PDT 24 6132806948 ps
T30 /workspace/coverage/default/0.chip_sw_usbdev_dpi.3888610390 Jul 20 07:55:24 PM PDT 24 Jul 20 08:42:56 PM PDT 24 12290860834 ps
T128 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.673737240 Jul 20 08:02:49 PM PDT 24 Jul 20 08:09:53 PM PDT 24 6783475200 ps
T354 /workspace/coverage/default/1.chip_sw_hmac_enc.3801594821 Jul 20 08:01:06 PM PDT 24 Jul 20 08:07:08 PM PDT 24 2730986510 ps
T108 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4155450805 Jul 20 07:52:59 PM PDT 24 Jul 20 08:01:23 PM PDT 24 18048742284 ps
T755 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.4152032983 Jul 20 08:24:22 PM PDT 24 Jul 20 08:30:19 PM PDT 24 3739470800 ps
T943 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3236726282 Jul 20 07:53:58 PM PDT 24 Jul 20 08:03:21 PM PDT 24 3558783296 ps
T944 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2718567912 Jul 20 08:08:43 PM PDT 24 Jul 20 08:13:02 PM PDT 24 2569303356 ps
T328 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3919028791 Jul 20 08:17:11 PM PDT 24 Jul 20 08:30:09 PM PDT 24 3866238344 ps
T945 /workspace/coverage/default/0.chip_sw_rv_timer_irq.2636767395 Jul 20 07:52:40 PM PDT 24 Jul 20 07:56:31 PM PDT 24 2286264320 ps
T946 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1142930790 Jul 20 07:49:04 PM PDT 24 Jul 20 08:17:36 PM PDT 24 10750644423 ps
T947 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.95595929 Jul 20 07:59:10 PM PDT 24 Jul 20 08:03:23 PM PDT 24 2978136626 ps
T114 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.214966526 Jul 20 07:51:33 PM PDT 24 Jul 20 09:01:01 PM PDT 24 24710872132 ps
T846 /workspace/coverage/default/65.chip_sw_all_escalation_resets.299691723 Jul 20 08:26:22 PM PDT 24 Jul 20 08:35:11 PM PDT 24 5998132400 ps
T754 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3010986621 Jul 20 08:24:33 PM PDT 24 Jul 20 08:31:06 PM PDT 24 3806302132 ps
T948 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.48421692 Jul 20 08:06:52 PM PDT 24 Jul 20 08:16:51 PM PDT 24 3504557390 ps
T756 /workspace/coverage/default/99.chip_sw_all_escalation_resets.2668081895 Jul 20 08:27:33 PM PDT 24 Jul 20 08:36:17 PM PDT 24 4481622302 ps
T949 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1548585372 Jul 20 08:11:03 PM PDT 24 Jul 20 08:15:04 PM PDT 24 2828589594 ps
T950 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1725705813 Jul 20 07:52:29 PM PDT 24 Jul 20 08:03:13 PM PDT 24 8269958266 ps
T344 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2808018609 Jul 20 07:59:13 PM PDT 24 Jul 20 08:10:39 PM PDT 24 4733547380 ps
T951 /workspace/coverage/default/1.chip_sw_csrng_smoketest.72130443 Jul 20 08:05:21 PM PDT 24 Jul 20 08:10:11 PM PDT 24 3131803274 ps
T826 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.154054538 Jul 20 08:21:17 PM PDT 24 Jul 20 08:26:51 PM PDT 24 3429918552 ps
T74 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.99996640 Jul 20 07:53:07 PM PDT 24 Jul 20 07:59:09 PM PDT 24 3160250095 ps
T227 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3816696977 Jul 20 08:07:19 PM PDT 24 Jul 20 08:30:52 PM PDT 24 9078000680 ps
T235 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.306560848 Jul 20 07:51:06 PM PDT 24 Jul 20 08:03:15 PM PDT 24 4666017848 ps
T373 /workspace/coverage/default/77.chip_sw_all_escalation_resets.2404725847 Jul 20 08:24:41 PM PDT 24 Jul 20 08:31:37 PM PDT 24 6014579880 ps
T406 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1472135862 Jul 20 08:01:03 PM PDT 24 Jul 20 09:50:24 PM PDT 24 23519039848 ps
T79 /workspace/coverage/default/2.chip_jtag_csr_rw.93724595 Jul 20 08:05:05 PM PDT 24 Jul 20 08:24:24 PM PDT 24 11036241100 ps
T952 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.3589903636 Jul 20 08:06:52 PM PDT 24 Jul 20 08:09:43 PM PDT 24 2150645160 ps
T375 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1954008491 Jul 20 07:49:46 PM PDT 24 Jul 20 08:15:50 PM PDT 24 6921299640 ps
T249 /workspace/coverage/default/2.chip_sw_flash_init.4281093953 Jul 20 08:06:48 PM PDT 24 Jul 20 08:44:10 PM PDT 24 25408062500 ps
T953 /workspace/coverage/default/1.chip_sw_edn_sw_mode.4063486145 Jul 20 08:00:06 PM PDT 24 Jul 20 08:31:08 PM PDT 24 7623772520 ps
T954 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3203062982 Jul 20 07:52:22 PM PDT 24 Jul 20 07:57:56 PM PDT 24 3331495592 ps
T151 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2289659469 Jul 20 07:50:07 PM PDT 24 Jul 20 09:01:27 PM PDT 24 17395761368 ps
T314 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3460688983 Jul 20 08:30:04 PM PDT 24 Jul 20 08:39:13 PM PDT 24 4010312000 ps
T368 /workspace/coverage/default/1.chip_sival_flash_info_access.1129769553 Jul 20 07:58:16 PM PDT 24 Jul 20 08:04:15 PM PDT 24 2831182760 ps
T955 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3406685403 Jul 20 07:52:43 PM PDT 24 Jul 20 08:01:15 PM PDT 24 4222947520 ps
T161 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2383175367 Jul 20 08:24:45 PM PDT 24 Jul 20 08:31:16 PM PDT 24 3630080096 ps
T735 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.295362125 Jul 20 08:19:55 PM PDT 24 Jul 20 08:26:19 PM PDT 24 3925558430 ps
T130 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2376473960 Jul 20 07:54:39 PM PDT 24 Jul 20 08:04:41 PM PDT 24 6178181536 ps
T262 /workspace/coverage/default/2.chip_sw_plic_sw_irq.891117334 Jul 20 08:11:28 PM PDT 24 Jul 20 08:16:24 PM PDT 24 3024325586 ps
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T191 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1338990255 Jul 20 08:12:19 PM PDT 24 Jul 20 08:22:35 PM PDT 24 7369436219 ps
T956 /workspace/coverage/default/4.chip_tap_straps_dev.2672164092 Jul 20 08:16:28 PM PDT 24 Jul 20 08:20:39 PM PDT 24 3338946831 ps
T410 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.615616042 Jul 20 08:07:25 PM PDT 24 Jul 20 08:12:54 PM PDT 24 3304373834 ps
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T958 /workspace/coverage/default/0.chip_sw_aon_timer_irq.2773233625 Jul 20 07:51:20 PM PDT 24 Jul 20 07:59:15 PM PDT 24 4113316404 ps
T67 /workspace/coverage/default/3.chip_tap_straps_testunlock0.3718997989 Jul 20 08:16:20 PM PDT 24 Jul 20 08:21:49 PM PDT 24 3561383126 ps
T737 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1133909260 Jul 20 07:55:51 PM PDT 24 Jul 20 08:07:17 PM PDT 24 4715074744 ps
T342 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3236536541 Jul 20 07:49:01 PM PDT 24 Jul 20 08:05:01 PM PDT 24 4503687350 ps
T959 /workspace/coverage/default/2.chip_sw_aon_timer_irq.1451094457 Jul 20 08:09:08 PM PDT 24 Jul 20 08:15:19 PM PDT 24 3860955930 ps
T237 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.610395576 Jul 20 07:56:44 PM PDT 24 Jul 20 08:21:16 PM PDT 24 8331308840 ps
T350 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3314922488 Jul 20 07:56:17 PM PDT 24 Jul 20 08:07:52 PM PDT 24 3936168130 ps
T175 /workspace/coverage/default/25.chip_sw_all_escalation_resets.1770597883 Jul 20 08:21:52 PM PDT 24 Jul 20 08:34:10 PM PDT 24 6480922688 ps
T960 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2188754059 Jul 20 07:54:02 PM PDT 24 Jul 20 08:22:35 PM PDT 24 11575696448 ps
T164 /workspace/coverage/default/5.chip_sw_all_escalation_resets.2539324735 Jul 20 08:20:26 PM PDT 24 Jul 20 08:33:41 PM PDT 24 5923667564 ps
T33 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1852509867 Jul 20 07:59:17 PM PDT 24 Jul 20 08:06:27 PM PDT 24 4109311950 ps
T251 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.2443254505 Jul 20 08:03:12 PM PDT 24 Jul 20 08:33:40 PM PDT 24 17517624434 ps
T288 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.847386734 Jul 20 08:16:39 PM PDT 24 Jul 20 08:29:49 PM PDT 24 5339126490 ps
T739 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3421405075 Jul 20 07:49:17 PM PDT 24 Jul 20 08:13:44 PM PDT 24 8751666960 ps
T43 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3741750367 Jul 20 08:06:32 PM PDT 24 Jul 20 08:13:23 PM PDT 24 2621111984 ps
T71 /workspace/coverage/default/1.chip_tap_straps_testunlock0.3895108821 Jul 20 08:02:11 PM PDT 24 Jul 20 08:13:20 PM PDT 24 7459258822 ps
T122 /workspace/coverage/default/2.chip_sw_edn_auto_mode.4015845236 Jul 20 08:09:41 PM PDT 24 Jul 20 08:51:23 PM PDT 24 6945293664 ps
T961 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3193468503 Jul 20 08:09:02 PM PDT 24 Jul 20 08:26:01 PM PDT 24 6254444066 ps
T962 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3979098741 Jul 20 08:09:55 PM PDT 24 Jul 20 08:14:24 PM PDT 24 2712629534 ps
T963 /workspace/coverage/default/0.chip_sw_aes_smoketest.2757829238 Jul 20 07:54:58 PM PDT 24 Jul 20 08:00:07 PM PDT 24 2862866908 ps
T964 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.3215315324 Jul 20 08:15:16 PM PDT 24 Jul 20 08:32:24 PM PDT 24 5593672672 ps
T184 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.2590871580 Jul 20 07:48:26 PM PDT 24 Jul 20 07:53:17 PM PDT 24 3446089422 ps
T418 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3318979652 Jul 20 08:24:38 PM PDT 24 Jul 20 08:33:27 PM PDT 24 4026918850 ps
T359 /workspace/coverage/default/2.chip_sw_flash_crash_alert.2057420880 Jul 20 08:14:37 PM PDT 24 Jul 20 08:26:06 PM PDT 24 5564125800 ps
T165 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2278073634 Jul 20 08:26:25 PM PDT 24 Jul 20 08:32:17 PM PDT 24 3404269880 ps
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