Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_host1_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	140765	1			T76	60		T77	22		T78	4
values[2]	10386	1			T76	1		T78	1		T152	4
values[3]	5081	1			T472	112		T554	55		T718	5
values[4]	2821	1			T472	67		T554	9		T872	50
values[5]	1593	1			T472	20		T872	20		T860	3
values[6]	1082	1			T472	3		T872	1		T860	2
values[7]	806	1			T472	3		T860	1		T584	4
values[8]	704	1			T860	2		T584	2		T880	13
values[9]	544	1			T860	3		T584	5		T880	10
values[10]	553	1			T860	4		T584	3		T880	3
values[11]	541	1			T860	1		T584	10		T880	24
values[12]	513	1			T860	6		T584	5		T880	4
values[13]	510	1			T860	8		T584	1		T880	8
values[14]	565	1			T860	9		T584	2		T880	18
values[15]	479	1			T860	12		T584	1		T880	5
values[16]	466	1			T860	7		T584	3		T880	6
values[17]	568	1			T860	7		T584	3		T880	5
values[18]	508	1			T860	5		T584	3		T880	11
values[19]	475	1			T860	1		T584	3		T880	4
values[20]	461	1			T860	4		T584	3		T880	22
values[21]	439	1			T860	9		T584	6		T880	7
values[22]	440	1			T860	3		T584	5		T880	16
values[23]	472	1			T860	4		T584	1		T880	12
values[24]	606	1			T860	8		T584	2		T880	10
values[25]	517	1			T860	5		T584	1		T880	12
values[26]	467	1			T860	14		T584	2		T880	5
values[27]	450	1			T860	12		T584	4		T880	5
values[28]	495	1			T860	10		T584	7		T880	9
values[29]	411	1			T860	11		T584	9		T880	8
values[30]	453	1			T860	13		T584	7		T880	10
values[31]	381	1			T860	8		T584	7		T880	22
values[32]	446	1			T860	5		T584	1		T880	5
values[33]	431	1			T860	1		T584	3		T880	6
values[34]	405	1			T860	2		T584	2		T880	11
values[35]	396	1			T860	1		T584	10		T880	13
values[36]	415	1			T860	2		T584	11		T880	25
values[37]	392	1			T860	2		T584	1		T880	11
values[38]	486	1			T860	5		T584	4		T880	16
values[39]	449	1			T860	5		T584	7		T880	9
values[40]	359	1			T860	1		T584	3		T893	31
values[41]	361	1			T860	4		T584	4		T893	36
values[42]	365	1			T860	2		T584	8		T893	19
values[43]	342	1			T860	1		T584	12		T893	27
values[44]	343	1			T860	4		T584	16		T893	27
values[45]	363	1			T860	2		T584	6		T893	18
values[46]	336	1			T860	4		T584	8		T893	14
values[47]	307	1			T860	7		T584	3		T893	11
values[48]	331	1			T860	6		T584	1		T893	10
values[49]	278	1			T860	7		T584	4		T893	7
values[50]	227	1			T860	7		T584	1		T893	6
values[51]	265	1			T860	15		T584	11		T893	9
values[52]	235	1			T860	8		T584	5		T893	22
values[53]	184	1			T860	6		T584	3		T893	3
values[54]	173	1			T860	6		T584	5		T894	4
values[55]	187	1			T860	14		T584	7		T894	4
values[56]	142	1			T860	7		T584	9		T894	7
values[57]	143	1			T860	7		T584	9		T894	6
values[58]	158	1			T860	5		T584	12		T894	27
values[59]	122	1			T860	4		T584	10		T508	4
values[60]	120	1			T860	4		T584	11		T508	1
values[61]	139	1			T860	9		T584	23		T508	2
values[62]	150	1			T860	4		T584	17		T508	7
values[63]	136	1			T860	2		T584	18		T508	6
values[64]	152	1			T860	9		T584	23		T508	9
values[65]	144	1			T860	20		T584	17		T508	9
values[66]	132	1			T860	3		T584	9		T508	5
values[67]	132	1			T860	2		T584	9		T508	2
values[68]	126	1			T860	4		T584	5		T508	8
values[69]	145	1			T860	12		T584	6		T508	4
values[70]	159	1			T860	22		T584	3		T508	14
values[71]	168	1			T860	6		T584	1		T508	34
values[72]	174	1			T860	2		T508	26		T540	1
values[73]	139	1			T860	1		T508	11		T540	1
values[74]	138	1			T860	6		T508	12		T540	1
values[75]	133	1			T860	6		T508	13		T540	1
values[76]	138	1			T860	6		T508	15		T540	1
values[77]	155	1			T860	17		T508	10		T540	1
values[78]	136	1			T860	22		T508	5		T540	1
values[79]	127	1			T860	10		T508	4		T540	1
values[80]	150	1			T860	10		T540	1		T890	1
values[81]	132	1			T860	14		T540	1		T890	1
values[82]	105	1			T860	6		T540	1		T890	1
values[83]	114	1			T540	1		T890	1		T489	1
values[84]	101	1			T540	1		T890	1		T489	1
values[85]	103	1			T540	1		T890	1		T489	1
values[86]	106	1			T540	1		T890	1		T489	1
values[87]	100	1			T540	1		T890	1		T489	1
values[88]	108	1			T540	1		T890	1		T489	1
values[89]	93	1			T540	1		T890	1		T489	1
values[90]	74	1			T540	1		T890	1		T489	1
values[91]	92	1			T540	1		T890	1		T489	1
values[92]	71	1			T540	1		T890	1		T489	1
values[93]	71	1			T540	1		T890	1		T489	1
values[94]	67	1			T540	1		T890	1		T489	1
values[95]	59	1			T540	1		T890	1		T489	1
values[96]	83	1			T540	6		T890	1		T489	1
values[97]	84	1			T540	2		T890	1		T489	1
values[98]	91	1			T540	3		T890	1		T489	1
values[99]	75	1			T540	6		T890	1		T489	1
values[100]	62	1			T540	4		T890	1		T489	1
values[101]	72	1			T540	4		T890	1		T489	1
values[102]	64	1			T540	5		T890	1		T489	1
values[103]	70	1			T540	6		T890	1		T489	1
values[104]	62	1			T540	2		T890	1		T489	1
values[105]	65	1			T540	3		T890	1		T489	1
values[106]	49	1			T540	4		T890	1		T489	1
values[107]	56	1			T540	3		T890	1		T489	1
values[108]	51	1			T540	1		T890	1		T489	1
values[109]	59	1			T540	5		T890	1		T489	1
values[110]	50	1			T540	1		T890	1		T489	1
values[111]	41	1			T540	2		T890	1		T489	1
values[112]	40	1			T540	1		T890	1		T489	1
values[113]	37	1			T540	1		T890	2		T489	1
values[114]	55	1			T540	4		T890	4		T489	1
values[115]	42	1			T540	1		T890	2		T489	2
values[116]	47	1			T540	1		T890	2		T489	5
values[117]	59	1			T540	1		T890	1		T489	2
values[118]	56	1			T540	1		T890	1		T489	12
values[119]	42	1			T540	1		T890	1		T489	7
values[120]	35	1			T540	2		T890	2		T489	1
values[121]	39	1			T540	3		T890	1		T489	6
values[122]	36	1			T540	1		T890	1		T489	3
values[123]	51	1			T540	5		T890	2		T489	2
values[124]	50	1			T540	1		T890	8		T489	2
values[125]	38	1			T540	1		T890	5		T489	3
values[126]	91	1			T540	5		T890	4		T489	10
values[127]	1211	1			T540	43		T890	56		T489	59
values[128]	5886	1			T540	228		T890	263		T489	287