Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	465	1			T443	3		T472	2		T757	1
all_values[1]	463	1			T878	6		T503	5		T710	4
all_values[2]	439	1			T126	1		T443	3		T472	1
all_values[3]	469	1			T443	3		T554	1		T441	1
all_values[4]	449	1			T443	2		T472	2		T554	2
all_values[5]	465	1			T472	2		T554	2		T878	2
all_values[6]	446	1			T443	1		T757	1		T758	3
all_values[7]	490	1			T126	1		T443	1		T855	1
all_values[8]	478	1			T443	2		T554	2		T757	1
all_values[9]	479	1			T126	1		T443	2		T554	1
all_values[10]	464	1			T126	1		T758	1		T878	2
all_values[11]	443	1			T126	1		T443	2		T554	3
all_values[12]	475	1			T443	1		T857	1		T758	4
all_values[13]	482	1			T443	6		T554	1		T758	4
all_values[14]	481	1			T126	1		T443	2		T758	2
all_values[15]	478	1			T443	3		T554	1		T758	2
all_values[16]	500	1			T443	4		T554	1		T758	3
all_values[17]	485	1			T443	2		T554	3		T758	1
all_values[18]	493	1			T443	2		T857	1		T554	1
all_values[19]	442	1			T443	3		T472	1		T554	2
all_values[20]	447	1			T443	3		T554	1		T758	1
all_values[21]	454	1			T443	1		T554	1		T757	1
all_values[22]	458	1			T443	1		T441	1		T758	3
all_values[23]	488	1			T443	2		T554	1		T757	1
all_values[24]	431	1			T443	1		T472	1		T554	1
all_values[25]	487	1			T443	3		T854	1		T857	1
all_values[26]	461	1			T126	1		T443	3		T857	1
all_values[27]	486	1			T443	2		T441	1		T758	3
all_values[28]	459	1			T443	2		T554	2		T758	2
all_values[29]	482	1			T443	6		T554	1		T758	3
all_values[30]	463	1			T443	5		T472	1		T857	1
all_values[31]	435	1			T126	1		T443	3		T554	2
all_values[32]	485	1			T443	1		T854	1		T857	2
all_values[33]	462	1			T443	2		T472	2		T757	1
all_values[34]	434	1			T443	1		T854	1		T554	1
all_values[35]	489	1			T443	4		T757	1		T758	2
all_values[36]	469	1			T443	2		T554	2		T758	4
all_values[37]	496	1			T443	2		T520	1		T554	1
all_values[38]	463	1			T443	3		T472	2		T554	1
all_values[39]	461	1			T443	2		T554	1		T758	1
all_values[40]	482	1			T443	1		T758	5		T878	3
all_values[41]	483	1			T443	2		T857	1		T441	1
all_values[42]	500	1			T443	2		T554	1		T758	2
all_values[43]	489	1			T126	1		T443	1		T472	2
all_values[44]	461	1			T443	2		T441	1		T878	4
all_values[45]	487	1			T126	1		T554	1		T441	1
all_values[46]	450	1			T126	1		T443	1		T554	1
all_values[47]	500	1			T443	3		T854	1		T554	1
all_values[48]	481	1			T126	1		T443	2		T854	1
all_values[49]	480	1			T126	1		T443	1		T854	1