Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3733	1			T443	37		T259	2		T520	2
all_values[1]	3635	1			T443	41		T259	2		T520	2
all_values[2]	3733	1			T443	37		T259	3		T520	1
all_values[3]	3647	1			T443	34		T259	2		T520	2
all_values[4]	3691	1			T443	38		T259	2		T520	1
all_values[5]	3734	1			T443	28		T520	2		T553	1
all_values[6]	3694	1			T443	32		T520	3		T553	4
all_values[7]	3735	1			T443	18		T259	3		T553	1
all_values[8]	3710	1			T443	32		T259	2		T520	3
all_values[9]	3751	1			T443	21		T259	3		T520	5
all_values[10]	3816	1			T443	30		T259	2		T520	3
all_values[11]	3642	1			T443	22		T553	1		T554	4
all_values[12]	3782	1			T443	27		T259	3		T520	3
all_values[13]	3818	1			T443	27		T259	1		T520	2
all_values[14]	3729	1			T443	38		T259	1		T520	1
all_values[15]	3747	1			T443	31		T520	4		T553	1
all_values[16]	3844	1			T443	33		T553	3		T554	2
all_values[17]	3753	1			T443	40		T520	5		T553	1
all_values[18]	3688	1			T443	42		T259	1		T554	6
all_values[19]	3799	1			T443	26		T520	1		T554	2
all_values[20]	3705	1			T443	28		T259	5		T520	2
all_values[21]	3701	1			T443	25		T259	1		T520	2
all_values[22]	3657	1			T443	29		T259	2		T520	1
all_values[23]	3649	1			T443	38		T259	1		T520	3
all_values[24]	3727	1			T443	26		T259	2		T520	3
all_values[25]	3834	1			T443	37		T259	3		T520	4
all_values[26]	3712	1			T443	37		T259	2		T520	3
all_values[27]	3695	1			T443	38		T259	1		T520	2
all_values[28]	3689	1			T443	27		T259	2		T520	5
all_values[29]	3692	1			T443	25		T259	2		T520	2
all_values[30]	3713	1			T443	24		T259	4		T520	3
all_values[31]	3720	1			T443	35		T259	3		T520	1
all_values[32]	3685	1			T443	32		T259	2		T520	2
all_values[33]	3661	1			T443	37		T259	1		T520	5
all_values[34]	3753	1			T443	27		T259	2		T520	1
all_values[35]	3624	1			T443	32		T259	2		T520	3
all_values[36]	3726	1			T443	26		T259	3		T520	2
all_values[37]	3600	1			T443	34		T259	1		T520	2
all_values[38]	3687	1			T443	25		T259	2		T520	3
all_values[39]	3717	1			T443	36		T520	3		T553	1
all_values[40]	3640	1			T443	27		T259	1		T520	4
all_values[41]	3689	1			T443	28		T259	5		T520	2
all_values[42]	3661	1			T443	36		T259	2		T520	2
all_values[43]	3735	1			T443	23		T259	3		T520	5
all_values[44]	3708	1			T443	30		T259	1		T553	1
all_values[45]	3689	1			T443	47		T259	1		T520	6
all_values[46]	3687	1			T443	40		T520	2		T553	2
all_values[47]	3644	1			T443	29		T259	3		T520	2
all_values[48]	3751	1			T443	43		T520	3		T554	4
all_values[49]	3773	1			T443	32		T259	3		T520	3
all_values[50]	3721	1			T443	43		T259	4		T520	1
all_values[51]	3787	1			T443	35		T259	2		T520	2
all_values[52]	3643	1			T443	28		T259	3		T520	4
all_values[53]	3693	1			T443	25		T520	3		T554	4
all_values[54]	3721	1			T443	29		T259	5		T520	1
all_values[55]	3715	1			T443	27		T259	3		T520	2
all_values[56]	3725	1			T443	36		T259	2		T520	1
all_values[57]	3907	1			T443	36		T259	2		T520	3
all_values[58]	3715	1			T443	24		T520	3		T554	8
all_values[59]	3719	1			T443	31		T259	2		T520	1
all_values[60]	3606	1			T443	27		T520	4		T553	1
all_values[61]	3855	1			T443	34		T259	2		T520	5
all_values[62]	3631	1			T443	26		T259	1		T520	4
all_values[63]	3759	1			T443	29		T259	2		T520	2