Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3782491	1			T75	4764		T76	1147		T77	11474
values[2]	749011	1			T75	808		T77	2203		T143	230
values[3]	98111	1			T75	37		T77	4		T245	2
values[4]	51362	1			T75	40		T245	2		T543	1
values[5]	34300	1			T75	28		T245	2		T428	121
values[6]	25713	1			T75	29		T245	2		T428	61
values[7]	20991	1			T75	58		T245	2		T428	31
values[8]	18101	1			T75	38		T245	2		T428	19
values[9]	16360	1			T75	26		T245	2		T428	13
values[10]	15143	1			T75	20		T245	2		T428	17
values[11]	14343	1			T75	35		T245	2		T428	16
values[12]	13728	1			T75	40		T245	2		T428	15
values[13]	13263	1			T75	18		T245	2		T428	16
values[14]	13132	1			T75	39		T245	2		T428	17
values[15]	12747	1			T75	34		T245	2		T428	21
values[16]	12227	1			T75	29		T245	2		T428	12
values[17]	11559	1			T75	40		T245	2		T428	16
values[18]	11100	1			T75	35		T245	2		T428	19
values[19]	10417	1			T75	56		T245	2		T428	23
values[20]	10051	1			T75	57		T245	2		T428	24
values[21]	10041	1			T75	39		T245	2		T428	13
values[22]	9957	1			T75	43		T245	2		T428	11
values[23]	9506	1			T75	39		T245	2		T428	7
values[24]	9219	1			T75	35		T245	2		T428	7
values[25]	8663	1			T75	21		T245	2		T428	9
values[26]	8304	1			T75	30		T245	2		T428	18
values[27]	8154	1			T75	35		T245	2		T428	9
values[28]	8015	1			T75	32		T245	2		T428	6
values[29]	7479	1			T75	19		T245	2		T428	7
values[30]	6751	1			T75	18		T245	2		T428	10
values[31]	6310	1			T75	18		T245	2		T428	20
values[32]	6010	1			T75	42		T245	2		T428	9
values[33]	5806	1			T75	50		T245	2		T428	9
values[34]	5467	1			T75	19		T245	2		T428	14
values[35]	4853	1			T75	14		T245	2		T428	8
values[36]	4629	1			T75	7		T245	2		T428	13
values[37]	4368	1			T75	5		T245	2		T428	6
values[38]	4228	1			T75	4		T245	2		T428	4
values[39]	3945	1			T75	11		T245	2		T428	5
values[40]	3813	1			T75	6		T245	2		T428	9
values[41]	3733	1			T75	7		T245	2		T428	6
values[42]	3658	1			T75	3		T245	2		T428	8
values[43]	3631	1			T75	4		T245	2		T428	17
values[44]	3572	1			T75	8		T245	2		T428	10
values[45]	3468	1			T75	2		T245	2		T428	10
values[46]	3431	1			T75	3		T245	2		T428	12
values[47]	3454	1			T75	6		T245	2		T428	3
values[48]	3390	1			T75	3		T245	2		T428	4
values[49]	3308	1			T75	4		T245	2		T428	6
values[50]	3205	1			T245	2		T428	6		T539	15
values[51]	3195	1			T245	2		T428	11		T539	15
values[52]	3074	1			T245	2		T428	5		T539	4
values[53]	3056	1			T245	2		T428	13		T539	6
values[54]	2968	1			T245	2		T428	5		T539	4
values[55]	2839	1			T245	2		T428	3		T539	2
values[56]	2737	1			T245	2		T428	3		T539	2
values[57]	2708	1			T245	2		T428	10		T539	2
values[58]	2670	1			T245	2		T428	7		T539	5
values[59]	2621	1			T245	2		T428	4		T539	8
values[60]	2729	1			T245	3		T428	11		T539	9
values[61]	2950	1			T245	2		T428	11		T539	7
values[62]	4245	1			T245	2		T428	13		T539	10
values[63]	11234	1			T245	2		T428	46		T539	17
values[64]	261631	1			T245	338		T428	80		T539	106

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4838005	1			T75	5899		T76	1126		T77	13652
values[2]	818449	1			T75	1115		T77	2628		T143	289
values[3]	85480	1			T75	21		T77	65		T143	6
values[4]	15052	1			T75	3		T77	8		T143	1
values[5]	5562	1			T77	1		T245	2		T428	1
values[6]	3085	1			T438	2		T539	2		T599	60
values[7]	2309	1			T438	1		T539	5		T599	47
values[8]	1901	1			T539	8		T599	41		T841	2
values[9]	1666	1			T539	2		T599	28		T841	5
values[10]	1483	1			T539	2		T599	37		T841	2
values[11]	1337	1			T539	4		T599	29		T841	2
values[12]	1279	1			T539	3		T599	24		T841	10
values[13]	1254	1			T539	2		T599	42		T841	4
values[14]	1223	1			T539	9		T599	32		T841	5
values[15]	1098	1			T539	5		T599	37		T841	3
values[16]	960	1			T539	8		T599	20		T841	1
values[17]	915	1			T539	10		T599	26		T841	1
values[18]	943	1			T539	9		T599	22		T841	1
values[19]	904	1			T539	7		T599	33		T841	2
values[20]	754	1			T539	2		T599	31		T841	4
values[21]	752	1			T539	2		T599	43		T841	10
values[22]	753	1			T539	6		T599	42		T841	5
values[23]	716	1			T539	3		T599	41		T841	3
values[24]	692	1			T539	4		T599	44		T841	2
values[25]	624	1			T539	2		T599	24		T841	4
values[26]	613	1			T539	3		T599	25		T841	1
values[27]	639	1			T539	5		T599	24		T841	1
values[28]	635	1			T539	8		T599	29		T841	2
values[29]	612	1			T539	6		T599	22		T841	1
values[30]	587	1			T539	1		T599	29		T841	1
values[31]	621	1			T539	4		T599	31		T841	6
values[32]	590	1			T539	1		T599	22		T841	3
values[33]	557	1			T539	5		T599	26		T841	4
values[34]	543	1			T539	1		T599	22		T841	5
values[35]	556	1			T539	3		T599	32		T841	1
values[36]	560	1			T539	4		T599	28		T841	5
values[37]	528	1			T539	11		T599	18		T841	5
values[38]	523	1			T539	16		T599	13		T841	7
values[39]	476	1			T539	9		T599	7		T841	2
values[40]	469	1			T539	8		T599	11		T841	2
values[41]	462	1			T539	4		T599	13		T841	2
values[42]	480	1			T539	4		T599	8		T841	3
values[43]	460	1			T539	4		T599	5		T841	1
values[44]	451	1			T539	2		T599	4		T841	1
values[45]	469	1			T539	2		T599	4		T841	1
values[46]	415	1			T539	2		T599	5		T841	2
values[47]	415	1			T539	2		T599	4		T841	7
values[48]	410	1			T539	1		T599	4		T841	5
values[49]	398	1			T539	1		T599	9		T841	10
values[50]	362	1			T539	1		T599	9		T841	4
values[51]	403	1			T539	1		T599	10		T841	3
values[52]	417	1			T539	1		T599	9		T841	5
values[53]	378	1			T539	3		T599	5		T841	2
values[54]	378	1			T539	4		T599	4		T841	1
values[55]	385	1			T539	1		T599	6		T841	1
values[56]	392	1			T539	1		T599	10		T841	1
values[57]	374	1			T539	6		T599	7		T841	3
values[58]	366	1			T539	3		T599	7		T841	3
values[59]	360	1			T539	1		T599	3		T841	2
values[60]	330	1			T599	3		T841	2		T843	3
values[61]	407	1			T599	6		T841	3		T843	3
values[62]	606	1			T599	26		T841	7		T843	3
values[63]	2319	1			T599	108		T841	4		T843	3
values[64]	26297	1			T599	238		T841	4		T843	629

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	569146	1			T75	603		T76	1199		T77	232
values[2]	2720179	1			T75	4519		T77	11373		T143	852
values[3]	1184521	1			T75	719		T77	2320		T143	259
values[4]	135537	1			T75	45		T77	4		T245	2
values[5]	69254	1			T75	43		T245	2		T428	150
values[6]	46193	1			T75	48		T245	2		T428	98
values[7]	34274	1			T75	33		T245	2		T428	70
values[8]	27107	1			T75	38		T245	2		T428	50
values[9]	23128	1			T75	59		T245	2		T428	20
values[10]	20277	1			T75	46		T245	2		T428	37
values[11]	17984	1			T75	35		T245	2		T428	20
values[12]	16426	1			T75	50		T245	2		T428	21
values[13]	16186	1			T75	50		T245	2		T428	12
values[14]	15453	1			T75	29		T245	2		T428	21
values[15]	14908	1			T75	43		T245	2		T428	19
values[16]	14091	1			T75	48		T245	2		T428	26
values[17]	13177	1			T75	46		T245	2		T428	16
values[18]	12881	1			T75	32		T245	2		T428	16
values[19]	12513	1			T75	20		T245	2		T428	5
values[20]	12030	1			T75	44		T245	2		T428	5
values[21]	11770	1			T75	52		T245	2		T428	8
values[22]	11230	1			T75	34		T245	2		T428	8
values[23]	10882	1			T75	30		T245	2		T428	17
values[24]	10693	1			T75	31		T245	2		T428	11
values[25]	9985	1			T75	28		T245	2		T428	13
values[26]	9495	1			T75	32		T245	2		T428	13
values[27]	9426	1			T75	25		T245	2		T428	11
values[28]	8736	1			T75	28		T245	2		T428	13
values[29]	8287	1			T75	20		T245	2		T428	20
values[30]	7713	1			T75	36		T245	2		T428	21
values[31]	7129	1			T75	54		T245	2		T428	19
values[32]	6728	1			T75	26		T245	2		T428	19
values[33]	6181	1			T75	8		T245	2		T428	23
values[34]	5658	1			T75	8		T245	2		T428	7
values[35]	5350	1			T75	14		T245	2		T428	13
values[36]	4917	1			T75	6		T245	2		T428	12
values[37]	4687	1			T75	4		T245	2		T428	12
values[38]	4383	1			T75	9		T245	2		T428	17
values[39]	4244	1			T75	6		T245	2		T428	6
values[40]	4198	1			T75	7		T245	2		T428	9
values[41]	4112	1			T75	8		T245	2		T428	12
values[42]	3868	1			T75	10		T245	2		T428	8
values[43]	3793	1			T75	3		T245	2		T428	12
values[44]	3698	1			T75	3		T245	2		T428	11
values[45]	3701	1			T75	10		T245	2		T428	10
values[46]	3688	1			T75	3		T245	2		T428	10
values[47]	3554	1			T75	3		T245	2		T428	12
values[48]	3541	1			T75	6		T245	2		T428	12
values[49]	3541	1			T75	3		T245	2		T428	9
values[50]	3550	1			T75	8		T245	2		T428	12
values[51]	3366	1			T75	4		T245	2		T428	8
values[52]	3348	1			T75	2		T245	2		T428	7
values[53]	3202	1			T75	5		T245	2		T428	14
values[54]	3194	1			T75	4		T245	2		T428	8
values[55]	3069	1			T75	1		T245	2		T428	11
values[56]	3068	1			T75	2		T245	2		T428	13
values[57]	2994	1			T75	2		T245	2		T428	8
values[58]	2940	1			T75	3		T245	2		T428	15
values[59]	2931	1			T245	2		T428	6		T539	7
values[60]	2939	1			T245	2		T428	10		T539	8
values[61]	3014	1			T245	2		T428	5		T539	8
values[62]	3931	1			T245	2		T428	14		T539	16
values[63]	9313	1			T245	3		T428	39		T539	18
values[64]	253801	1			T245	413		T428	210		T539	140