Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2316974	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

39950456

1

T4

6214

T5

4451

T6

116807

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	29634122	1			T4	2782		T5	1480		T6	102495
values[0x0]	11074504	1			T4	3432		T5	2971		T6	14312
values[0x1]	1558804	1			T4	537		T5	158		T6	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	841916	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

41425514

1

T4

6751

T5

4609

T6

116818

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19652928	1			T4	3376		T5	2305		T6	58409
valid_sources[0x01]	19651343	1			T4	3375		T5	2304		T6	58409
valid_sources[0x02]	49665	1			T440	1		T138	758		T391	135
valid_sources[0x03]	45979	1			T138	913		T391	116		T139	383
valid_sources[0x04]	48160	1			T86	1		T440	1		T138	776
valid_sources[0x05]	47743	1			T440	1		T138	702		T391	122
valid_sources[0x06]	48024	1			T440	1		T138	754		T391	123
valid_sources[0x07]	47547	1			T86	1		T138	863		T391	126
valid_sources[0x08]	47583	1			T440	2		T138	728		T391	142
valid_sources[0x09]	47110	1			T80	8		T138	807		T391	102
valid_sources[0x0a]	47640	1			T138	831		T391	133		T139	421
valid_sources[0x0b]	47354	1			T440	1		T138	934		T391	107
valid_sources[0x0c]	47947	1			T86	2		T440	2		T138	725
valid_sources[0x0d]	47329	1			T138	924		T391	124		T139	420
valid_sources[0x0e]	47629	1			T86	1		T138	831		T391	128
valid_sources[0x0f]	47320	1			T86	1		T138	777		T391	120
valid_sources[0x10]	47729	1			T86	3		T440	2		T138	735
valid_sources[0x11]	48132	1			T440	1		T138	849		T391	126
valid_sources[0x12]	47057	1			T8	9		T440	2		T138	832
valid_sources[0x13]	48544	1			T86	2		T138	780		T391	108
valid_sources[0x14]	47723	1			T8	5		T86	1		T138	836
valid_sources[0x15]	48069	1			T8	3		T138	800		T391	118
valid_sources[0x16]	46169	1			T138	700		T391	110		T139	383
valid_sources[0x17]	47292	1			T86	1		T138	793		T391	137
valid_sources[0x18]	48581	1			T86	2		T138	789		T391	119
valid_sources[0x19]	48326	1			T138	722		T391	144		T139	409
valid_sources[0x1a]	47688	1			T80	11		T86	1		T138	733
valid_sources[0x1b]	47753	1			T81	12		T138	728		T391	132
valid_sources[0x1c]	47326	1			T138	760		T391	111		T139	391
valid_sources[0x1d]	47160	1			T86	1		T440	1		T138	874
valid_sources[0x1e]	47771	1			T440	1		T138	857		T391	123
valid_sources[0x1f]	47434	1			T80	5		T440	1		T138	797
valid_sources[0x20]	47310	1			T138	726		T391	107		T139	387

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28648659

1

T4

2782

T5

1480

T6

102495

values[0x0]

all_enables

biggest_size

11022204

1

T4

3432

T5

2971

T6

14312

values[0x1]

all_enables

biggest_size

279593

1

T80

21

T8

24

T81

18

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3028667	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

479314

1

T75

35

T76

169

T77

59

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1187445	1			T75	156		T76	391		T77	304
values[0x0]	1134368	1			T75	28		T76	375		T77	46
values[0x1]	1186168	1			T75	147		T76	381		T77	279

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2345290	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1162691

1

T75

125

T76

399

T77

220

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55490	1			T75	2		T76	17		T77	12
valid_sources[0x01]	54160	1			T75	7		T76	48		T77	11
valid_sources[0x02]	53885	1			T75	7		T76	54		T77	6
valid_sources[0x03]	55110	1			T75	5		T77	6		T143	13
valid_sources[0x04]	54581	1			T75	6		T76	16		T77	11
valid_sources[0x05]	54033	1			T75	5		T76	20		T77	7
valid_sources[0x06]	55972	1			T75	4		T76	32		T77	12
valid_sources[0x07]	54500	1			T75	8		T76	33		T77	10
valid_sources[0x08]	54007	1			T75	10		T76	27		T77	14
valid_sources[0x09]	53827	1			T75	7		T76	18		T77	4
valid_sources[0x0a]	54754	1			T75	6		T76	19		T77	10
valid_sources[0x0b]	54640	1			T75	5		T76	24		T77	11
valid_sources[0x0c]	54241	1			T75	5		T77	10		T143	23
valid_sources[0x0d]	54897	1			T75	3		T76	42		T77	9
valid_sources[0x0e]	53487	1			T75	7		T77	8		T143	14
valid_sources[0x0f]	54747	1			T75	5		T76	34		T77	9
valid_sources[0x10]	55480	1			T75	6		T76	17		T77	9
valid_sources[0x11]	54480	1			T75	6		T77	16		T143	19
valid_sources[0x12]	55141	1			T75	5		T76	33		T77	7
valid_sources[0x13]	54166	1			T75	7		T76	11		T77	7
valid_sources[0x14]	55412	1			T75	7		T76	17		T77	5
valid_sources[0x15]	54404	1			T75	3		T76	8		T77	2
valid_sources[0x16]	55619	1			T76	11		T77	11		T143	7
valid_sources[0x17]	54776	1			T75	3		T77	14		T143	20
valid_sources[0x18]	55349	1			T75	4		T76	43		T77	12
valid_sources[0x19]	55207	1			T75	9		T76	9		T77	7
valid_sources[0x1a]	54645	1			T75	2		T77	14		T143	32
valid_sources[0x1b]	55107	1			T75	10		T76	14		T77	9
valid_sources[0x1c]	54375	1			T75	4		T76	11		T77	5
valid_sources[0x1d]	55267	1			T75	4		T76	11		T77	7
valid_sources[0x1e]	54622	1			T75	8		T76	23		T77	16
valid_sources[0x1f]	54843	1			T75	6		T76	13		T77	13
valid_sources[0x20]	54954	1			T75	2		T76	10		T77	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

50286

1

T75

7

T76

22

T77

23

values[0x0]

all_enables

biggest_size

379091

1

T75

15

T76

126

T77

15

values[0x1]

all_enables

biggest_size

49937

1

T75

13

T76

21

T77

21

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3212103	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

522534

1

T75

29

T76

149

T77

72

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1276183	1			T75	161		T76	375		T77	323
values[0x0]	1180172	1			T75	29		T76	351		T77	65
values[0x1]	1278282	1			T75	152		T76	400		T77	327

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2466020	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1268617

1

T75

116

T76

376

T77

255

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	58772	1			T75	3		T76	7		T77	9
valid_sources[0x01]	58589	1			T75	8		T76	46		T77	9
valid_sources[0x02]	58628	1			T75	7		T76	56		T77	16
valid_sources[0x03]	58785	1			T75	5		T77	13		T143	8
valid_sources[0x04]	57919	1			T75	3		T76	23		T77	4
valid_sources[0x05]	58531	1			T75	6		T76	8		T77	11
valid_sources[0x06]	57991	1			T75	5		T76	17		T77	7
valid_sources[0x07]	58921	1			T75	7		T76	21		T77	12
valid_sources[0x08]	58267	1			T75	5		T76	12		T77	14
valid_sources[0x09]	56589	1			T75	6		T76	18		T77	14
valid_sources[0x0a]	58525	1			T75	3		T76	25		T77	15
valid_sources[0x0b]	58681	1			T75	10		T76	25		T77	8
valid_sources[0x0c]	57586	1			T75	3		T77	7		T143	32
valid_sources[0x0d]	58383	1			T75	5		T76	46		T77	9
valid_sources[0x0e]	58368	1			T75	2		T77	6		T143	6
valid_sources[0x0f]	58386	1			T75	10		T76	36		T77	8
valid_sources[0x10]	58051	1			T75	6		T76	20		T77	12
valid_sources[0x11]	56583	1			T75	4		T77	13		T143	24
valid_sources[0x12]	58700	1			T75	4		T76	26		T77	4
valid_sources[0x13]	60134	1			T75	1		T76	20		T77	6
valid_sources[0x14]	58806	1			T75	5		T76	6		T77	15
valid_sources[0x15]	57235	1			T75	4		T76	19		T77	6
valid_sources[0x16]	59784	1			T75	5		T76	6		T77	12
valid_sources[0x17]	58528	1			T75	6		T77	11		T143	13
valid_sources[0x18]	58856	1			T75	3		T76	48		T77	9
valid_sources[0x19]	58605	1			T75	4		T76	17		T77	11
valid_sources[0x1a]	58021	1			T75	6		T77	10		T143	8
valid_sources[0x1b]	58291	1			T75	2		T76	6		T77	7
valid_sources[0x1c]	57757	1			T75	6		T76	9		T77	8
valid_sources[0x1d]	58095	1			T75	6		T76	11		T77	16
valid_sources[0x1e]	58709	1			T75	4		T76	13		T77	14
valid_sources[0x1f]	57918	1			T75	9		T76	20		T77	19
valid_sources[0x20]	58190	1			T75	6		T76	33		T77	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

54796

1

T75

12

T76

13

T77

19

values[0x0]

all_enables

biggest_size

412984

1

T75

7

T76

121

T77

26

values[0x1]

all_enables

biggest_size

54754

1

T75

10

T76

15

T77

27

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3052207	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

482132

1

T75

36

T76

160

T77

60

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1194266	1			T75	141		T76	391		T77	302
values[0x0]	1143771	1			T75	23		T76	403		T77	38
values[0x1]	1196302	1			T75	171		T76	405		T77	291

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2364351	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1169988

1

T75

129

T76

409

T77

250

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54971	1			T75	3		T76	13		T77	8
valid_sources[0x01]	54298	1			T75	7		T76	41		T77	12
valid_sources[0x02]	55166	1			T75	8		T76	55		T77	8
valid_sources[0x03]	56151	1			T75	7		T77	8		T143	24
valid_sources[0x04]	55441	1			T75	5		T76	22		T77	15
valid_sources[0x05]	54636	1			T75	8		T76	18		T77	9
valid_sources[0x06]	56171	1			T75	5		T76	14		T77	13
valid_sources[0x07]	56367	1			T75	11		T76	28		T77	9
valid_sources[0x08]	55191	1			T75	7		T76	17		T77	10
valid_sources[0x09]	53852	1			T75	4		T76	22		T77	11
valid_sources[0x0a]	55541	1			T75	7		T76	33		T77	10
valid_sources[0x0b]	54826	1			T75	5		T76	26		T77	10
valid_sources[0x0c]	55002	1			T75	6		T77	6		T143	24
valid_sources[0x0d]	54673	1			T75	5		T76	50		T77	13
valid_sources[0x0e]	54722	1			T75	6		T77	6		T143	7
valid_sources[0x0f]	55376	1			T75	6		T76	38		T77	13
valid_sources[0x10]	55807	1			T75	2		T76	12		T77	8
valid_sources[0x11]	54673	1			T75	9		T77	10		T143	24
valid_sources[0x12]	56443	1			T75	11		T76	25		T77	12
valid_sources[0x13]	54674	1			T75	2		T76	17		T77	8
valid_sources[0x14]	55335	1			T75	3		T76	17		T77	8
valid_sources[0x15]	55645	1			T75	4		T76	16		T77	10
valid_sources[0x16]	55250	1			T75	3		T76	14		T77	3
valid_sources[0x17]	54513	1			T75	2		T77	14		T143	16
valid_sources[0x18]	56480	1			T75	2		T76	46		T77	12
valid_sources[0x19]	55099	1			T75	7		T76	16		T77	15
valid_sources[0x1a]	55095	1			T75	6		T77	9		T143	19
valid_sources[0x1b]	56711	1			T75	6		T76	19		T77	9
valid_sources[0x1c]	55827	1			T75	3		T76	7		T77	10
valid_sources[0x1d]	55015	1			T75	10		T76	5		T77	12
valid_sources[0x1e]	55304	1			T75	3		T76	22		T77	9
valid_sources[0x1f]	54944	1			T75	6		T76	6		T77	7
valid_sources[0x20]	56131	1			T75	1		T76	27		T77	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

50345

1

T75

15

T76

15

T77

23

values[0x0]

all_enables

biggest_size

381385

1

T75

12

T76

135

T77

15

values[0x1]

all_enables

biggest_size

50402

1

T75

9

T76

10

T77

22