Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	545743387	63388534	0	0
DepthKnown_A	545743387	545635492	0	0
RvalidKnown_A	545743387	545635492	0	0
WreadyKnown_A	545743387	545635492	0	0
gen_passthru_fifo.paramCheckPass	1022	1022	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545743387	63388534	0	0
T4	94885	11266	0	0
T5	82084	10683	0	0
T6	131524	143735	0	0
T16	243783	25416	0	0
T17	136181	13142	0	0
T39	222808	29332	0	0
T40	248167	32680	0	0
T41	343305	34034	0	0
T47	173492	20245	0	0
T89	63001	6309	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545743387	545635492	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545743387	545635492	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545743387	545635492	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T41	1	1	0	0
T47	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	545743387	49267051	0	0
DepthKnown_A	545743387	545635492	0	0
RvalidKnown_A	545743387	545635492	0	0
WreadyKnown_A	545743387	545635492	0	0
gen_passthru_fifo.paramCheckPass	1022	1022	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545743387	49267051	0	0
T4	94885	8883	0	0
T5	82084	7532	0	0
T6	131524	124336	0	0
T16	243783	21494	0	0
T17	136181	9040	0	0
T39	222808	19730	0	0
T40	248167	23077	0	0
T41	343305	28067	0	0
T47	173492	15228	0	0
T89	63001	4371	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545743387	545635492	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545743387	545635492	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545743387	545635492	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T41	1	1	0	0
T47	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	545743387	46442277	0	0
DepthKnown_A	545743387	545635492	0	0
RvalidKnown_A	545743387	545635492	0	0
WreadyKnown_A	545743387	545635492	0	0
gen_passthru_fifo.paramCheckPass	1022	1022	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545743387	46442277	0	0
T4	94885	6942	0	0
T5	82084	4755	0	0
T6	131524	201406	0	0
T16	243783	23148	0	0
T17	136181	6797	0	0
T39	222808	13964	0	0
T40	248167	16376	0	0
T41	343305	16164	0	0
T47	173492	11221	0	0
T89	63001	3484	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545743387	545635492	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545743387	545635492	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545743387	545635492	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T41	1	1	0	0
T47	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	545743387	39323825	0	0
DepthKnown_A	545743387	545635492	0	0
RvalidKnown_A	545743387	545635492	0	0
WreadyKnown_A	545743387	545635492	0	0
gen_passthru_fifo.paramCheckPass	1022	1022	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545743387	39323825	0	0
T4	94885	6751	0	0
T5	82084	4609	0	0
T6	131524	116818	0	0
T16	243783	22943	0	0
T17	136181	6530	0	0
T39	222808	13585	0	0
T40	248167	15994	0	0
T41	343305	15780	0	0
T47	173492	10871	0	0
T89	63001	3367	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545743387	545635492	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545743387	545635492	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	545743387	545635492	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1022	1022	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T41	1	1	0	0
T47	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	643794361	96347	0	0
DepthKnown_A	643794361	643670560	0	0
RvalidKnown_A	643794361	643670560	0	0
WreadyKnown_A	643794361	643670560	0	0
gen_passthru_fifo.paramCheckPass	2933	2933	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643794361	96347	0	0
T4	94885	14	0	0
T5	82084	16	0	0
T6	131524	34	0	0
T16	243783	53	0	0
T17	136181	27	0	0
T39	222808	151	0	0
T40	248167	151	0	0
T41	343305	44	0	0
T47	173492	74	0	0
T89	63001	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643794361	643670560	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643794361	643670560	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643794361	643670560	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2933	2933	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T41	1	1	0	0
T47	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	643794361	96718	0	0
DepthKnown_A	643794361	643670560	0	0
RvalidKnown_A	643794361	643670560	0	0
WreadyKnown_A	643794361	643670560	0	0
gen_passthru_fifo.paramCheckPass	2933	2933	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643794361	96718	0	0
T4	94885	14	0	0
T5	82084	16	0	0
T6	131524	34	0	0
T16	243783	53	0	0
T17	136181	27	0	0
T39	222808	151	0	0
T40	248167	151	0	0
T41	343305	44	0	0
T47	173492	74	0	0
T89	63001	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643794361	643670560	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643794361	643670560	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643794361	643670560	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2933	2933	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T41	1	1	0	0
T47	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	643794361	52503	0	0
DepthKnown_A	643794361	643670560	0	0
RvalidKnown_A	643794361	643670560	0	0
WreadyKnown_A	643794361	643670560	0	0
gen_passthru_fifo.paramCheckPass	2933	2933	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643794361	52503	0	0
T4	94885	13	0	0
T5	82084	13	0	0
T6	131524	5	0	0
T16	243783	52	0	0
T17	136181	25	0	0
T39	222808	95	0	0
T40	248167	95	0	0
T41	343305	41	0	0
T47	173492	72	0	0
T89	63001	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643794361	643670560	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643794361	643670560	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643794361	643670560	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2933	2933	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T41	1	1	0	0
T47	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	643794361	52503	0	0
DepthKnown_A	643794361	643670560	0	0
RvalidKnown_A	643794361	643670560	0	0
WreadyKnown_A	643794361	643670560	0	0
gen_passthru_fifo.paramCheckPass	2933	2933	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643794361	52503	0	0
T4	94885	13	0	0
T5	82084	13	0	0
T6	131524	5	0	0
T16	243783	52	0	0
T17	136181	25	0	0
T39	222808	95	0	0
T40	248167	95	0	0
T41	343305	41	0	0
T47	173492	72	0	0
T89	63001	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643794361	643670560	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643794361	643670560	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643794361	643670560	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2933	2933	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T41	1	1	0	0
T47	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	643794361	43844	0	0
DepthKnown_A	643794361	643670560	0	0
RvalidKnown_A	643794361	643670560	0	0
WreadyKnown_A	643794361	643670560	0	0
gen_passthru_fifo.paramCheckPass	2933	2933	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643794361	43844	0	0
T4	94885	1	0	0
T5	82084	3	0	0
T6	131524	29	0	0
T16	243783	1	0	0
T17	136181	2	0	0
T39	222808	56	0	0
T40	248167	56	0	0
T41	343305	3	0	0
T47	173492	2	0	0
T89	63001	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643794361	643670560	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643794361	643670560	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643794361	643670560	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2933	2933	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T41	1	1	0	0
T47	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	643794361	44215	0	0
DepthKnown_A	643794361	643670560	0	0
RvalidKnown_A	643794361	643670560	0	0
WreadyKnown_A	643794361	643670560	0	0
gen_passthru_fifo.paramCheckPass	2933	2933	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643794361	44215	0	0
T4	94885	1	0	0
T5	82084	3	0	0
T6	131524	29	0	0
T16	243783	1	0	0
T17	136181	2	0	0
T39	222808	56	0	0
T40	248167	56	0	0
T41	343305	3	0	0
T47	173492	2	0	0
T89	63001	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643794361	643670560	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643794361	643670560	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	643794361	643670560	0	0
T4	94885	94830	0	0
T5	82084	82033	0	0
T6	131524	131519	0	0
T16	243783	243721	0	0
T17	136181	136073	0	0
T39	222808	222699	0	0
T40	248167	248054	0	0
T41	343305	343076	0	0
T47	173492	173391	0	0
T89	63001	62943	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2933	2933	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T39	1	1	0	0
T40	1	1	0	0
T41	1	1	0	0
T47	1	1	0	0
T89	1	1	0	0