Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.34	90.68		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T47,T17,T39	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T6,T56,T207	Yes	T6,T56,T207	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T6,T56,T207	Yes	T6,T56,T207	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T78,*T79	Yes	T70,T78,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T80,T8,T81	Yes	T80,T8,T81	INPUT
tl_i.a_valid	Yes	Yes	T6,T56,T207	Yes	T6,T56,T207	INPUT
tl_o.a_ready	Yes	Yes	T6,T56,T207	Yes	T6,T56,T207	OUTPUT
tl_o.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T6,T56,T207	Yes	T6,T56,T207	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T6,T56,T207	Yes	T6,T56,T207	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T6,T56,T207	Yes	T6,T56,T207	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T254,*T741,*T256	Yes	T254,T741,T256	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T6,*T56,*T207	Yes	T6,T56,T207	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T6,T56,T207	Yes	T6,T56,T207	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T148,T82,T742	Yes	T148,T82,T742	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T148,T82,T83	Yes	T148,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T148,T82,T83	Yes	T148,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T148,T82,T742	Yes	T148,T82,T742	OUTPUT
cio_rx_i	Yes	Yes	T39,T40,T41	Yes	T4,T5,T16	INPUT
cio_tx_o	Yes	Yes	T6,T56,T207	Yes	T6,T56,T207	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T207,T141,T103	Yes	T207,T141,T103	OUTPUT
intr_tx_empty_o	Yes	Yes	T207,T141,T103	Yes	T207,T141,T103	OUTPUT
intr_rx_watermark_o	Yes	Yes	T207,T141,T103	Yes	T207,T141,T103	OUTPUT
intr_tx_done_o	Yes	Yes	T207,T141,T103	Yes	T207,T141,T103	OUTPUT
intr_rx_overflow_o	Yes	Yes	T207,T141,T103	Yes	T207,T141,T103	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T326,T322,T338	Yes	T326,T322,T338	OUTPUT
intr_rx_break_err_o	Yes	Yes	T326,T322,T338	Yes	T326,T322,T338	OUTPUT
intr_rx_timeout_o	Yes	Yes	T326,T322,T338	Yes	T326,T322,T338	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T326,T322,T338	Yes	T326,T322,T338	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T47,T17,T39	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T6,T56,T103	Yes	T6,T56,T103	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T6,T56,T103	Yes	T6,T56,T103	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T78,*T79	Yes	T70,T78,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T80,T8,T81	Yes	T80,T8,T81	INPUT
tl_i.a_valid	Yes	Yes	T6,T56,T103	Yes	T6,T56,T103	INPUT
tl_o.a_ready	Yes	Yes	T6,T56,T103	Yes	T6,T56,T103	OUTPUT
tl_o.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T6,T56,T103	Yes	T6,T56,T103	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T6,T56,T103	Yes	T6,T56,T103	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T6,T56,T103	Yes	T6,T56,T103	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T254,*T741,*T256	Yes	T254,T741,T256	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T6,*T56,*T103	Yes	T6,T56,T103	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T6,T56,T103	Yes	T6,T56,T103	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T82,T150,T386	Yes	T82,T150,T386	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T82,T83,T85	Yes	T82,T83,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T82,T83,T85	Yes	T82,T83,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T82,T150,T386	Yes	T82,T150,T386	OUTPUT
cio_rx_i	Yes	Yes	T39,T40,T41	Yes	T4,T5,T16	INPUT
cio_tx_o	Yes	Yes	T6,T56,T103	Yes	T6,T56,T103	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T103,T213,T305	Yes	T103,T213,T305	OUTPUT
intr_tx_empty_o	Yes	Yes	T103,T213,T214	Yes	T103,T213,T214	OUTPUT
intr_rx_watermark_o	Yes	Yes	T103,T213,T214	Yes	T103,T213,T214	OUTPUT
intr_tx_done_o	Yes	Yes	T103,T213,T214	Yes	T103,T213,T214	OUTPUT
intr_rx_overflow_o	Yes	Yes	T103,T213,T214	Yes	T103,T213,T214	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T326,T322,T338	Yes	T326,T322,T338	OUTPUT
intr_rx_break_err_o	Yes	Yes	T326,T322,T338	Yes	T326,T322,T338	OUTPUT
intr_rx_timeout_o	Yes	Yes	T326,T322,T338	Yes	T326,T322,T338	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T326,T322,T338	Yes	T326,T322,T338	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T47,T17,T39	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T207,T208,T326	Yes	T207,T208,T326	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T207,T208,T326	Yes	T207,T208,T326	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T78,*T79	Yes	T70,T78,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T80,T8,T81	Yes	T80,T8,T81	INPUT
tl_i.a_valid	Yes	Yes	T207,T208,T150	Yes	T207,T208,T150	INPUT
tl_o.a_ready	Yes	Yes	T207,T208,T150	Yes	T207,T208,T150	OUTPUT
tl_o.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T207,T208,T326	Yes	T207,T208,T326	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T207,T208,T150	Yes	T207,T208,T150	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T207,T208,T150	Yes	T207,T208,T150	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T207,*T208,*T326	Yes	T207,T208,T326	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T207,T208,T150	Yes	T207,T208,T150	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T148,T82,T743	Yes	T148,T82,T743	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T148,T82,T83	Yes	T148,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T148,T82,T83	Yes	T148,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T148,T82,T743	Yes	T148,T82,T743	OUTPUT
cio_rx_i	Yes	Yes	T42,T207,T208	Yes	T42,T207,T208	INPUT
cio_tx_o	Yes	Yes	T207,T208,T209	Yes	T207,T208,T209	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T207,T208,T326	Yes	T207,T208,T326	OUTPUT
intr_tx_empty_o	Yes	Yes	T207,T208,T326	Yes	T207,T208,T326	OUTPUT
intr_rx_watermark_o	Yes	Yes	T207,T208,T326	Yes	T207,T208,T326	OUTPUT
intr_tx_done_o	Yes	Yes	T207,T208,T326	Yes	T207,T208,T326	OUTPUT
intr_rx_overflow_o	Yes	Yes	T207,T208,T326	Yes	T207,T208,T326	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T326,T322,T338	Yes	T326,T322,T338	OUTPUT
intr_rx_break_err_o	Yes	Yes	T326,T322,T338	Yes	T326,T322,T338	OUTPUT
intr_rx_timeout_o	Yes	Yes	T326,T322,T338	Yes	T326,T322,T338	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T326,T322,T338	Yes	T326,T322,T338	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T47,T17,T39	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T141,T334,T335	Yes	T141,T334,T335	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T141,T334,T335	Yes	T141,T334,T335	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T78,*T79	Yes	T70,T78,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T80,T8,T81	Yes	T80,T8,T81	INPUT
tl_i.a_valid	Yes	Yes	T141,T334,T335	Yes	T141,T334,T335	INPUT
tl_o.a_ready	Yes	Yes	T141,T334,T335	Yes	T141,T334,T335	OUTPUT
tl_o.d_error	Yes	Yes	T75,T77,T143	Yes	T75,T77,T143	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T141,T334,T335	Yes	T141,T334,T335	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T141,T334,T335	Yes	T141,T334,T335	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T141,T334,T335	Yes	T141,T334,T335	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T141,*T334,*T335	Yes	T141,T334,T335	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T141,T334,T335	Yes	T141,T334,T335	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T148,T82,T742	Yes	T148,T82,T742	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T148,T82,T83	Yes	T148,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T148,T82,T83	Yes	T148,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T148,T82,T742	Yes	T148,T82,T742	OUTPUT
cio_rx_i	Yes	Yes	T141,T334,T335	Yes	T141,T334,T335	INPUT
cio_tx_o	Yes	Yes	T141,T334,T335	Yes	T141,T334,T335	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T141,T334,T335	Yes	T141,T334,T335	OUTPUT
intr_tx_empty_o	Yes	Yes	T141,T334,T335	Yes	T141,T334,T335	OUTPUT
intr_rx_watermark_o	Yes	Yes	T141,T334,T335	Yes	T141,T334,T335	OUTPUT
intr_tx_done_o	Yes	Yes	T141,T334,T335	Yes	T141,T334,T335	OUTPUT
intr_rx_overflow_o	Yes	Yes	T141,T334,T335	Yes	T141,T334,T335	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T326,T322,T338	Yes	T326,T322,T338	OUTPUT
intr_rx_break_err_o	Yes	Yes	T326,T322,T338	Yes	T326,T322,T338	OUTPUT
intr_rx_timeout_o	Yes	Yes	T326,T322,T338	Yes	T326,T322,T338	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T326,T322,T338	Yes	T326,T322,T338	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T47,T17,T39	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T16,T323,T324	Yes	T16,T323,T324	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T16,T323,T324	Yes	T16,T323,T324	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T70,*T78,*T79	Yes	T70,T78,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T80,T8,T81	Yes	T80,T8,T81	INPUT
tl_i.a_valid	Yes	Yes	T16,T323,T324	Yes	T16,T323,T324	INPUT
tl_o.a_ready	Yes	Yes	T16,T323,T324	Yes	T16,T323,T324	OUTPUT
tl_o.d_error	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T16,T323,T324	Yes	T16,T323,T324	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T16,T323,T324	Yes	T16,T323,T324	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T16,T323,T324	Yes	T16,T323,T324	OUTPUT
tl_o.d_sink	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T16,*T323,*T324	Yes	T16,T323,T324	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T16,T323,T324	Yes	T16,T323,T324	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T148,T82,T360	Yes	T148,T82,T360	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T148,T82,T83	Yes	T148,T82,T83	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T148,T82,T83	Yes	T148,T82,T83	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T148,T82,T360	Yes	T148,T82,T360	OUTPUT
cio_rx_i	Yes	Yes	T16,T323,T324	Yes	T16,T323,T324	INPUT
cio_tx_o	Yes	Yes	T16,T323,T324	Yes	T16,T323,T324	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T16,T323,T324	Yes	T16,T323,T324	OUTPUT
intr_tx_empty_o	Yes	Yes	T16,T323,T324	Yes	T16,T323,T324	OUTPUT
intr_rx_watermark_o	Yes	Yes	T16,T323,T324	Yes	T16,T323,T324	OUTPUT
intr_tx_done_o	Yes	Yes	T16,T323,T324	Yes	T16,T323,T324	OUTPUT
intr_rx_overflow_o	Yes	Yes	T16,T323,T324	Yes	T16,T323,T324	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T326,T322,T338	Yes	T326,T322,T338	OUTPUT
intr_rx_break_err_o	Yes	Yes	T326,T322,T338	Yes	T326,T322,T338	OUTPUT
intr_rx_timeout_o	Yes	Yes	T326,T322,T338	Yes	T326,T322,T338	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T326,T322,T338	Yes	T326,T322,T338	OUTPUT

*Tests covering at least one bit in the range