Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	148732	1			T75	1033		T76	2		T77	6
values[2]	9430	1			T75	90		T81	1		T130	6
values[3]	3737	1			T75	31		T254	9		T503	10
values[4]	2213	1			T75	4		T254	4		T503	7
values[5]	1459	1			T75	2		T254	7		T503	6
values[6]	1120	1			T254	7		T503	8		T542	2
values[7]	840	1			T254	9		T503	6		T542	2
values[8]	764	1			T254	9		T503	8		T542	2
values[9]	650	1			T254	12		T503	6		T542	2
values[10]	577	1			T254	5		T503	1		T542	2
values[11]	428	1			T254	3		T542	2		T696	1
values[12]	452	1			T254	17		T542	2		T696	1
values[13]	434	1			T254	5		T542	2		T696	1
values[14]	432	1			T254	8		T542	2		T696	1
values[15]	392	1			T254	10		T542	2		T696	1
values[16]	441	1			T254	6		T542	2		T696	1
values[17]	401	1			T254	15		T542	2		T696	1
values[18]	412	1			T254	8		T542	2		T696	1
values[19]	406	1			T254	5		T542	2		T696	1
values[20]	363	1			T254	13		T542	3		T696	1
values[21]	408	1			T254	10		T542	2		T696	1
values[22]	423	1			T254	11		T542	2		T696	1
values[23]	331	1			T254	5		T542	2		T696	1
values[24]	310	1			T254	4		T542	2		T696	1
values[25]	372	1			T254	6		T542	2		T696	1
values[26]	315	1			T254	12		T542	2		T696	1
values[27]	346	1			T254	7		T542	2		T696	1
values[28]	318	1			T254	4		T542	2		T696	1
values[29]	347	1			T254	3		T542	2		T696	1
values[30]	375	1			T254	7		T542	2		T696	1
values[31]	402	1			T254	7		T542	2		T696	1
values[32]	429	1			T254	16		T542	2		T696	1
values[33]	335	1			T254	12		T542	2		T696	1
values[34]	326	1			T254	7		T542	2		T696	1
values[35]	380	1			T254	6		T542	2		T696	1
values[36]	319	1			T254	5		T542	2		T696	1
values[37]	300	1			T254	4		T542	2		T696	1
values[38]	329	1			T254	3		T542	2		T696	1
values[39]	327	1			T254	5		T542	2		T696	1
values[40]	341	1			T254	17		T542	2		T696	1
values[41]	326	1			T254	6		T542	2		T696	1
values[42]	306	1			T254	8		T542	2		T696	1
values[43]	328	1			T254	4		T542	2		T696	1
values[44]	323	1			T254	8		T542	2		T696	1
values[45]	332	1			T254	6		T542	2		T696	1
values[46]	380	1			T254	5		T542	2		T696	1
values[47]	362	1			T254	10		T542	2		T696	1
values[48]	335	1			T254	6		T542	2		T696	1
values[49]	312	1			T254	4		T542	2		T696	1
values[50]	331	1			T254	8		T542	2		T696	1
values[51]	321	1			T254	6		T542	2		T696	1
values[52]	302	1			T254	7		T542	2		T696	1
values[53]	312	1			T254	9		T542	2		T696	1
values[54]	319	1			T254	5		T542	2		T696	1
values[55]	304	1			T254	2		T542	2		T696	1
values[56]	243	1			T254	3		T542	2		T696	1
values[57]	281	1			T254	14		T542	2		T696	1
values[58]	212	1			T254	4		T542	2		T696	1
values[59]	234	1			T254	6		T542	2		T696	1
values[60]	219	1			T254	8		T542	2		T696	1
values[61]	204	1			T254	9		T542	2		T696	1
values[62]	216	1			T254	17		T542	2		T696	1
values[63]	172	1			T254	6		T542	2		T696	1
values[64]	184	1			T254	4		T542	2		T696	1
values[65]	217	1			T542	2		T696	1		T842	1
values[66]	139	1			T542	2		T696	1		T842	1
values[67]	141	1			T542	2		T696	1		T842	1
values[68]	127	1			T542	2		T696	1		T842	1
values[69]	120	1			T542	2		T696	1		T842	1
values[70]	92	1			T542	2		T696	1		T842	1
values[71]	93	1			T542	2		T696	1		T842	1
values[72]	103	1			T542	2		T696	1		T842	1
values[73]	140	1			T542	2		T696	1		T842	1
values[74]	103	1			T542	2		T696	1		T842	1
values[75]	97	1			T542	2		T696	1		T842	1
values[76]	93	1			T542	2		T696	1		T842	1
values[77]	75	1			T542	2		T696	1		T842	1
values[78]	76	1			T542	2		T696	1		T842	1
values[79]	73	1			T542	2		T696	1		T842	1
values[80]	83	1			T542	2		T696	1		T842	1
values[81]	61	1			T542	2		T696	1		T842	1
values[82]	60	1			T542	2		T696	1		T842	1
values[83]	88	1			T542	2		T696	1		T842	1
values[84]	79	1			T542	2		T696	1		T842	1
values[85]	76	1			T542	2		T696	1		T842	1
values[86]	69	1			T542	2		T696	1		T842	1
values[87]	66	1			T542	2		T696	1		T842	1
values[88]	67	1			T542	2		T696	1		T842	1
values[89]	61	1			T542	2		T696	1		T842	1
values[90]	71	1			T542	2		T696	1		T842	1
values[91]	66	1			T542	2		T696	1		T842	1
values[92]	63	1			T542	2		T696	1		T842	1
values[93]	81	1			T542	2		T696	1		T842	1
values[94]	91	1			T542	2		T696	1		T842	1
values[95]	87	1			T542	3		T696	1		T842	2
values[96]	73	1			T542	2		T696	1		T842	1
values[97]	85	1			T542	2		T696	1		T842	2
values[98]	72	1			T542	2		T696	1		T842	1
values[99]	78	1			T542	2		T696	1		T842	1
values[100]	70	1			T542	2		T696	1		T842	1
values[101]	88	1			T542	2		T696	1		T842	1
values[102]	75	1			T542	2		T696	1		T842	1
values[103]	76	1			T542	2		T696	1		T842	1
values[104]	87	1			T542	2		T696	1		T842	1
values[105]	69	1			T542	2		T696	2		T842	1
values[106]	84	1			T542	2		T696	3		T842	1
values[107]	85	1			T542	2		T696	1		T842	1
values[108]	79	1			T542	2		T696	1		T842	1
values[109]	55	1			T542	2		T696	1		T842	1
values[110]	61	1			T542	2		T696	4		T842	1
values[111]	69	1			T542	2		T696	1		T842	1
values[112]	78	1			T542	3		T696	1		T842	1
values[113]	95	1			T542	4		T696	2		T842	1
values[114]	82	1			T542	8		T696	1		T842	1
values[115]	84	1			T542	2		T696	3		T842	1
values[116]	76	1			T542	3		T696	1		T842	1
values[117]	105	1			T542	8		T696	13		T842	1
values[118]	75	1			T542	5		T696	1		T842	1
values[119]	67	1			T542	3		T696	3		T842	1
values[120]	74	1			T542	2		T696	2		T842	1
values[121]	72	1			T542	4		T696	1		T842	1
values[122]	80	1			T542	2		T696	2		T842	1
values[123]	84	1			T542	5		T696	4		T842	1
values[124]	84	1			T542	3		T696	3		T842	1
values[125]	115	1			T542	9		T696	1		T842	2
values[126]	143	1			T542	7		T696	2		T842	3
values[127]	938	1			T542	65		T696	25		T842	28
values[128]	7591	1			T542	627		T696	284		T842	286