Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.12	95.44	93.98	95.35		94.84	97.53	99.57

Total tests in report: 2931

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.62	39.62	44.90	44.90	43.07	43.07	31.94	31.94			57.96	57.96	59.44	59.44	0.39	0.39	/workspace/coverage/default/47.chip_sw_all_escalation_resets.3135079267
48.64	9.02	52.69	7.80	51.91	8.84	34.95	3.01			65.95	7.98	85.66	26.22	0.65	0.26	/workspace/coverage/default/2.chip_jtag_csr_rw.2865238910
55.31	6.67	62.96	10.26	56.31	4.40	41.96	7.01			66.22	0.27	85.66	0.00	18.73	18.08	/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.1662567963
60.43	5.12	74.20	11.24	63.65	7.34	43.99	2.03			76.33	10.12	85.66	0.00	18.73	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.3321351563
64.61	4.19	74.20	0.00	63.73	0.08	43.99	0.00			76.36	0.02	85.66	0.00	43.74	25.01	/workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.2484826561
68.03	3.42	80.07	5.86	68.00	4.28	47.81	3.82			78.36	2.00	90.21	4.55	43.74	0.00	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2504898819
70.94	2.91	80.07	0.01	68.03	0.02	65.16	17.34			78.38	0.02	90.21	0.00	43.79	0.05	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.338374156
73.83	2.89	80.07	0.00	68.10	0.07	65.16	0.00			78.38	0.00	90.21	0.00	61.09	17.30	/workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.648468158
76.56	2.72	82.87	2.79	75.44	7.35	65.52	0.36			83.34	4.97	90.21	0.00	61.96	0.87	/workspace/coverage/cover_reg_top/18.chip_csr_rw.2232267130
78.62	2.06	84.82	1.96	77.92	2.48	71.49	5.97			85.13	1.78	90.38	0.17	61.96	0.00	/workspace/coverage/default/1.rom_e2e_smoke.4008211669
80.21	1.60	84.82	0.00	77.92	0.00	71.49	0.00			85.13	0.00	90.38	0.00	71.54	9.59	/workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.510564365
81.78	1.57	85.11	0.29	78.08	0.16	79.94	8.45			85.31	0.18	90.73	0.35	71.54	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2804180213
83.14	1.35	85.11	0.00	78.09	0.01	79.94	0.00			85.31	0.00	90.73	0.00	79.65	8.11	/workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.2560979026
84.46	1.33	87.23	2.12	79.99	1.90	81.59	1.65			87.59	2.29	90.73	0.00	79.65	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.245994700
85.60	1.14	89.11	1.88	82.26	2.27	81.96	0.38			89.55	1.96	91.08	0.35	79.65	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.9048572
86.59	0.99	89.11	0.00	82.36	0.11	81.96	0.00			89.55	0.00	91.08	0.00	85.47	5.82	/workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.411989971
87.46	0.87	90.05	0.93	83.27	0.91	83.23	1.26			90.23	0.68	91.08	0.00	86.90	1.43	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3917429534
88.22	0.76	90.95	0.90	84.14	0.87	84.41	1.18			91.12	0.89	91.78	0.70	86.92	0.02	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2615870684
88.96	0.74	91.22	0.28	84.29	0.15	84.42	0.01			91.27	0.15	95.63	3.85	86.92	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.45610422
89.66	0.70	91.22	0.00	84.29	0.00	84.42	0.00			91.27	0.00	95.63	0.00	91.15	4.23	/workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.2310634556
90.31	0.65	92.13	0.91	85.55	1.25	85.05	0.63			92.36	1.09	95.63	0.00	91.15	0.00	/workspace/coverage/default/2.chip_sw_gpio.3841983930
90.84	0.53	92.80	0.66	86.10	0.56	86.44	1.39			92.94	0.58	95.63	0.00	91.15	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.569687094
91.33	0.49	92.81	0.01	88.62	2.51	86.44	0.00			92.94	0.00	95.63	0.00	91.56	0.41	/workspace/coverage/cover_reg_top/7.chip_tl_errors.3437406859
91.72	0.39	92.81	0.00	89.04	0.42	86.44	0.00			93.04	0.10	95.63	0.00	93.36	1.80	/workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.910749980
92.05	0.33	92.82	0.01	89.05	0.01	88.41	1.97			93.04	0.00	95.63	0.00	93.36	0.00	/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.836211628
92.34	0.29	92.82	0.00	89.31	0.27	88.41	0.00			93.09	0.05	95.63	0.00	94.79	1.43	/workspace/coverage/cover_reg_top/96.xbar_stress_all.1642227403
92.60	0.25	92.82	0.00	89.33	0.01	88.41	0.00			93.09	0.00	95.63	0.00	96.31	1.52	/workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.2171499727
92.81	0.21	93.12	0.31	89.51	0.19	88.91	0.50			93.37	0.28	95.63	0.00	96.32	0.01	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2838640373
93.01	0.19	93.18	0.06	89.53	0.01	89.65	0.74			93.38	0.01	95.98	0.35	96.32	0.00	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.301893962
93.16	0.16	93.18	0.00	89.53	0.00	90.60	0.95			93.38	0.00	95.98	0.00	96.32	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.2886093974
93.32	0.16	93.39	0.21	90.02	0.49	90.65	0.05			93.46	0.08	95.98	0.00	96.43	0.11	/workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.494263185
93.47	0.15	93.57	0.18	90.17	0.15	90.76	0.11			93.59	0.13	96.33	0.35	96.43	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.107556322
93.63	0.15	93.58	0.01	90.21	0.04	91.45	0.68			93.60	0.01	96.50	0.17	96.43	0.00	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2790748968
93.77	0.15	93.79	0.21	90.53	0.32	91.80	0.35			93.60	0.00	96.50	0.00	96.43	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2722274237
93.90	0.13	93.84	0.06	90.86	0.33	91.84	0.03			93.96	0.36	96.50	0.00	96.43	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2804439411
94.03	0.13	93.84	0.00	90.87	0.01	91.84	0.00			93.96	0.00	96.50	0.00	97.17	0.74	/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.100233586
94.13	0.10	93.95	0.11	90.96	0.08	91.92	0.08			94.00	0.05	96.50	0.00	97.45	0.28	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1265554729
94.22	0.09	93.95	0.00	90.96	0.00	92.47	0.55			94.00	0.00	96.50	0.00	97.45	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.604751603
94.31	0.08	93.95	0.00	90.96	0.01	92.96	0.49			94.00	0.00	96.50	0.00	97.45	0.00	/workspace/coverage/default/8.chip_sw_all_escalation_resets.2432026553
94.39	0.08	93.95	0.00	91.45	0.49	92.96	0.00			94.00	0.00	96.50	0.00	97.45	0.00	/workspace/coverage/cover_reg_top/17.chip_tl_errors.1234841300
94.46	0.08	93.95	0.00	91.45	0.00	92.96	0.00			94.00	0.00	96.50	0.00	97.92	0.47	/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.3645536561
94.54	0.08	94.06	0.11	91.59	0.15	93.09	0.13			94.09	0.08	96.50	0.00	97.92	0.00	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3509736506
94.62	0.08	94.20	0.14	91.64	0.05	93.10	0.01			94.14	0.06	96.68	0.17	97.96	0.04	/workspace/coverage/default/6.chip_sw_all_escalation_resets.151534738
94.69	0.07	94.26	0.06	91.67	0.03	93.22	0.12			94.17	0.03	96.85	0.17	97.97	0.01	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2798742279
94.76	0.07	94.26	0.00	91.86	0.18	93.22	0.01			94.39	0.21	96.85	0.00	97.97	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.724239610
94.81	0.05	94.26	0.00	91.86	0.00	93.48	0.26			94.39	0.00	96.85	0.00	98.00	0.04	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2768874988
94.85	0.05	94.29	0.02	91.96	0.10	93.49	0.01			94.43	0.04	96.85	0.00	98.11	0.11	/workspace/coverage/cover_reg_top/3.chip_csr_rw.3762657796
94.90	0.04	94.29	0.00	91.96	0.00	93.74	0.25			94.43	0.00	96.85	0.00	98.11	0.00	/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3320782421
94.94	0.04	94.34	0.06	92.08	0.12	93.74	0.00			94.49	0.06	96.85	0.00	98.11	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.2775252844
94.97	0.04	94.37	0.03	92.09	0.01	93.74	0.01			94.50	0.01	97.03	0.17	98.12	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.343608977
95.01	0.04	94.37	0.00	92.09	0.00	93.96	0.22			94.50	0.00	97.03	0.00	98.12	0.00	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2859161396
95.05	0.04	94.37	0.01	92.10	0.01	93.97	0.01			94.51	0.01	97.20	0.17	98.13	0.01	/workspace/coverage/default/43.chip_sw_all_escalation_resets.4063287308
95.08	0.04	94.38	0.01	92.11	0.01	93.97	0.00			94.52	0.01	97.38	0.17	98.14	0.01	/workspace/coverage/default/64.chip_sw_all_escalation_resets.3941159912
95.12	0.04	94.38	0.00	92.33	0.22	93.97	0.00			94.52	0.00	97.38	0.00	98.14	0.00	/workspace/coverage/cover_reg_top/2.chip_tl_errors.4241036217
95.15	0.03	94.38	0.00	92.41	0.09	93.97	0.00			94.53	0.02	97.38	0.00	98.24	0.09	/workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.558895628
95.18	0.03	94.45	0.07	92.41	0.00	94.08	0.12			94.54	0.01	97.38	0.00	98.24	0.00	/workspace/coverage/default/1.chip_tap_straps_testunlock0.1367914967
95.22	0.03	94.47	0.02	92.48	0.07	94.18	0.10			94.55	0.01	97.38	0.00	98.24	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.495685754
95.25	0.03	94.47	0.00	92.48	0.00	94.19	0.01			94.55	0.00	97.55	0.17	98.24	0.00	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.626436189
95.27	0.03	94.47	0.00	92.65	0.17	94.19	0.00			94.55	0.00	97.55	0.00	98.24	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.2504852580
95.30	0.03	94.47	0.00	92.65	0.00	94.35	0.16			94.55	0.00	97.55	0.00	98.24	0.00	/workspace/coverage/default/0.chip_sw_aes_enc.2273648911
95.33	0.03	94.54	0.07	92.68	0.03	94.35	0.01			94.60	0.05	97.55	0.00	98.24	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1040548237
95.35	0.02	94.54	0.00	92.68	0.00	94.50	0.15			94.60	0.00	97.55	0.00	98.24	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1844364812
95.38	0.02	94.57	0.03	92.72	0.05	94.55	0.05			94.62	0.02	97.55	0.00	98.24	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.799302714
95.40	0.02	94.59	0.02	92.75	0.03	94.56	0.02			94.62	0.00	97.55	0.00	98.31	0.07	/workspace/coverage/default/1.chip_sw_alert_test.1855675277
95.42	0.02	94.64	0.06	92.80	0.05	94.56	0.00			94.65	0.02	97.55	0.00	98.31	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.165440013
95.44	0.02	94.64	0.00	92.87	0.07	94.56	0.00			94.65	0.00	97.55	0.00	98.37	0.06	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.673768351
95.46	0.02	94.68	0.03	92.92	0.05	94.58	0.01			94.67	0.02	97.55	0.00	98.37	0.00	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2184138476
95.48	0.02	94.73	0.05	92.96	0.05	94.58	0.00			94.69	0.02	97.55	0.00	98.37	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1683316343
95.50	0.02	94.73	0.01	93.01	0.05	94.58	0.00			94.73	0.05	97.55	0.00	98.37	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.1734665164
95.51	0.02	94.73	0.00	93.04	0.03	94.58	0.00			94.75	0.02	97.55	0.00	98.43	0.06	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.849553812
95.53	0.02	94.73	0.00	93.15	0.10	94.58	0.00			94.75	0.00	97.55	0.00	98.43	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.2293776444
95.55	0.02	94.75	0.01	93.19	0.05	94.60	0.03			94.77	0.02	97.55	0.00	98.43	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1494120646
95.56	0.02	94.75	0.00	93.19	0.00	94.70	0.10			94.77	0.00	97.55	0.00	98.43	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.2104230925
95.58	0.02	94.75	0.01	93.27	0.07	94.70	0.00			94.78	0.02	97.55	0.00	98.43	0.00	/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.2794678176
95.60	0.02	94.75	0.00	93.27	0.00	94.70	0.00			94.78	0.00	97.55	0.00	98.52	0.09	/workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.3814947306
95.61	0.02	94.75	0.00	93.27	0.01	94.79	0.09			94.78	0.00	97.55	0.00	98.52	0.00	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1541716005
95.63	0.01	94.75	0.00	93.27	0.00	94.87	0.09			94.78	0.00	97.55	0.00	98.52	0.00	/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1653445770
95.64	0.01	94.75	0.00	93.35	0.08	94.87	0.00			94.78	0.00	97.55	0.00	98.52	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.2544632981
95.65	0.01	94.75	0.00	93.43	0.08	94.87	0.00			94.78	0.00	97.55	0.00	98.52	0.00	/workspace/coverage/cover_reg_top/13.chip_tl_errors.2083550062
95.67	0.01	94.77	0.01	93.47	0.04	94.87	0.00			94.81	0.02	97.55	0.00	98.52	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3479986070
95.68	0.01	94.77	0.00	93.48	0.01	94.87	0.00			94.81	0.00	97.55	0.00	98.58	0.06	/workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.1594315734
95.69	0.01	94.78	0.01	93.53	0.05	94.88	0.01			94.81	0.00	97.55	0.00	98.58	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.862173615
95.70	0.01	94.80	0.02	93.54	0.01	94.89	0.01			94.82	0.02	97.55	0.00	98.58	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1997903662
95.71	0.01	94.80	0.00	93.54	0.00	94.94	0.06			94.82	0.00	97.55	0.00	98.58	0.00	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2088605821
95.72	0.01	94.80	0.00	93.59	0.05	94.94	0.00			94.82	0.00	97.55	0.00	98.58	0.00	/workspace/coverage/cover_reg_top/42.xbar_stress_all.31635816
95.72	0.01	94.80	0.00	93.59	0.00	94.94	0.00			94.82	0.00	97.55	0.00	98.63	0.05	/workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.3632248519
95.73	0.01	94.80	0.00	93.59	0.00	94.99	0.04			94.82	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1442393152
95.74	0.01	94.80	0.00	93.62	0.03	94.99	0.00			94.82	0.00	97.55	0.00	98.64	0.01	/workspace/coverage/cover_reg_top/28.chip_tl_errors.660759963
95.74	0.01	94.82	0.01	93.62	0.00	95.01	0.03			94.82	0.00	97.55	0.00	98.64	0.00	/workspace/coverage/default/0.chip_sw_power_idle_load.134294558
95.75	0.01	94.82	0.00	93.66	0.04	95.01	0.00			94.82	0.00	97.55	0.00	98.64	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.1822124018
95.76	0.01	94.82	0.00	93.66	0.00	95.04	0.02			94.82	0.00	97.55	0.00	98.65	0.01	/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3654261043
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95.98	0.01	94.85	0.00	93.84	0.00	95.27	0.00			94.82	0.00	97.55	0.00	99.52	0.01	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1639365398
95.98	0.01	94.85	0.00	93.84	0.00	95.27	0.00			94.82	0.00	97.55	0.00	99.53	0.01	/workspace/coverage/default/82.chip_sw_all_escalation_resets.3397832030
95.98	0.01	94.85	0.00	93.84	0.00	95.27	0.00			94.82	0.00	97.55	0.00	99.54	0.01	/workspace/coverage/default/83.chip_sw_all_escalation_resets.168156268
95.98	0.01	94.85	0.00	93.84	0.00	95.27	0.00			94.82	0.00	97.55	0.00	99.55	0.01	/workspace/coverage/default/85.chip_sw_all_escalation_resets.2595640541
95.98	0.01	94.85	0.00	93.84	0.00	95.27	0.00			94.82	0.00	97.55	0.00	99.57	0.01	/workspace/coverage/default/86.chip_sw_all_escalation_resets.3598350101
95.99	0.01	94.85	0.00	93.85	0.01	95.27	0.00			94.82	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.382512031
95.99	0.01	94.85	0.00	93.86	0.01	95.27	0.00			94.82	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/30.xbar_stress_all.1047765676
95.99	0.01	94.85	0.00	93.87	0.01	95.27	0.00			94.82	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2686533133
95.99	0.01	94.85	0.00	93.88	0.01	95.27	0.00			94.82	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_gpio.4018397694
95.99	0.01	94.85	0.00	93.89	0.01	95.27	0.00			94.82	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3429836627
95.99	0.01	94.85	0.00	93.90	0.01	95.27	0.00			94.82	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx.622097615
96.00	0.01	94.85	0.00	93.90	0.00	95.27	0.01			94.83	0.01	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1471000807
96.00	0.01	94.85	0.00	93.90	0.00	95.28	0.01			94.83	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2503363528
96.00	0.01	94.85	0.00	93.90	0.00	95.29	0.01			94.83	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3784584245
96.00	0.01	94.85	0.00	93.90	0.00	95.29	0.00			94.84	0.01	97.55	0.00	99.57	0.00	/workspace/coverage/default/4.chip_tap_straps_dev.3435545050
96.00	0.01	94.85	0.00	93.91	0.01	95.29	0.00			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1150116637
96.00	0.01	94.85	0.00	93.92	0.01	95.29	0.00			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/14.chip_tl_errors.4157889023
96.00	0.01	94.85	0.00	93.92	0.01	95.29	0.00			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.1164537398
96.01	0.01	94.85	0.00	93.93	0.01	95.29	0.00			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.2850487957
96.01	0.01	94.85	0.00	93.94	0.01	95.29	0.00			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.735956827
96.01	0.01	94.85	0.00	93.94	0.01	95.29	0.00			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_gpio.2942296738
96.01	0.01	94.85	0.00	93.95	0.01	95.29	0.00			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2019259888
96.01	0.01	94.85	0.00	93.95	0.00	95.30	0.01			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.302972378
96.01	0.01	94.85	0.00	93.95	0.00	95.31	0.01			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2913933553
96.01	0.01	94.85	0.00	93.95	0.00	95.31	0.01			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1683624301
96.01	0.01	94.86	0.01	93.95	0.00	95.31	0.00			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2675312294
96.01	0.01	94.87	0.01	93.95	0.00	95.31	0.00			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.3513479527
96.02	0.01	94.87	0.00	93.95	0.00	95.32	0.01			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.1853469975
96.02	0.01	94.87	0.00	93.95	0.00	95.32	0.01			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_hmac_smoketest.2546520350
96.02	0.01	94.87	0.00	93.95	0.00	95.33	0.01			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3025395766
96.02	0.01	94.87	0.00	93.95	0.00	95.33	0.01			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2519329807
96.02	0.01	94.87	0.00	93.95	0.00	95.34	0.01			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1806692762
96.02	0.01	94.87	0.00	93.95	0.01	95.34	0.00			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.1923593382
96.02	0.01	94.87	0.00	93.96	0.01	95.34	0.00			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.316220221
96.02	0.01	94.87	0.00	93.96	0.01	95.34	0.00			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/16.chip_tl_errors.2800063857
96.02	0.01	94.87	0.00	93.96	0.01	95.34	0.00			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.3081481999
96.02	0.01	94.87	0.00	93.97	0.01	95.34	0.00			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.1470148252
96.02	0.01	94.87	0.00	93.97	0.01	95.34	0.00			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.4283158045
96.02	0.01	94.87	0.00	93.98	0.01	95.34	0.00			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1246956205
96.02	0.01	94.87	0.00	93.98	0.01	95.34	0.00			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3379734462
96.02	0.01	94.87	0.00	93.98	0.00	95.34	0.01			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/4.chip_tap_straps_testunlock0.2804274889
96.02	0.01	94.87	0.00	93.98	0.00	95.34	0.01			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1109255504
96.02	0.01	94.87	0.00	93.98	0.00	95.34	0.01			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.1726240482
96.02	0.01	94.87	0.00	93.98	0.00	95.35	0.01			94.84	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.4049201106

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.689209437
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.4032025594
/workspace/coverage/cover_reg_top/0.chip_csr_rw.1009324787
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.2629042780
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1076972883
/workspace/coverage/cover_reg_top/0.chip_tl_errors.1251428196
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.4263229038
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.673417956
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.685582335
/workspace/coverage/cover_reg_top/0.xbar_error_random.2249345932
/workspace/coverage/cover_reg_top/0.xbar_random.1026700162
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.421961909
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3041339684
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.4139429667
/workspace/coverage/cover_reg_top/0.xbar_same_source.1005426397
/workspace/coverage/cover_reg_top/0.xbar_smoke.2483631691
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.350449606
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1775832175
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.809481729
/workspace/coverage/cover_reg_top/0.xbar_stress_all.1294153628
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.163032547
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3997250461
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1037206969
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1950622928
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.4244319082
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1509651197
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1458354410
/workspace/coverage/cover_reg_top/1.chip_csr_rw.372052364
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2651082340
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.611481759
/workspace/coverage/cover_reg_top/1.chip_tl_errors.3658141254
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.512715932
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1805908601
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1725169219
/workspace/coverage/cover_reg_top/1.xbar_error_random.1872524017
/workspace/coverage/cover_reg_top/1.xbar_random.2463344605
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2089542841
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.660688397
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.209703866
/workspace/coverage/cover_reg_top/1.xbar_same_source.489141269
/workspace/coverage/cover_reg_top/1.xbar_smoke.1076794853
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1080097225
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2118856389
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2958485864
/workspace/coverage/cover_reg_top/1.xbar_stress_all.1312388869
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.2539678475
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2309915264
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3541901580
/workspace/coverage/cover_reg_top/10.chip_csr_rw.2551776330
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.2277195739
/workspace/coverage/cover_reg_top/10.chip_tl_errors.1317753999
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1390597650
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1451906163
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.745824724
/workspace/coverage/cover_reg_top/10.xbar_error_random.650638857
/workspace/coverage/cover_reg_top/10.xbar_random.965618811
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2591982295
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3454752713
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.31903837
/workspace/coverage/cover_reg_top/10.xbar_same_source.2660122914
/workspace/coverage/cover_reg_top/10.xbar_smoke.310569328
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.2760641488
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3696300783
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.479338589
/workspace/coverage/cover_reg_top/10.xbar_stress_all.91084768
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.1055105102
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1359389958
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.800790479
/workspace/coverage/cover_reg_top/11.chip_csr_rw.3287978729
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.1267591454
/workspace/coverage/cover_reg_top/11.chip_tl_errors.3257747344
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.819813419
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1457205466
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2645072354
/workspace/coverage/cover_reg_top/11.xbar_error_random.3433006106
/workspace/coverage/cover_reg_top/11.xbar_random.2770029833
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.855135584
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.4255549673
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.4186019272
/workspace/coverage/cover_reg_top/11.xbar_same_source.2061673914
/workspace/coverage/cover_reg_top/11.xbar_smoke.415842481
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.190790476
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.1588773697
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.1323012568
/workspace/coverage/cover_reg_top/11.xbar_stress_all.1681103535
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3583534252
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1228647822
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1723162144
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2203173099
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.2598660354
/workspace/coverage/cover_reg_top/12.chip_csr_rw.1208623310
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2787575940
/workspace/coverage/cover_reg_top/12.chip_tl_errors.2895208509
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.1582513716
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3542081714
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.4017691508
/workspace/coverage/cover_reg_top/12.xbar_error_random.457970787
/workspace/coverage/cover_reg_top/12.xbar_random.3537230499
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1706119165
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2847722226
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1873629724
/workspace/coverage/cover_reg_top/12.xbar_same_source.2627055147
/workspace/coverage/cover_reg_top/12.xbar_smoke.2790672454
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3068692087
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1328646637
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.420516351
/workspace/coverage/cover_reg_top/12.xbar_stress_all.932728035
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.4065214868
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.853974484
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2684693210
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.392180331
/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.1380659086
/workspace/coverage/cover_reg_top/13.chip_csr_rw.2712922732
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.3073322208
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.1937281712
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.393501838
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.2300342062
/workspace/coverage/cover_reg_top/13.xbar_error_random.3494763935
/workspace/coverage/cover_reg_top/13.xbar_random.3190623016
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.648779584
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3222300775
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.4077125923
/workspace/coverage/cover_reg_top/13.xbar_same_source.2658690522
/workspace/coverage/cover_reg_top/13.xbar_smoke.3120411858
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.1221550074
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.2001543669
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3717116575
/workspace/coverage/cover_reg_top/13.xbar_stress_all.3525518023
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.3454584701
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.2987534628
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.2332649978
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2285811218
/workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.74155834
/workspace/coverage/cover_reg_top/14.chip_csr_rw.1388696310
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.3840500956
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.3678552464
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3043419125
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/workspace/coverage/default/30.chip_sw_all_escalation_resets.1699486679
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.161529752
/workspace/coverage/default/33.chip_sw_all_escalation_resets.1358749823
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3725898983
/workspace/coverage/default/34.chip_sw_all_escalation_resets.508061720
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2859649123
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/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3081955853
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1785714643
/workspace/coverage/default/38.chip_sw_all_escalation_resets.3533102476
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/workspace/coverage/default/39.chip_sw_all_escalation_resets.2942612382
/workspace/coverage/default/4.chip_sw_all_escalation_resets.473366911
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1684324882
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/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.4169335370
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2573434865
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/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.265928348
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/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.429181648
/workspace/coverage/default/48.chip_sw_all_escalation_resets.3172671204
/workspace/coverage/default/49.chip_sw_all_escalation_resets.1700264322
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1545375256
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/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1067392742
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/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2197361140
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1820280365
/workspace/coverage/default/50.chip_sw_all_escalation_resets.1806730461
/workspace/coverage/default/51.chip_sw_all_escalation_resets.1999123610
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2276595944
/workspace/coverage/default/52.chip_sw_all_escalation_resets.904391936
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.808806856
/workspace/coverage/default/53.chip_sw_all_escalation_resets.1084369322
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3025351569
/workspace/coverage/default/54.chip_sw_all_escalation_resets.1945768372
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3503258711
/workspace/coverage/default/55.chip_sw_all_escalation_resets.1719336583
/workspace/coverage/default/56.chip_sw_all_escalation_resets.1000088505
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.914023180
/workspace/coverage/default/58.chip_sw_all_escalation_resets.1992869096
/workspace/coverage/default/59.chip_sw_all_escalation_resets.1104285707
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3211904193
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.960528538
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.1777418000
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.985843443
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3206645330
/workspace/coverage/default/60.chip_sw_all_escalation_resets.4056858663
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2003892316
/workspace/coverage/default/61.chip_sw_all_escalation_resets.3173060565
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2446426530
/workspace/coverage/default/62.chip_sw_all_escalation_resets.1013309438
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.341036653
/workspace/coverage/default/63.chip_sw_all_escalation_resets.3300102447
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1792008540
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.343162972
/workspace/coverage/default/65.chip_sw_all_escalation_resets.4271105248
/workspace/coverage/default/66.chip_sw_all_escalation_resets.602160957
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.587428405
/workspace/coverage/default/67.chip_sw_all_escalation_resets.926379866
/workspace/coverage/default/68.chip_sw_all_escalation_resets.3127714923
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.180443734
/workspace/coverage/default/69.chip_sw_all_escalation_resets.4250075327
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3691870636
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1191107823
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2711749540
/workspace/coverage/default/70.chip_sw_all_escalation_resets.3666165841
/workspace/coverage/default/71.chip_sw_all_escalation_resets.529920723
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.19885365
/workspace/coverage/default/72.chip_sw_all_escalation_resets.1066503982
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2828507248
/workspace/coverage/default/73.chip_sw_all_escalation_resets.4099369287
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1084779721
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2378928842
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3668918685
/workspace/coverage/default/75.chip_sw_all_escalation_resets.4060871175
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2015590456
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3520342848
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3902599466
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1292590172
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1565284078
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1551042667
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3050983631
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3338783905
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2517153068
/workspace/coverage/default/80.chip_sw_all_escalation_resets.2802831602
/workspace/coverage/default/81.chip_sw_all_escalation_resets.4047909458
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1377428613
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.747395413
/workspace/coverage/default/84.chip_sw_all_escalation_resets.1227046389
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2837661579
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1971320543
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3869998641
/workspace/coverage/default/87.chip_sw_all_escalation_resets.2218412568
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.4131261685
/workspace/coverage/default/88.chip_sw_all_escalation_resets.578997897
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1064429236
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1241672548
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.616608536
/workspace/coverage/default/9.chip_sw_all_escalation_resets.1305051129
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3983458711
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.533679469
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1664918839
/workspace/coverage/default/90.chip_sw_all_escalation_resets.1998117844
/workspace/coverage/default/91.chip_sw_all_escalation_resets.3891096264
/workspace/coverage/default/92.chip_sw_all_escalation_resets.1727418529
/workspace/coverage/default/93.chip_sw_all_escalation_resets.458492490
/workspace/coverage/default/94.chip_sw_all_escalation_resets.1826805181
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2998272040
/workspace/coverage/default/96.chip_sw_all_escalation_resets.198913484
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3120771101
/workspace/coverage/default/98.chip_sw_all_escalation_resets.1453536998
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2720544883
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1133993371
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1668305774
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2220812521
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.649717117
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3973954894
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1397018843
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1937994191
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2868984450
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1318469087

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Total test records in report: 2931

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3320782421			Jul 22 08:34:21 PM PDT 24	Jul 22 08:44:54 PM PDT 24	5676613900 ps
T2	/workspace/coverage/default/47.chip_sw_all_escalation_resets.3135079267			Jul 22 08:42:20 PM PDT 24	Jul 22 08:51:38 PM PDT 24	5362898000 ps
T3	/workspace/coverage/default/1.rom_e2e_smoke.4008211669			Jul 22 08:41:48 PM PDT 24	Jul 22 09:31:06 PM PDT 24	14838390864 ps
T34	/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.2554458467			Jul 22 08:32:31 PM PDT 24	Jul 22 08:38:18 PM PDT 24	3120591600 ps
T4	/workspace/coverage/default/2.chip_sw_spi_device_tpm.995765619			Jul 22 08:26:11 PM PDT 24	Jul 22 08:32:56 PM PDT 24	3091685911 ps
T86	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3286213996			Jul 22 08:24:30 PM PDT 24	Jul 22 08:28:02 PM PDT 24	2802161631 ps
T5	/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3654261043			Jul 22 08:44:44 PM PDT 24	Jul 22 08:50:30 PM PDT 24	3744070130 ps
T87	/workspace/coverage/default/0.chip_sw_example_manufacturer.2140790132			Jul 22 08:19:13 PM PDT 24	Jul 22 08:22:44 PM PDT 24	2774728664 ps
T88	/workspace/coverage/default/2.chip_sw_uart_smoketest.2652561705			Jul 22 08:40:03 PM PDT 24	Jul 22 08:43:27 PM PDT 24	2919098900 ps
T59	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3211904193			Jul 22 08:38:07 PM PDT 24	Jul 22 08:45:34 PM PDT 24	4029531536 ps
T33	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2408427036			Jul 22 08:15:35 PM PDT 24	Jul 22 08:24:52 PM PDT 24	5414510300 ps
T61	/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.3109459026			Jul 22 08:36:09 PM PDT 24	Jul 22 08:43:17 PM PDT 24	3892454540 ps
T411	/workspace/coverage/default/0.chip_sw_example_rom.2320766994			Jul 22 08:09:58 PM PDT 24	Jul 22 08:11:56 PM PDT 24	2698131550 ps
T182	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2790748968			Jul 22 08:23:32 PM PDT 24	Jul 22 08:31:52 PM PDT 24	4899549064 ps
T62	/workspace/coverage/default/67.chip_sw_all_escalation_resets.926379866			Jul 22 08:43:36 PM PDT 24	Jul 22 08:52:40 PM PDT 24	5725185136 ps
T60	/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2418154933			Jul 22 08:29:27 PM PDT 24	Jul 22 08:38:07 PM PDT 24	4165572716 ps
T6	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2804180213			Jul 22 08:12:46 PM PDT 24	Jul 22 08:58:04 PM PDT 24	25620523888 ps
T295	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.914023180			Jul 22 08:43:52 PM PDT 24	Jul 22 08:52:37 PM PDT 24	3911729544 ps
T296	/workspace/coverage/default/0.chip_sw_aes_enc.2273648911			Jul 22 08:14:56 PM PDT 24	Jul 22 08:19:36 PM PDT 24	3218944152 ps
T131	/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.154987551			Jul 22 08:17:03 PM PDT 24	Jul 22 08:24:05 PM PDT 24	4334308104 ps
T82	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2798742279			Jul 22 08:45:49 PM PDT 24	Jul 22 08:51:30 PM PDT 24	3488982360 ps
T93	/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3413850847			Jul 22 08:14:30 PM PDT 24	Jul 22 08:19:09 PM PDT 24	3089481720 ps
T94	/workspace/coverage/default/2.chip_sw_hmac_smoketest.1428713668			Jul 22 08:34:58 PM PDT 24	Jul 22 08:41:02 PM PDT 24	3168669816 ps
T7	/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1653445770			Jul 22 08:17:09 PM PDT 24	Jul 22 08:19:28 PM PDT 24	3442867457 ps
T95	/workspace/coverage/default/44.chip_sw_all_escalation_resets.92708475			Jul 22 08:41:15 PM PDT 24	Jul 22 08:51:26 PM PDT 24	5094479016 ps
T96	/workspace/coverage/default/1.chip_sw_kmac_app_rom.3007657206			Jul 22 08:20:12 PM PDT 24	Jul 22 08:23:15 PM PDT 24	3201425748 ps
T97	/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.836211628			Jul 22 08:38:27 PM PDT 24	Jul 22 09:54:09 PM PDT 24	21920265472 ps
T98	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1473239441			Jul 22 08:29:31 PM PDT 24	Jul 22 08:41:41 PM PDT 24	5847560380 ps
T99	/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.167251513			Jul 22 08:28:50 PM PDT 24	Jul 22 08:49:50 PM PDT 24	8591537920 ps
T100	/workspace/coverage/default/32.chip_sw_all_escalation_resets.2674976340			Jul 22 08:40:28 PM PDT 24	Jul 22 08:50:14 PM PDT 24	4825843580 ps
T46	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1683624301			Jul 22 08:32:04 PM PDT 24	Jul 22 08:36:50 PM PDT 24	2637879940 ps
T729	/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1241803911			Jul 22 08:12:57 PM PDT 24	Jul 22 08:23:41 PM PDT 24	4772608890 ps
T117	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.265089981			Jul 22 08:15:19 PM PDT 24	Jul 22 09:19:37 PM PDT 24	25262483767 ps
T125	/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.3947619607			Jul 22 08:27:46 PM PDT 24	Jul 22 08:32:57 PM PDT 24	5900537122 ps
T21	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3560168728			Jul 22 08:14:39 PM PDT 24	Jul 22 08:20:19 PM PDT 24	3124105506 ps
T8	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2838640373			Jul 22 08:24:56 PM PDT 24	Jul 22 10:04:17 PM PDT 24	23514435211 ps
T245	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.2887646576			Jul 22 08:30:16 PM PDT 24	Jul 22 08:39:27 PM PDT 24	3335312350 ps
T378	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1709753609			Jul 22 08:14:43 PM PDT 24	Jul 22 08:26:02 PM PDT 24	5416010276 ps
T43	/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2561721215			Jul 22 08:30:38 PM PDT 24	Jul 22 09:27:19 PM PDT 24	14823928049 ps
T379	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.888843575			Jul 22 08:31:43 PM PDT 24	Jul 22 08:36:47 PM PDT 24	3136319150 ps
T45	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2951791752			Jul 22 08:15:30 PM PDT 24	Jul 22 08:32:52 PM PDT 24	9003446204 ps
T380	/workspace/coverage/default/1.chip_sw_csrng_smoketest.2168904806			Jul 22 08:25:13 PM PDT 24	Jul 22 08:28:54 PM PDT 24	2888837950 ps
T12	/workspace/coverage/default/0.chip_sw_spi_device_pass_through.557619915			Jul 22 08:11:42 PM PDT 24	Jul 22 08:24:00 PM PDT 24	6305154858 ps
T119	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1652030974			Jul 22 08:33:28 PM PDT 24	Jul 22 08:39:42 PM PDT 24	3384534097 ps
T122	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2422058794			Jul 22 08:15:38 PM PDT 24	Jul 22 08:26:35 PM PDT 24	4875217146 ps
T129	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.338374156			Jul 22 08:30:03 PM PDT 24	Jul 22 09:26:46 PM PDT 24	12352021110 ps
T15	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.4224448379			Jul 22 08:38:42 PM PDT 24	Jul 22 08:49:18 PM PDT 24	4799514010 ps
T66	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.1799741353			Jul 22 08:33:22 PM PDT 24	Jul 22 08:44:27 PM PDT 24	6483731128 ps
T158	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2768874988			Jul 22 08:18:50 PM PDT 24	Jul 22 08:34:03 PM PDT 24	5761707800 ps
T409	/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2585392538			Jul 22 08:11:14 PM PDT 24	Jul 22 08:25:35 PM PDT 24	5637502512 ps
T126	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2657242987			Jul 22 08:20:49 PM PDT 24	Jul 22 08:53:31 PM PDT 24	20966200600 ps
T337	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3215498654			Jul 22 08:18:43 PM PDT 24	Jul 22 08:43:47 PM PDT 24	10761371082 ps
T358	/workspace/coverage/default/24.chip_sw_all_escalation_resets.1136368841			Jul 22 08:41:27 PM PDT 24	Jul 22 08:54:29 PM PDT 24	5947914296 ps
T164	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1265554729			Jul 22 08:27:22 PM PDT 24	Jul 22 08:56:30 PM PDT 24	9805881976 ps
T137	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1997903662			Jul 22 08:35:27 PM PDT 24	Jul 22 08:48:56 PM PDT 24	5731303674 ps
T67	/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.811229684			Jul 22 08:33:34 PM PDT 24	Jul 22 08:42:44 PM PDT 24	4932614056 ps
T172	/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.543806722			Jul 22 08:16:23 PM PDT 24	Jul 22 08:52:43 PM PDT 24	11765147128 ps
T232	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.619873367			Jul 22 08:17:53 PM PDT 24	Jul 22 09:11:53 PM PDT 24	15457193130 ps
T905	/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1822962635			Jul 22 08:22:05 PM PDT 24	Jul 22 08:26:58 PM PDT 24	2718197676 ps
T176	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.2886093974			Jul 22 08:15:11 PM PDT 24	Jul 22 09:33:40 PM PDT 24	44632089056 ps
T906	/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2441779539			Jul 22 08:13:35 PM PDT 24	Jul 22 08:23:47 PM PDT 24	5194869072 ps
T265	/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.960528538			Jul 22 08:39:51 PM PDT 24	Jul 22 10:13:58 PM PDT 24	26512182160 ps
T13	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3509736506			Jul 22 08:19:47 PM PDT 24	Jul 22 08:30:25 PM PDT 24	4589143613 ps
T118	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3622404925			Jul 22 08:25:58 PM PDT 24	Jul 22 09:26:30 PM PDT 24	24775213095 ps
T83	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3917429534			Jul 22 08:14:33 PM PDT 24	Jul 22 08:37:42 PM PDT 24	11651915536 ps
T185	/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.409389028			Jul 22 08:32:37 PM PDT 24	Jul 22 08:36:05 PM PDT 24	2676854215 ps
T123	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1268659474			Jul 22 08:21:06 PM PDT 24	Jul 22 08:32:12 PM PDT 24	4593654924 ps
T165	/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3668918685			Jul 22 08:43:42 PM PDT 24	Jul 22 08:51:10 PM PDT 24	4339499556 ps
T113	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1541716005			Jul 22 08:27:02 PM PDT 24	Jul 22 09:24:21 PM PDT 24	25037518480 ps
T162	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2829346461			Jul 22 08:12:39 PM PDT 24	Jul 22 08:23:38 PM PDT 24	4432783280 ps
T63	/workspace/coverage/default/0.chip_tap_straps_testunlock0.2638237731			Jul 22 08:13:35 PM PDT 24	Jul 22 08:16:34 PM PDT 24	2945749141 ps
T307	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.161529752			Jul 22 08:41:24 PM PDT 24	Jul 22 08:47:01 PM PDT 24	4176842656 ps
T173	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1583316370			Jul 22 08:32:09 PM PDT 24	Jul 22 08:55:48 PM PDT 24	8539049300 ps
T308	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2381041874			Jul 22 08:22:38 PM PDT 24	Jul 22 08:31:59 PM PDT 24	3323669502 ps
T250	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3379734462			Jul 22 08:20:27 PM PDT 24	Jul 22 08:56:20 PM PDT 24	11479000952 ps
T374	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.4146622993			Jul 22 08:41:04 PM PDT 24	Jul 22 08:56:12 PM PDT 24	10443467556 ps
T68	/workspace/coverage/default/1.rom_raw_unlock.558466132			Jul 22 08:27:47 PM PDT 24	Jul 22 08:32:24 PM PDT 24	5615076992 ps
T16	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2184138476			Jul 22 08:27:23 PM PDT 24	Jul 22 08:54:50 PM PDT 24	7632942140 ps
T375	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1224351138			Jul 22 08:41:42 PM PDT 24	Jul 22 08:47:48 PM PDT 24	4077507882 ps
T225	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3025395766			Jul 22 08:14:07 PM PDT 24	Jul 22 08:48:57 PM PDT 24	7701636416 ps
T376	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.584983734			Jul 22 08:40:44 PM PDT 24	Jul 22 08:47:05 PM PDT 24	4133258546 ps
T534	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1246956205			Jul 22 08:13:15 PM PDT 24	Jul 22 08:28:02 PM PDT 24	5008908232 ps
T246	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.2096795136			Jul 22 08:38:38 PM PDT 24	Jul 22 08:50:18 PM PDT 24	4488490908 ps
T458	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3359340092			Jul 22 08:31:43 PM PDT 24	Jul 22 08:37:19 PM PDT 24	2885597102 ps
T907	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1177045319			Jul 22 08:19:23 PM PDT 24	Jul 22 09:10:24 PM PDT 24	11450702972 ps
T704	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.4213040738			Jul 22 08:26:16 PM PDT 24	Jul 22 08:37:01 PM PDT 24	5024561620 ps
T132	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2299581009			Jul 22 08:31:01 PM PDT 24	Jul 22 08:38:02 PM PDT 24	4686664708 ps
T908	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1806692762			Jul 22 08:13:33 PM PDT 24	Jul 22 08:22:18 PM PDT 24	8060465944 ps
T686	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1382550072			Jul 22 08:10:34 PM PDT 24	Jul 22 08:30:44 PM PDT 24	11113549797 ps
T909	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2493334671			Jul 22 08:27:23 PM PDT 24	Jul 22 09:21:03 PM PDT 24	15394122924 ps
T169	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.59785567			Jul 22 08:30:25 PM PDT 24	Jul 22 09:02:57 PM PDT 24	25772494173 ps
T825	/workspace/coverage/default/28.chip_sw_all_escalation_resets.425860222			Jul 22 08:41:30 PM PDT 24	Jul 22 08:50:24 PM PDT 24	4560336534 ps
T18	/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2263172060			Jul 22 08:36:12 PM PDT 24	Jul 22 08:42:53 PM PDT 24	4998337680 ps
T793	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.341036653			Jul 22 08:44:37 PM PDT 24	Jul 22 08:50:07 PM PDT 24	3916619632 ps
T910	/workspace/coverage/default/0.chip_sw_example_flash.632606			Jul 22 08:12:31 PM PDT 24	Jul 22 08:17:01 PM PDT 24	2618248696 ps
T44	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2571915966			Jul 22 08:22:32 PM PDT 24	Jul 22 09:20:59 PM PDT 24	15238046289 ps
T318	/workspace/coverage/default/3.chip_sw_all_escalation_resets.3742482360			Jul 22 08:37:32 PM PDT 24	Jul 22 08:49:02 PM PDT 24	5810124344 ps
T227	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3952958481			Jul 22 08:21:49 PM PDT 24	Jul 22 08:45:48 PM PDT 24	9640073992 ps
T789	/workspace/coverage/default/49.chip_sw_all_escalation_resets.1700264322			Jul 22 08:41:07 PM PDT 24	Jul 22 08:53:04 PM PDT 24	5595837208 ps
T352	/workspace/coverage/default/0.chip_sw_flash_crash_alert.3667495252			Jul 22 08:16:08 PM PDT 24	Jul 22 08:30:55 PM PDT 24	5263209860 ps
T70	/workspace/coverage/default/3.chip_tap_straps_dev.122827320			Jul 22 08:36:13 PM PDT 24	Jul 22 08:50:33 PM PDT 24	7898851965 ps
T536	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2941844942			Jul 22 08:26:11 PM PDT 24	Jul 22 08:30:41 PM PDT 24	2504635944 ps
T192	/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.961515084			Jul 22 08:41:10 PM PDT 24	Jul 22 08:52:44 PM PDT 24	10215705848 ps
T462	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.54114062			Jul 22 08:35:05 PM PDT 24	Jul 22 09:43:19 PM PDT 24	28771157550 ps
T214	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3541891914			Jul 22 08:28:56 PM PDT 24	Jul 22 08:54:48 PM PDT 24	7433476216 ps
T677	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3081955853			Jul 22 08:41:09 PM PDT 24	Jul 22 08:47:37 PM PDT 24	3553586884 ps
T415	/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.587428405			Jul 22 08:47:09 PM PDT 24	Jul 22 08:52:59 PM PDT 24	4054957994 ps
T911	/workspace/coverage/default/0.chip_sw_example_concurrency.4244436149			Jul 22 08:18:22 PM PDT 24	Jul 22 08:23:23 PM PDT 24	3557795420 ps
T78	/workspace/coverage/default/0.rom_raw_unlock.3571135388			Jul 22 08:16:03 PM PDT 24	Jul 22 08:20:06 PM PDT 24	4350781868 ps
T709	/workspace/coverage/default/52.chip_sw_all_escalation_resets.904391936			Jul 22 08:44:46 PM PDT 24	Jul 22 08:53:21 PM PDT 24	5257853300 ps
T221	/workspace/coverage/default/1.chip_sw_uart_tx_rx.3978864186			Jul 22 08:18:30 PM PDT 24	Jul 22 08:29:52 PM PDT 24	4692870488 ps
T703	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2222788651			Jul 22 08:13:13 PM PDT 24	Jul 22 08:19:51 PM PDT 24	3736494152 ps
T705	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1064429236			Jul 22 08:46:37 PM PDT 24	Jul 22 08:51:36 PM PDT 24	3308106224 ps
T912	/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3383512569			Jul 22 08:34:44 PM PDT 24	Jul 22 08:40:39 PM PDT 24	3439936392 ps
T708	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1971320543			Jul 22 08:45:55 PM PDT 24	Jul 22 08:51:52 PM PDT 24	3899467848 ps
T219	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2787845087			Jul 22 08:15:15 PM PDT 24	Jul 22 08:28:37 PM PDT 24	4912743380 ps
T706	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1565284078			Jul 22 08:44:58 PM PDT 24	Jul 22 08:52:13 PM PDT 24	4272761792 ps
T913	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1117107473			Jul 22 08:12:57 PM PDT 24	Jul 22 08:32:13 PM PDT 24	6811539726 ps
T914	/workspace/coverage/default/1.chip_sw_aes_smoketest.2171290192			Jul 22 08:24:30 PM PDT 24	Jul 22 08:29:52 PM PDT 24	2767409466 ps
T915	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3275189083			Jul 22 08:26:11 PM PDT 24	Jul 22 08:32:00 PM PDT 24	3267703090 ps
T216	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1874090786			Jul 22 08:26:05 PM PDT 24	Jul 22 08:53:45 PM PDT 24	13284084349 ps
T916	/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1998975600			Jul 22 08:40:31 PM PDT 24	Jul 22 08:45:41 PM PDT 24	3122213026 ps
T17	/workspace/coverage/default/0.chip_sw_gpio_smoketest.2526163292			Jul 22 08:15:38 PM PDT 24	Jul 22 08:20:02 PM PDT 24	3050919906 ps
T412	/workspace/coverage/default/82.chip_sw_all_escalation_resets.3397832030			Jul 22 08:44:58 PM PDT 24	Jul 22 08:55:26 PM PDT 24	5022899140 ps
T455	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2350268064			Jul 22 08:29:11 PM PDT 24	Jul 22 08:47:41 PM PDT 24	6132053110 ps
T180	/workspace/coverage/default/2.rom_e2e_shutdown_output.3637768731			Jul 22 08:40:54 PM PDT 24	Jul 22 09:38:38 PM PDT 24	25674851842 ps
T159	/workspace/coverage/default/1.chip_plic_all_irqs_10.569687094			Jul 22 08:22:48 PM PDT 24	Jul 22 08:31:46 PM PDT 24	3797572108 ps
T181	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3641405108			Jul 22 08:19:13 PM PDT 24	Jul 22 08:35:20 PM PDT 24	10627971378 ps
T456	/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1840430935			Jul 22 08:33:53 PM PDT 24	Jul 22 08:54:47 PM PDT 24	6120793542 ps
T353	/workspace/coverage/default/9.chip_sw_all_escalation_resets.1305051129			Jul 22 08:38:55 PM PDT 24	Jul 22 08:50:18 PM PDT 24	4911048084 ps
T377	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1095169523			Jul 22 08:32:41 PM PDT 24	Jul 22 09:54:21 PM PDT 24	15459458500 ps
T917	/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.349393411			Jul 22 08:24:10 PM PDT 24	Jul 22 08:27:29 PM PDT 24	2940619056 ps
T147	/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3409045998			Jul 22 08:23:12 PM PDT 24	Jul 22 08:31:34 PM PDT 24	6312935730 ps
T918	/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.649985984			Jul 22 08:39:09 PM PDT 24	Jul 22 08:47:46 PM PDT 24	7930548041 ps
T919	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.610406543			Jul 22 08:11:27 PM PDT 24	Jul 22 08:21:39 PM PDT 24	4076915800 ps
T920	/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3983458711			Jul 22 08:40:27 PM PDT 24	Jul 22 09:30:31 PM PDT 24	16440816326 ps
T153	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3249434224			Jul 22 08:36:46 PM PDT 24	Jul 22 08:46:26 PM PDT 24	4519837450 ps
T84	/workspace/coverage/default/1.chip_sw_alert_handler_entropy.210496777			Jul 22 08:22:56 PM PDT 24	Jul 22 08:29:00 PM PDT 24	3045795935 ps
T177	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.1844364812			Jul 22 08:19:45 PM PDT 24	Jul 22 09:54:37 PM PDT 24	48077939820 ps
T814	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2828507248			Jul 22 08:43:36 PM PDT 24	Jul 22 08:51:09 PM PDT 24	4030296076 ps
T755	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1041101224			Jul 22 08:25:02 PM PDT 24	Jul 22 08:32:05 PM PDT 24	3412946856 ps
T921	/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1191107823			Jul 22 08:37:34 PM PDT 24	Jul 22 08:46:21 PM PDT 24	6942599846 ps
T19	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2615870684			Jul 22 08:16:46 PM PDT 24	Jul 22 08:42:06 PM PDT 24	23524287864 ps
T103	/workspace/coverage/default/1.chip_sw_rv_timer_irq.145412806			Jul 22 08:22:34 PM PDT 24	Jul 22 08:26:47 PM PDT 24	2499810760 ps
T104	/workspace/coverage/default/15.chip_sw_all_escalation_resets.1720088116			Jul 22 08:39:31 PM PDT 24	Jul 22 08:49:16 PM PDT 24	4280226656 ps
T22	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.107556322			Jul 22 08:19:31 PM PDT 24	Jul 22 08:49:32 PM PDT 24	25013235560 ps
T105	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3436711782			Jul 22 08:22:17 PM PDT 24	Jul 22 08:31:12 PM PDT 24	4455883424 ps
T106	/workspace/coverage/default/84.chip_sw_all_escalation_resets.1227046389			Jul 22 08:45:57 PM PDT 24	Jul 22 08:54:21 PM PDT 24	4318477208 ps
T107	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2231186225			Jul 22 08:45:50 PM PDT 24	Jul 22 08:51:42 PM PDT 24	3762222356 ps
T108	/workspace/coverage/default/1.chip_sw_hmac_multistream.11485667			Jul 22 08:32:47 PM PDT 24	Jul 22 08:59:20 PM PDT 24	8257736680 ps
T109	/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.745558655			Jul 22 08:21:03 PM PDT 24	Jul 22 08:30:38 PM PDT 24	4799101392 ps
T110	/workspace/coverage/default/10.chip_sw_all_escalation_resets.2333361061			Jul 22 08:40:03 PM PDT 24	Jul 22 08:52:55 PM PDT 24	6360693400 ps
T89	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1545375256			Jul 22 08:38:43 PM PDT 24	Jul 22 08:44:50 PM PDT 24	3335279322 ps
T114	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1518890633			Jul 22 08:28:37 PM PDT 24	Jul 22 08:37:48 PM PDT 24	19304034524 ps
T922	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.653220196			Jul 22 08:17:42 PM PDT 24	Jul 22 08:29:54 PM PDT 24	7102217340 ps
T9	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.9048572			Jul 22 08:26:25 PM PDT 24	Jul 22 08:33:12 PM PDT 24	3371996555 ps
T923	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.3479173923			Jul 22 08:31:18 PM PDT 24	Jul 22 09:23:47 PM PDT 24	15284714154 ps
T702	/workspace/coverage/default/2.chip_sw_all_escalation_resets.1321022999			Jul 22 08:41:35 PM PDT 24	Jul 22 08:51:54 PM PDT 24	6129201564 ps
T58	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1494120646			Jul 22 08:10:38 PM PDT 24	Jul 22 08:17:34 PM PDT 24	4080838086 ps
T924	/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2833207613			Jul 22 08:37:41 PM PDT 24	Jul 22 09:21:51 PM PDT 24	11341545126 ps
T226	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3484462884			Jul 22 08:12:55 PM PDT 24	Jul 22 09:18:34 PM PDT 24	13960825144 ps
T222	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1982464068			Jul 22 08:36:49 PM PDT 24	Jul 22 08:45:15 PM PDT 24	5068983618 ps
T925	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2478408517			Jul 22 08:30:46 PM PDT 24	Jul 22 08:53:56 PM PDT 24	11269387961 ps
T276	/workspace/coverage/default/2.rom_volatile_raw_unlock.1941499699			Jul 22 08:33:55 PM PDT 24	Jul 22 08:35:46 PM PDT 24	1880829468 ps
T146	/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1844890292			Jul 22 08:25:32 PM PDT 24	Jul 22 08:34:17 PM PDT 24	6121173668 ps
T124	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.186797752			Jul 22 08:35:16 PM PDT 24	Jul 22 08:46:45 PM PDT 24	4597782528 ps
T359	/workspace/coverage/default/5.chip_sw_all_escalation_resets.1510101985			Jul 22 08:40:00 PM PDT 24	Jul 22 08:51:34 PM PDT 24	4817093768 ps
T10	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.724239610			Jul 22 08:17:05 PM PDT 24	Jul 22 08:23:23 PM PDT 24	3145848547 ps
T926	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.2876822136			Jul 22 08:21:43 PM PDT 24	Jul 22 08:29:38 PM PDT 24	3878492438 ps
T735	/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.3283429878			Jul 22 08:29:51 PM PDT 24	Jul 22 08:51:38 PM PDT 24	8099997106 ps
T170	/workspace/coverage/default/8.chip_sw_all_escalation_resets.2432026553			Jul 22 08:41:08 PM PDT 24	Jul 22 08:50:09 PM PDT 24	5269450992 ps
T756	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.2675817069			Jul 22 08:32:25 PM PDT 24	Jul 22 08:50:32 PM PDT 24	7074240818 ps
T127	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.1279790289			Jul 22 08:32:27 PM PDT 24	Jul 22 08:56:38 PM PDT 24	7351735660 ps
T261	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2078433300			Jul 22 08:17:14 PM PDT 24	Jul 22 08:20:59 PM PDT 24	2518429512 ps
T927	/workspace/coverage/default/1.chip_sw_otbn_randomness.693258493			Jul 22 08:25:27 PM PDT 24	Jul 22 08:41:02 PM PDT 24	5850190474 ps
T360	/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.783044033			Jul 22 08:09:39 PM PDT 24	Jul 22 08:17:52 PM PDT 24	5478404782 ps
T168	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1442393152			Jul 22 08:17:35 PM PDT 24	Jul 22 08:19:45 PM PDT 24	2652237288 ps
T827	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3025351569			Jul 22 08:42:50 PM PDT 24	Jul 22 08:49:31 PM PDT 24	3894668392 ps
T183	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2874379305			Jul 22 08:34:17 PM PDT 24	Jul 22 08:48:25 PM PDT 24	7555099608 ps
T215	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.800223950			Jul 22 08:28:29 PM PDT 24	Jul 22 08:40:00 PM PDT 24	4249951520 ps
T258	/workspace/coverage/default/0.chip_sw_plic_sw_irq.2272679599			Jul 22 08:12:25 PM PDT 24	Jul 22 08:18:25 PM PDT 24	3377037032 ps
T460	/workspace/coverage/default/0.chip_sw_kmac_entropy.3836954151			Jul 22 08:11:29 PM PDT 24	Jul 22 08:16:59 PM PDT 24	3061954820 ps
T928	/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.95553700			Jul 22 08:12:05 PM PDT 24	Jul 22 08:19:34 PM PDT 24	3474497008 ps
T154	/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1961187989			Jul 22 08:30:06 PM PDT 24	Jul 22 08:39:33 PM PDT 24	3994425640 ps
T220	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1041824001			Jul 22 08:12:24 PM PDT 24	Jul 22 08:22:15 PM PDT 24	4507559778 ps
T14	/workspace/coverage/default/2.chip_sw_spi_device_pass_through.1461816962			Jul 22 08:28:22 PM PDT 24	Jul 22 08:38:28 PM PDT 24	6337712342 ps
T929	/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2237362345			Jul 22 08:14:17 PM PDT 24	Jul 22 08:24:01 PM PDT 24	5433925428 ps
T207	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2193772514			Jul 22 08:22:43 PM PDT 24	Jul 22 08:28:33 PM PDT 24	3274748696 ps
T314	/workspace/coverage/default/2.chip_plic_all_irqs_20.3321351563			Jul 22 08:33:46 PM PDT 24	Jul 22 08:49:20 PM PDT 24	5274118530 ps
T155	/workspace/coverage/default/0.chip_sw_power_idle_load.134294558			Jul 22 08:17:16 PM PDT 24	Jul 22 08:28:03 PM PDT 24	4007042000 ps
T217	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1861414810			Jul 22 08:38:11 PM PDT 24	Jul 22 08:45:56 PM PDT 24	3980616217 ps
T26	/workspace/coverage/default/2.chip_sw_gpio.3841983930			Jul 22 08:28:42 PM PDT 24	Jul 22 08:35:32 PM PDT 24	3499386503 ps
T930	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.211738055			Jul 22 08:17:30 PM PDT 24	Jul 22 08:31:13 PM PDT 24	4315160580 ps
T350	/workspace/coverage/default/2.chip_sw_pattgen_ios.296956564			Jul 22 08:24:46 PM PDT 24	Jul 22 08:27:44 PM PDT 24	2522953720 ps
T262	/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.2952538248			Jul 22 08:18:13 PM PDT 24	Jul 22 09:08:50 PM PDT 24	31521751866 ps
T189	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3275818768			Jul 22 08:15:29 PM PDT 24	Jul 22 08:22:34 PM PDT 24	3909376780 ps
T128	/workspace/coverage/default/2.chip_sw_edn_boot_mode.2153980017			Jul 22 08:30:53 PM PDT 24	Jul 22 08:42:31 PM PDT 24	3249078648 ps
T931	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.1418367765			Jul 22 08:17:45 PM PDT 24	Jul 22 08:25:01 PM PDT 24	5454322784 ps
T338	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.60433085			Jul 22 08:36:18 PM PDT 24	Jul 22 08:44:00 PM PDT 24	3613509332 ps
T333	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.799302714			Jul 22 08:18:25 PM PDT 24	Jul 22 08:52:04 PM PDT 24	8978525580 ps
T218	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3348439673			Jul 22 08:23:04 PM PDT 24	Jul 22 08:32:50 PM PDT 24	3984742856 ps
T120	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2080948183			Jul 22 08:14:11 PM PDT 24	Jul 22 08:41:22 PM PDT 24	9356678957 ps
T932	/workspace/coverage/default/2.rom_e2e_smoke.3120927026			Jul 22 08:38:51 PM PDT 24	Jul 22 09:31:20 PM PDT 24	14537636120 ps
T351	/workspace/coverage/default/0.chip_sw_pattgen_ios.3513479527			Jul 22 08:19:20 PM PDT 24	Jul 22 08:22:34 PM PDT 24	2429449134 ps
T79	/workspace/coverage/default/2.chip_jtag_mem_access.1906529968			Jul 22 08:24:55 PM PDT 24	Jul 22 08:49:15 PM PDT 24	13860173628 ps
T57	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3097789952			Jul 22 08:33:28 PM PDT 24	Jul 22 08:42:11 PM PDT 24	7087238028 ps
T35	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1396402080			Jul 22 08:11:12 PM PDT 24	Jul 22 08:17:00 PM PDT 24	3392447750 ps
T277	/workspace/coverage/default/0.rom_e2e_shutdown_output.1101997649			Jul 22 08:21:08 PM PDT 24	Jul 22 09:23:34 PM PDT 24	22584405192 ps
T745	/workspace/coverage/default/87.chip_sw_all_escalation_resets.2218412568			Jul 22 08:46:04 PM PDT 24	Jul 22 08:57:00 PM PDT 24	5680201292 ps
T933	/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2969345342			Jul 22 08:32:50 PM PDT 24	Jul 22 08:42:07 PM PDT 24	4314110080 ps
T934	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1710917726			Jul 22 08:25:09 PM PDT 24	Jul 22 08:28:23 PM PDT 24	2295351314 ps
T388	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1369071819			Jul 22 08:23:25 PM PDT 24	Jul 22 10:06:10 PM PDT 24	23278160516 ps
T347	/workspace/coverage/default/0.chip_sw_uart_tx_rx.622097615			Jul 22 08:12:40 PM PDT 24	Jul 22 08:24:46 PM PDT 24	3948575218 ps
T329	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2686533133			Jul 22 08:15:08 PM PDT 24	Jul 22 08:43:25 PM PDT 24	6989379960 ps
T247	/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.960198585			Jul 22 08:16:41 PM PDT 24	Jul 22 08:25:23 PM PDT 24	4799443480 ps
T269	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.995820026			Jul 22 08:39:45 PM PDT 24	Jul 22 08:46:09 PM PDT 24	4183405952 ps
T270	/workspace/coverage/default/0.chip_sw_kmac_idle.460538246			Jul 22 08:15:58 PM PDT 24	Jul 22 08:20:28 PM PDT 24	2155146904 ps
T156	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1308153879			Jul 22 08:31:47 PM PDT 24	Jul 22 09:31:58 PM PDT 24	17272018364 ps
T271	/workspace/coverage/default/54.chip_sw_all_escalation_resets.1945768372			Jul 22 08:45:26 PM PDT 24	Jul 22 08:54:19 PM PDT 24	5100323344 ps
T272	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3479986070			Jul 22 08:28:46 PM PDT 24	Jul 22 08:41:00 PM PDT 24	4054715083 ps
T273	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3653293711			Jul 22 08:12:29 PM PDT 24	Jul 22 08:35:26 PM PDT 24	6453887582 ps
T157	/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.301893962			Jul 22 08:18:10 PM PDT 24	Jul 22 11:13:03 PM PDT 24	57740739950 ps
T274	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3464828952			Jul 22 08:16:13 PM PDT 24	Jul 22 08:42:50 PM PDT 24	13289512292 ps
T275	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3388633946			Jul 22 08:42:16 PM PDT 24	Jul 22 08:49:16 PM PDT 24	3025733320 ps
T317	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3691870636			Jul 22 08:37:32 PM PDT 24	Jul 22 08:45:01 PM PDT 24	4077886174 ps
T935	/workspace/coverage/default/0.rom_e2e_asm_init_dev.1934389537			Jul 22 08:19:39 PM PDT 24	Jul 22 09:17:14 PM PDT 24	15608112138 ps
T203	/workspace/coverage/default/2.chip_sw_inject_scramble_seed.1731733861			Jul 22 08:28:22 PM PDT 24	Jul 22 11:30:54 PM PDT 24	63762574981 ps
T23	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3050532242			Jul 22 08:41:52 PM PDT 24	Jul 22 08:48:36 PM PDT 24	3245204758 ps
T748	/workspace/coverage/default/48.chip_sw_all_escalation_resets.3172671204			Jul 22 08:40:29 PM PDT 24	Jul 22 08:49:55 PM PDT 24	4518050112 ps
T349	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3203740177			Jul 22 08:39:08 PM PDT 24	Jul 22 09:15:16 PM PDT 24	12674680828 ps
T828	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.20921662			Jul 22 08:40:46 PM PDT 24	Jul 22 08:47:11 PM PDT 24	3508454936 ps
T936	/workspace/coverage/default/2.rom_e2e_asm_init_dev.1612276526			Jul 22 08:38:23 PM PDT 24	Jul 22 09:37:59 PM PDT 24	15613676784 ps
T27	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.2775252844			Jul 22 08:11:04 PM PDT 24	Jul 22 08:15:40 PM PDT 24	2949971696 ps
T417	/workspace/coverage/default/1.chip_sw_edn_sw_mode.1197346163			Jul 22 08:19:27 PM PDT 24	Jul 22 08:49:19 PM PDT 24	8321172664 ps
T357	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.328217953			Jul 22 08:17:28 PM PDT 24	Jul 22 08:25:58 PM PDT 24	4083630174 ps
T418	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3988072644			Jul 22 08:28:20 PM PDT 24	Jul 22 08:34:36 PM PDT 24	4337174220 ps
T419	/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.786180048			Jul 22 08:26:33 PM PDT 24	Jul 22 08:49:51 PM PDT 24	8761844180 ps
T244	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2960681012			Jul 22 08:41:05 PM PDT 24	Jul 22 08:47:13 PM PDT 24	3836630824 ps
T420	/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.1391678956			Jul 22 08:20:44 PM PDT 24	Jul 22 08:49:18 PM PDT 24	8172714656 ps
T421	/workspace/coverage/default/77.chip_sw_all_escalation_resets.3520342848			Jul 22 08:44:31 PM PDT 24	Jul 22 08:53:25 PM PDT 24	5457524562 ps
T263	/workspace/coverage/default/0.rom_e2e_jtag_debug_dev.1635790124			Jul 22 08:17:02 PM PDT 24	Jul 22 08:53:12 PM PDT 24	11295778626 ps
T422	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2695793662			Jul 22 08:39:56 PM PDT 24	Jul 22 08:47:39 PM PDT 24	4000951720 ps
T726	/workspace/coverage/default/2.chip_sw_hmac_oneshot.4002340889			Jul 22 08:31:09 PM PDT 24	Jul 22 08:36:02 PM PDT 24	2817381412 ps
T343	/workspace/coverage/default/2.chip_sw_hmac_enc.802497532			Jul 22 08:31:03 PM PDT 24	Jul 22 08:35:38 PM PDT 24	2749480518 ps
T796	/workspace/coverage/default/94.chip_sw_all_escalation_resets.1826805181			Jul 22 08:46:07 PM PDT 24	Jul 22 08:54:53 PM PDT 24	5933205870 ps
T354	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.302972378			Jul 22 08:12:04 PM PDT 24	Jul 22 08:22:29 PM PDT 24	18905953400 ps
T208	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2427589330			Jul 22 08:15:53 PM PDT 24	Jul 22 08:44:19 PM PDT 24	24478356928 ps
T391	/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.14507117			Jul 22 08:14:11 PM PDT 24	Jul 22 08:34:23 PM PDT 24	8586192288 ps
T937	/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1684324882			Jul 22 08:37:31 PM PDT 24	Jul 22 08:44:20 PM PDT 24	7022021076 ps
T238	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.604751603			Jul 22 08:30:15 PM PDT 24	Jul 22 08:39:55 PM PDT 24	5479310854 ps