Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.pattgen_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	146129	1			T75	1091		T76	3		T77	6
values[2]	8896	1			T75	61		T130	6		T254	1
values[3]	3145	1			T75	2		T430	23		T542	1
values[4]	1849	1			T430	7		T542	1		T541	2
values[5]	1255	1			T430	10		T542	1		T845	1
values[6]	956	1			T542	1		T845	1		T862	5
values[7]	738	1			T542	1		T845	1		T862	10
values[8]	646	1			T542	1		T845	1		T862	4
values[9]	581	1			T542	1		T845	1		T862	11
values[10]	510	1			T542	1		T845	1		T862	4
values[11]	469	1			T542	1		T845	1		T862	5
values[12]	426	1			T542	1		T845	1		T862	6
values[13]	380	1			T542	1		T845	1		T862	5
values[14]	381	1			T542	1		T845	1		T862	3
values[15]	479	1			T542	1		T845	1		T862	11
values[16]	364	1			T542	1		T845	1		T862	4
values[17]	390	1			T542	1		T845	1		T862	10
values[18]	399	1			T542	1		T845	1		T862	4
values[19]	339	1			T542	1		T845	1		T862	8
values[20]	393	1			T542	1		T845	1		T862	13
values[21]	385	1			T542	1		T845	1		T862	20
values[22]	413	1			T542	1		T845	1		T862	8
values[23]	374	1			T542	1		T845	1		T862	3
values[24]	387	1			T542	1		T845	1		T862	4
values[25]	424	1			T542	1		T845	1		T862	5
values[26]	435	1			T542	1		T845	1		T862	3
values[27]	352	1			T542	1		T845	1		T862	15
values[28]	328	1			T542	1		T845	1		T862	5
values[29]	428	1			T542	1		T845	1		T862	14
values[30]	358	1			T542	1		T845	1		T862	5
values[31]	382	1			T542	1		T845	1		T862	5
values[32]	428	1			T542	1		T845	1		T862	6
values[33]	424	1			T542	1		T845	1		T862	5
values[34]	445	1			T542	1		T845	1		T862	7
values[35]	440	1			T542	1		T845	1		T862	2
values[36]	384	1			T542	1		T845	1		T862	4
values[37]	316	1			T542	1		T845	1		T862	3
values[38]	281	1			T542	1		T845	1		T862	4
values[39]	356	1			T542	1		T845	1		T862	4
values[40]	370	1			T542	1		T845	1		T862	4
values[41]	399	1			T542	1		T845	1		T862	4
values[42]	330	1			T542	1		T845	1		T862	8
values[43]	354	1			T542	1		T845	1		T862	3
values[44]	349	1			T542	1		T845	1		T862	22
values[45]	320	1			T542	1		T845	1		T862	19
values[46]	310	1			T542	1		T845	1		T862	4
values[47]	312	1			T542	1		T845	1		T862	15
values[48]	343	1			T542	1		T845	1		T862	10
values[49]	292	1			T542	1		T845	1		T862	8
values[50]	299	1			T542	1		T845	1		T862	6
values[51]	262	1			T542	1		T845	1		T862	4
values[52]	286	1			T542	1		T845	1		T862	19
values[53]	343	1			T542	1		T845	1		T862	4
values[54]	323	1			T542	1		T845	1		T862	9
values[55]	298	1			T542	1		T845	1		T862	7
values[56]	295	1			T542	1		T845	1		T862	4
values[57]	293	1			T542	1		T845	1		T862	19
values[58]	276	1			T542	1		T845	1		T862	6
values[59]	335	1			T542	1		T845	1		T862	3
values[60]	275	1			T542	1		T845	1		T862	6
values[61]	229	1			T542	1		T845	1		T862	13
values[62]	218	1			T542	1		T845	1		T862	8
values[63]	189	1			T542	1		T845	1		T491	7
values[64]	156	1			T542	1		T845	1		T491	10
values[65]	161	1			T542	1		T845	1		T491	4
values[66]	167	1			T542	1		T845	1		T491	8
values[67]	149	1			T542	1		T845	1		T491	2
values[68]	162	1			T542	1		T845	1		T491	3
values[69]	127	1			T542	1		T845	1		T841	1
values[70]	88	1			T542	1		T845	1		T841	1
values[71]	75	1			T542	1		T845	2		T841	1
values[72]	88	1			T542	1		T845	1		T841	1
values[73]	90	1			T542	1		T845	1		T841	1
values[74]	93	1			T542	1		T845	1		T841	1
values[75]	105	1			T542	1		T845	1		T841	1
values[76]	71	1			T542	1		T845	1		T841	1
values[77]	51	1			T542	1		T845	1		T841	1
values[78]	57	1			T542	1		T845	1		T841	1
values[79]	52	1			T542	1		T845	1		T841	1
values[80]	53	1			T542	1		T845	1		T841	1
values[81]	51	1			T542	1		T845	1		T841	1
values[82]	57	1			T542	1		T845	1		T841	1
values[83]	49	1			T542	1		T845	1		T841	1
values[84]	49	1			T542	1		T845	1		T841	1
values[85]	62	1			T542	1		T845	1		T841	1
values[86]	54	1			T542	1		T845	1		T841	1
values[87]	61	1			T542	1		T845	1		T841	1
values[88]	63	1			T542	1		T845	1		T841	1
values[89]	69	1			T542	1		T845	1		T841	1
values[90]	57	1			T542	1		T845	1		T841	1
values[91]	69	1			T542	1		T845	1		T841	1
values[92]	64	1			T542	1		T845	1		T841	1
values[93]	75	1			T542	1		T845	1		T841	1
values[94]	92	1			T542	1		T845	1		T841	1
values[95]	87	1			T542	1		T845	1		T841	1
values[96]	84	1			T542	1		T845	2		T841	1
values[97]	92	1			T542	1		T845	3		T841	1
values[98]	91	1			T542	2		T845	4		T841	1
values[99]	85	1			T542	1		T845	1		T841	2
values[100]	76	1			T542	2		T845	2		T841	1
values[101]	69	1			T542	1		T845	1		T841	1
values[102]	71	1			T542	1		T845	1		T841	1
values[103]	84	1			T542	1		T845	1		T841	1
values[104]	83	1			T542	1		T845	2		T841	1
values[105]	77	1			T542	1		T845	3		T841	1
values[106]	67	1			T542	1		T845	3		T841	1
values[107]	73	1			T542	1		T845	1		T841	1
values[108]	83	1			T542	1		T845	1		T841	1
values[109]	86	1			T542	2		T845	1		T841	1
values[110]	104	1			T542	4		T845	2		T841	1
values[111]	83	1			T542	1		T845	3		T841	1
values[112]	56	1			T542	6		T845	1		T841	1
values[113]	76	1			T542	1		T845	5		T841	1
values[114]	56	1			T542	1		T845	1		T841	1
values[115]	60	1			T542	1		T845	2		T841	1
values[116]	62	1			T542	1		T845	2		T841	1
values[117]	55	1			T542	1		T845	1		T841	1
values[118]	58	1			T542	2		T845	2		T841	1
values[119]	58	1			T542	1		T845	2		T841	1
values[120]	62	1			T542	2		T845	1		T841	1
values[121]	63	1			T542	1		T845	4		T841	1
values[122]	60	1			T542	3		T845	1		T841	1
values[123]	57	1			T542	2		T845	2		T841	1
values[124]	63	1			T542	7		T845	3		T841	2
values[125]	86	1			T542	3		T845	4		T841	1
values[126]	139	1			T542	1		T845	4		T841	4
values[127]	721	1			T542	30		T845	37		T841	44
values[128]	5880	1			T542	331		T845	338		T841	363