Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	146513	1			T75	879		T76	1		T77	3
values[2]	7557	1			T75	19		T81	4		T130	166
values[3]	3598	1			T75	20		T130	108		T537	7
values[4]	2171	1			T75	10		T130	65		T537	3
values[5]	1520	1			T75	22		T130	35		T537	7
values[6]	1140	1			T75	12		T130	7		T537	8
values[7]	790	1			T75	5		T537	3		T696	1
values[8]	770	1			T75	25		T537	2		T696	1
values[9]	670	1			T75	6		T537	3		T696	1
values[10]	647	1			T75	14		T537	2		T696	1
values[11]	625	1			T75	6		T537	10		T696	1
values[12]	519	1			T75	12		T537	5		T696	1
values[13]	555	1			T75	10		T537	8		T696	1
values[14]	561	1			T75	10		T537	6		T696	1
values[15]	537	1			T75	5		T537	4		T696	2
values[16]	505	1			T75	8		T537	2		T696	1
values[17]	443	1			T75	11		T537	2		T696	1
values[18]	506	1			T75	10		T537	6		T696	1
values[19]	466	1			T75	6		T537	8		T696	1
values[20]	383	1			T75	5		T537	7		T696	1
values[21]	333	1			T75	6		T537	3		T696	1
values[22]	379	1			T75	6		T537	4		T696	1
values[23]	411	1			T75	28		T537	3		T696	1
values[24]	318	1			T75	4		T537	10		T696	1
values[25]	380	1			T75	4		T537	7		T696	1
values[26]	400	1			T75	4		T537	2		T696	1
values[27]	346	1			T75	24		T537	7		T696	1
values[28]	279	1			T75	25		T537	2		T696	1
values[29]	277	1			T75	6		T537	1		T696	1
values[30]	298	1			T75	7		T537	2		T696	1
values[31]	298	1			T75	3		T537	2		T696	1
values[32]	290	1			T75	4		T537	5		T696	1
values[33]	274	1			T75	7		T537	7		T696	1
values[34]	287	1			T537	2		T696	1		T846	1
values[35]	269	1			T537	2		T696	1		T846	1
values[36]	305	1			T537	3		T696	1		T846	1
values[37]	322	1			T537	6		T696	1		T846	1
values[38]	256	1			T537	5		T696	1		T846	1
values[39]	260	1			T537	1		T696	1		T846	1
values[40]	245	1			T537	3		T696	1		T846	1
values[41]	252	1			T537	3		T696	1		T846	1
values[42]	237	1			T537	3		T696	1		T846	1
values[43]	177	1			T537	2		T696	1		T846	1
values[44]	226	1			T537	3		T696	1		T846	1
values[45]	192	1			T537	6		T696	1		T846	1
values[46]	205	1			T537	5		T696	1		T846	1
values[47]	190	1			T537	1		T696	1		T846	1
values[48]	204	1			T537	2		T696	1		T846	1
values[49]	195	1			T537	2		T696	1		T846	1
values[50]	174	1			T537	9		T696	1		T846	1
values[51]	133	1			T537	11		T696	1		T846	1
values[52]	146	1			T537	4		T696	1		T846	1
values[53]	85	1			T537	3		T696	1		T846	1
values[54]	64	1			T537	9		T696	1		T846	1
values[55]	66	1			T537	15		T696	1		T846	1
values[56]	40	1			T537	3		T696	1		T846	1
values[57]	32	1			T537	1		T696	1		T846	1
values[58]	36	1			T537	4		T696	1		T846	1
values[59]	30	1			T537	5		T696	1		T846	1
values[60]	36	1			T537	6		T696	1		T846	1
values[61]	43	1			T537	3		T696	1		T846	1
values[62]	53	1			T537	6		T696	1		T846	1
values[63]	55	1			T537	5		T696	1		T846	1
values[64]	41	1			T537	5		T696	1		T846	1
values[65]	52	1			T537	11		T696	1		T846	1
values[66]	64	1			T537	12		T696	1		T846	1
values[67]	53	1			T537	11		T696	1		T846	1
values[68]	47	1			T537	8		T696	1		T846	1
values[69]	55	1			T537	12		T696	1		T846	2
values[70]	65	1			T537	11		T696	2		T846	1
values[71]	40	1			T537	5		T696	1		T846	1
values[72]	52	1			T537	5		T696	1		T846	1
values[73]	44	1			T537	2		T696	1		T846	1
values[74]	35	1			T537	4		T696	1		T846	1
values[75]	29	1			T537	1		T696	1		T846	1
values[76]	38	1			T537	6		T696	1		T846	1
values[77]	44	1			T537	9		T696	1		T846	1
values[78]	49	1			T537	20		T696	1		T846	1
values[79]	70	1			T537	32		T696	1		T846	1
values[80]	46	1			T537	19		T696	1		T846	1
values[81]	35	1			T537	9		T696	1		T846	1
values[82]	45	1			T537	11		T696	1		T846	1
values[83]	43	1			T537	4		T696	1		T846	1
values[84]	52	1			T537	15		T696	1		T846	1
values[85]	38	1			T537	6		T696	1		T846	1
values[86]	35	1			T537	4		T696	1		T846	1
values[87]	35	1			T696	1		T846	1		T874	1
values[88]	40	1			T696	1		T846	1		T874	3
values[89]	43	1			T696	1		T846	1		T874	6
values[90]	30	1			T696	1		T846	1		T874	1
values[91]	25	1			T696	1		T846	1		T874	1
values[92]	34	1			T696	1		T846	1		T874	3
values[93]	48	1			T696	1		T846	1		T874	4
values[94]	61	1			T696	1		T846	1		T874	4
values[95]	47	1			T696	1		T846	1		T874	4
values[96]	40	1			T696	1		T846	1		T874	1
values[97]	38	1			T696	1		T846	1		T874	1
values[98]	42	1			T696	1		T846	1		T874	1
values[99]	46	1			T696	1		T846	1		T874	2
values[100]	45	1			T696	1		T846	1		T874	2
values[101]	44	1			T696	1		T846	1		T874	2
values[102]	40	1			T696	1		T846	1		T874	1
values[103]	38	1			T696	1		T846	1		T874	2
values[104]	35	1			T696	1		T846	1		T874	1
values[105]	39	1			T696	1		T846	1		T874	1
values[106]	39	1			T696	1		T846	1		T874	3
values[107]	35	1			T696	1		T846	1		T874	4
values[108]	34	1			T696	2		T846	1		T874	1
values[109]	34	1			T696	2		T846	1		T874	2
values[110]	46	1			T696	2		T846	1		T874	1
values[111]	41	1			T696	1		T846	1		T874	1
values[112]	27	1			T696	1		T846	1		T874	3
values[113]	27	1			T696	1		T846	1		T874	3
values[114]	24	1			T696	2		T846	1		T874	2
values[115]	32	1			T696	1		T846	6		T874	2
values[116]	23	1			T696	1		T846	4		T874	1
values[117]	27	1			T696	1		T846	2		T874	1
values[118]	25	1			T696	1		T846	3		T874	1
values[119]	27	1			T696	1		T846	2		T874	2
values[120]	29	1			T696	2		T846	2		T874	1
values[121]	40	1			T696	2		T846	3		T874	1
values[122]	26	1			T696	4		T846	1		T874	2
values[123]	24	1			T696	1		T846	1		T874	1
values[124]	41	1			T696	4		T846	3		T874	2
values[125]	27	1			T696	1		T846	1		T874	2
values[126]	59	1			T696	2		T846	2		T874	2
values[127]	892	1			T696	68		T846	53		T874	57
values[128]	4191	1			T696	323		T846	249		T874	246