Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.edn0_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	177263	1			T75	1146		T76	5		T77	5
values[2]	4332	1			T81	1		T130	265		T255	3
values[3]	1951	1			T130	145		T542	1		T566	1
values[4]	1442	1			T130	107		T542	1		T685	16
values[5]	1016	1			T130	78		T542	1		T685	6
values[6]	773	1			T130	51		T542	1		T685	14
values[7]	720	1			T130	31		T542	1		T685	22
values[8]	625	1			T130	24		T542	1		T685	25
values[9]	537	1			T130	19		T542	1		T685	24
values[10]	544	1			T130	21		T542	1		T685	28
values[11]	565	1			T130	7		T542	1		T685	24
values[12]	499	1			T130	15		T542	1		T685	25
values[13]	503	1			T130	15		T542	1		T685	27
values[14]	455	1			T130	9		T542	1		T685	33
values[15]	387	1			T130	4		T542	1		T685	17
values[16]	320	1			T130	7		T542	1		T685	19
values[17]	280	1			T130	6		T542	1		T685	12
values[18]	292	1			T130	20		T542	1		T685	13
values[19]	260	1			T130	19		T542	1		T685	13
values[20]	222	1			T130	14		T542	1		T685	20
values[21]	189	1			T130	7		T542	1		T685	25
values[22]	193	1			T130	2		T542	1		T685	34
values[23]	180	1			T542	1		T685	39		T526	4
values[24]	188	1			T542	1		T685	33		T526	3
values[25]	180	1			T542	1		T685	23		T526	3
values[26]	151	1			T542	1		T685	23		T526	2
values[27]	157	1			T542	1		T685	6		T526	2
values[28]	163	1			T542	1		T685	1		T526	3
values[29]	154	1			T542	1		T685	2		T526	2
values[30]	134	1			T542	1		T685	2		T526	1
values[31]	154	1			T542	1		T526	4		T850	1
values[32]	119	1			T542	1		T526	2		T850	1
values[33]	90	1			T542	1		T526	1		T850	1
values[34]	72	1			T542	1		T526	1		T850	1
values[35]	65	1			T542	1		T526	5		T850	1
values[36]	62	1			T542	1		T526	5		T850	1
values[37]	65	1			T542	1		T526	2		T850	1
values[38]	57	1			T542	1		T526	1		T850	1
values[39]	66	1			T542	1		T526	5		T850	1
values[40]	59	1			T542	1		T526	1		T850	1
values[41]	79	1			T542	1		T526	1		T850	1
values[42]	76	1			T542	1		T526	2		T850	1
values[43]	61	1			T542	1		T526	2		T850	1
values[44]	67	1			T542	1		T526	2		T850	1
values[45]	69	1			T542	1		T526	1		T850	1
values[46]	87	1			T542	1		T526	1		T850	1
values[47]	83	1			T542	1		T526	3		T850	1
values[48]	69	1			T542	1		T526	3		T850	1
values[49]	67	1			T542	1		T526	2		T850	1
values[50]	73	1			T542	1		T526	5		T850	1
values[51]	79	1			T542	1		T526	5		T850	1
values[52]	59	1			T542	1		T526	7		T850	1
values[53]	58	1			T542	1		T526	2		T850	1
values[54]	59	1			T542	1		T526	7		T850	1
values[55]	60	1			T542	1		T526	7		T850	1
values[56]	68	1			T542	1		T526	4		T850	1
values[57]	57	1			T542	1		T526	1		T850	1
values[58]	62	1			T542	1		T526	3		T850	1
values[59]	54	1			T542	1		T526	5		T850	1
values[60]	49	1			T542	1		T526	1		T850	1
values[61]	54	1			T542	1		T526	3		T850	1
values[62]	53	1			T542	1		T526	4		T850	1
values[63]	55	1			T542	1		T526	5		T850	1
values[64]	50	1			T542	1		T526	2		T850	1
values[65]	58	1			T542	1		T526	4		T850	1
values[66]	55	1			T542	1		T526	1		T850	1
values[67]	58	1			T542	1		T526	3		T850	1
values[68]	59	1			T542	1		T526	6		T850	1
values[69]	52	1			T542	1		T526	2		T850	1
values[70]	57	1			T542	1		T526	4		T850	1
values[71]	61	1			T542	1		T526	9		T850	1
values[72]	88	1			T542	1		T526	22		T850	1
values[73]	72	1			T542	1		T526	7		T850	1
values[74]	68	1			T542	1		T526	4		T850	1
values[75]	72	1			T542	1		T526	12		T850	1
values[76]	72	1			T542	1		T526	4		T850	1
values[77]	67	1			T542	1		T526	4		T850	1
values[78]	82	1			T542	1		T526	4		T850	1
values[79]	75	1			T542	1		T526	5		T850	1
values[80]	75	1			T542	1		T526	3		T850	1
values[81]	73	1			T542	1		T526	5		T850	1
values[82]	72	1			T542	1		T526	2		T850	1
values[83]	90	1			T542	1		T526	6		T850	1
values[84]	93	1			T542	1		T526	5		T850	1
values[85]	75	1			T542	1		T526	3		T850	1
values[86]	81	1			T542	1		T526	3		T850	1
values[87]	80	1			T542	1		T526	4		T850	1
values[88]	69	1			T542	1		T526	5		T850	1
values[89]	84	1			T542	1		T526	10		T850	1
values[90]	66	1			T542	1		T526	3		T850	1
values[91]	84	1			T542	1		T526	6		T850	1
values[92]	98	1			T542	1		T526	3		T850	1
values[93]	88	1			T542	1		T526	4		T850	1
values[94]	86	1			T542	1		T526	1		T850	2
values[95]	93	1			T542	1		T526	4		T850	1
values[96]	95	1			T542	1		T526	6		T850	2
values[97]	91	1			T542	1		T526	6		T850	4
values[98]	99	1			T542	1		T526	6		T850	3
values[99]	97	1			T542	1		T526	3		T850	1
values[100]	91	1			T542	1		T526	2		T850	1
values[101]	84	1			T542	1		T526	3		T850	1
values[102]	87	1			T542	1		T526	2		T850	3
values[103]	94	1			T542	1		T526	4		T850	2
values[104]	98	1			T542	1		T526	4		T850	6
values[105]	114	1			T542	1		T526	5		T850	2
values[106]	91	1			T542	1		T526	4		T850	2
values[107]	107	1			T542	1		T526	11		T850	1
values[108]	92	1			T542	1		T526	3		T850	2
values[109]	92	1			T542	1		T526	6		T850	1
values[110]	121	1			T542	1		T526	9		T850	3
values[111]	113	1			T542	1		T526	6		T850	1
values[112]	94	1			T542	1		T526	1		T850	2
values[113]	103	1			T542	1		T526	1		T850	2
values[114]	95	1			T542	1		T526	4		T850	3
values[115]	91	1			T542	1		T526	1		T850	5
values[116]	101	1			T542	1		T526	2		T850	1
values[117]	120	1			T542	1		T526	8		T850	2
values[118]	100	1			T542	1		T526	7		T850	2
values[119]	94	1			T542	1		T526	2		T850	1
values[120]	109	1			T542	1		T526	2		T850	4
values[121]	101	1			T542	1		T526	4		T850	3
values[122]	104	1			T542	1		T526	2		T850	2
values[123]	110	1			T542	1		T526	4		T850	3
values[124]	137	1			T542	1		T526	6		T850	1
values[125]	239	1			T542	1		T526	2		T850	2
values[126]	695	1			T542	13		T526	4		T850	11
values[127]	3983	1			T542	114		T526	1		T850	92
values[128]	7748	1			T542	226		T850	228		T843	239