Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	172624	1			T75	1034		T76	5		T77	4
values[2]	5253	1			T81	1		T130	112		T463	1
values[3]	2910	1			T130	74		T542	1		T541	12
values[4]	2100	1			T130	43		T542	1		T541	20
values[5]	1739	1			T130	31		T542	1		T541	7
values[6]	1509	1			T130	12		T542	1		T541	5
values[7]	1327	1			T130	1		T542	1		T845	2
values[8]	1065	1			T542	1		T845	2		T842	1
values[9]	1019	1			T542	1		T845	2		T842	1
values[10]	802	1			T542	1		T845	2		T842	1
values[11]	704	1			T542	1		T845	2		T842	1
values[12]	632	1			T542	1		T845	2		T842	1
values[13]	559	1			T542	1		T845	2		T842	1
values[14]	444	1			T542	1		T845	2		T842	1
values[15]	358	1			T542	1		T845	2		T842	1
values[16]	321	1			T542	1		T845	2		T842	1
values[17]	306	1			T542	1		T845	2		T842	1
values[18]	292	1			T542	2		T845	2		T842	1
values[19]	316	1			T542	1		T845	2		T842	1
values[20]	320	1			T542	1		T845	2		T842	1
values[21]	278	1			T542	1		T845	2		T842	1
values[22]	213	1			T542	1		T845	2		T842	1
values[23]	166	1			T542	1		T845	2		T842	1
values[24]	152	1			T542	1		T845	2		T842	1
values[25]	147	1			T542	1		T845	2		T842	1
values[26]	160	1			T542	1		T845	2		T842	1
values[27]	154	1			T542	1		T845	2		T842	1
values[28]	121	1			T542	1		T845	2		T842	1
values[29]	99	1			T542	1		T845	2		T842	1
values[30]	131	1			T542	1		T845	2		T842	1
values[31]	140	1			T542	1		T845	2		T842	1
values[32]	111	1			T542	1		T845	2		T842	1
values[33]	112	1			T542	1		T845	2		T842	1
values[34]	107	1			T542	1		T845	2		T842	1
values[35]	136	1			T542	1		T845	2		T842	1
values[36]	124	1			T542	1		T845	2		T842	1
values[37]	123	1			T542	1		T845	2		T842	1
values[38]	130	1			T542	1		T845	2		T842	1
values[39]	127	1			T542	1		T845	2		T842	1
values[40]	100	1			T542	1		T845	2		T842	1
values[41]	85	1			T542	1		T845	2		T842	1
values[42]	74	1			T542	1		T845	2		T842	1
values[43]	72	1			T542	1		T845	2		T842	1
values[44]	64	1			T542	1		T845	2		T842	1
values[45]	67	1			T542	1		T845	2		T842	1
values[46]	63	1			T542	1		T845	2		T842	1
values[47]	75	1			T542	1		T845	2		T842	1
values[48]	61	1			T542	1		T845	2		T842	1
values[49]	56	1			T542	1		T845	2		T842	1
values[50]	61	1			T542	1		T845	2		T842	1
values[51]	69	1			T542	1		T845	2		T842	1
values[52]	73	1			T542	1		T845	2		T842	1
values[53]	68	1			T542	1		T845	2		T842	1
values[54]	62	1			T542	1		T845	2		T842	1
values[55]	60	1			T542	1		T845	2		T842	1
values[56]	66	1			T542	1		T845	2		T842	1
values[57]	60	1			T542	1		T845	2		T842	1
values[58]	57	1			T542	1		T845	2		T842	1
values[59]	62	1			T542	1		T845	2		T842	1
values[60]	48	1			T542	1		T845	2		T842	1
values[61]	55	1			T542	1		T845	2		T842	1
values[62]	55	1			T542	1		T845	2		T842	1
values[63]	48	1			T542	1		T845	2		T842	1
values[64]	57	1			T542	1		T845	2		T842	1
values[65]	62	1			T542	1		T845	2		T842	1
values[66]	56	1			T542	1		T845	2		T842	1
values[67]	62	1			T542	1		T845	3		T842	1
values[68]	73	1			T542	1		T845	2		T842	1
values[69]	71	1			T542	1		T845	2		T842	1
values[70]	63	1			T542	1		T845	2		T842	1
values[71]	64	1			T542	1		T845	2		T842	1
values[72]	64	1			T542	1		T845	2		T842	1
values[73]	63	1			T542	1		T845	2		T842	1
values[74]	57	1			T542	1		T845	2		T842	1
values[75]	62	1			T542	1		T845	2		T842	1
values[76]	49	1			T542	1		T845	2		T842	1
values[77]	56	1			T542	1		T845	2		T842	1
values[78]	64	1			T542	3		T845	2		T842	1
values[79]	68	1			T542	8		T845	2		T842	1
values[80]	59	1			T542	9		T845	2		T842	1
values[81]	63	1			T542	4		T845	2		T842	1
values[82]	74	1			T542	3		T845	2		T842	1
values[83]	70	1			T542	5		T845	2		T842	1
values[84]	77	1			T542	4		T845	2		T842	1
values[85]	78	1			T542	3		T845	7		T842	1
values[86]	78	1			T542	2		T845	6		T842	1
values[87]	76	1			T542	3		T845	10		T842	1
values[88]	101	1			T542	4		T845	5		T842	1
values[89]	79	1			T542	2		T845	3		T842	1
values[90]	81	1			T542	3		T845	3		T842	1
values[91]	89	1			T542	4		T845	5		T842	1
values[92]	102	1			T542	3		T845	5		T842	2
values[93]	93	1			T542	3		T845	4		T842	2
values[94]	86	1			T542	1		T845	4		T842	1
values[95]	97	1			T542	3		T845	4		T842	6
values[96]	93	1			T542	6		T845	6		T842	2
values[97]	80	1			T542	1		T845	6		T842	6
values[98]	83	1			T542	3		T845	7		T842	3
values[99]	103	1			T542	2		T845	2		T842	5
values[100]	92	1			T542	2		T845	2		T842	4
values[101]	67	1			T542	1		T845	3		T842	1
values[102]	83	1			T542	1		T845	2		T842	1
values[103]	98	1			T542	1		T845	3		T842	1
values[104]	100	1			T542	3		T845	2		T842	1
values[105]	86	1			T542	1		T845	3		T842	2
values[106]	102	1			T542	3		T845	5		T842	2
values[107]	111	1			T542	2		T845	3		T842	5
values[108]	115	1			T542	3		T845	3		T842	3
values[109]	77	1			T542	1		T845	2		T842	4
values[110]	96	1			T542	2		T845	3		T842	3
values[111]	106	1			T542	2		T845	4		T842	2
values[112]	101	1			T542	1		T845	6		T842	2
values[113]	110	1			T542	1		T845	2		T842	2
values[114]	99	1			T542	1		T845	2		T842	6
values[115]	116	1			T542	1		T845	2		T842	5
values[116]	107	1			T542	2		T845	2		T842	1
values[117]	124	1			T542	2		T845	4		T842	4
values[118]	145	1			T542	1		T845	5		T842	4
values[119]	131	1			T542	1		T845	5		T842	1
values[120]	114	1			T542	1		T845	3		T842	2
values[121]	104	1			T542	3		T845	3		T842	3
values[122]	137	1			T542	1		T845	2		T842	3
values[123]	174	1			T542	1		T845	2		T842	3
values[124]	282	1			T542	2		T845	2		T842	2
values[125]	533	1			T542	2		T845	4		T842	5
values[126]	944	1			T542	7		T845	41		T842	12
values[127]	2427	1			T542	91		T845	200		T842	89
values[128]	3929	1			T542	180		T845	348		T842	166