Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	518	1			T75	2		T254	1		T430	1
all_values[1]	505	1			T75	6		T430	1		T542	2
all_values[2]	496	1			T75	6		T430	1		T541	3
all_values[3]	527	1			T75	2		T130	2		T254	1
all_values[4]	510	1			T75	4		T254	1		T541	3
all_values[5]	474	1			T75	3		T254	3		T765	1
all_values[6]	467	1			T75	2		T130	1		T430	4
all_values[7]	464	1			T75	4		T254	1		T430	5
all_values[8]	503	1			T75	4		T254	1		T765	1
all_values[9]	480	1			T430	2		T542	1		T541	3
all_values[10]	456	1			T75	2		T430	2		T541	6
all_values[11]	443	1			T75	5		T430	3		T540	1
all_values[12]	465	1			T75	2		T430	1		T542	1
all_values[13]	484	1			T75	1		T130	1		T765	1
all_values[14]	460	1			T75	4		T430	3		T503	1
all_values[15]	506	1			T75	3		T130	4		T254	2
all_values[16]	489	1			T75	3		T130	1		T430	4
all_values[17]	470	1			T75	3		T430	3		T503	1
all_values[18]	499	1			T130	1		T254	1		T765	2
all_values[19]	477	1			T75	2		T430	1		T541	6
all_values[20]	500	1			T75	2		T130	1		T254	1
all_values[21]	489	1			T75	1		T130	2		T254	1
all_values[22]	522	1			T75	2		T130	2		T254	2
all_values[23]	523	1			T75	4		T254	2		T430	2
all_values[24]	517	1			T75	6		T130	1		T430	5
all_values[25]	517	1			T75	3		T254	1		T430	1
all_values[26]	516	1			T75	2		T254	1		T430	3
all_values[27]	489	1			T75	3		T130	1		T430	1
all_values[28]	440	1			T75	3		T430	2		T537	1
all_values[29]	503	1			T75	2		T254	1		T430	2
all_values[30]	458	1			T75	1		T430	3		T542	1
all_values[31]	474	1			T75	3		T430	5		T541	5
all_values[32]	506	1			T254	1		T430	1		T540	1
all_values[33]	497	1			T75	3		T254	1		T430	2
all_values[34]	503	1			T75	2		T254	1		T430	2
all_values[35]	452	1			T75	2		T130	4		T430	1
all_values[36]	476	1			T75	3		T313	1		T430	5
all_values[37]	474	1			T254	2		T765	1		T430	5
all_values[38]	508	1			T75	2		T130	1		T254	1
all_values[39]	471	1			T75	3		T130	1		T430	2
all_values[40]	479	1			T75	1		T130	1		T254	1
all_values[41]	520	1			T130	2		T430	5		T541	5
all_values[42]	469	1			T75	2		T313	1		T254	1
all_values[43]	491	1			T75	2		T130	2		T254	1
all_values[44]	447	1			T75	2		T130	1		T254	1
all_values[45]	470	1			T75	3		T430	2		T537	1
all_values[46]	476	1			T75	2		T430	3		T537	1
all_values[47]	485	1			T75	3		T254	1		T430	1
all_values[48]	496	1			T75	1		T130	2		T254	1
all_values[49]	468	1			T254	1		T845	1		T881	1