Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3707	1			T75	11		T130	8		T254	1
all_values[1]	3575	1			T75	12		T130	7		T254	1
all_values[2]	3629	1			T75	12		T130	5		T254	2
all_values[3]	3579	1			T75	19		T130	3		T254	1
all_values[4]	3707	1			T75	11		T130	6		T254	1
all_values[5]	3662	1			T75	14		T130	5		T254	3
all_values[6]	3698	1			T75	8		T130	6		T254	4
all_values[7]	3832	1			T75	15		T130	5		T254	5
all_values[8]	3774	1			T75	16		T130	7		T254	6
all_values[9]	3750	1			T75	11		T130	6		T254	4
all_values[10]	3814	1			T75	11		T130	5		T254	4
all_values[11]	3724	1			T75	11		T130	7		T254	2
all_values[12]	3783	1			T75	13		T130	5		T254	1
all_values[13]	3615	1			T75	10		T130	4		T254	4
all_values[14]	3680	1			T75	10		T130	6		T254	1
all_values[15]	3652	1			T75	15		T130	5		T254	2
all_values[16]	3722	1			T75	23		T130	4		T254	1
all_values[17]	3737	1			T75	21		T130	4		T254	2
all_values[18]	3797	1			T75	15		T130	3		T254	5
all_values[19]	3730	1			T75	18		T130	5		T254	3
all_values[20]	3786	1			T75	12		T130	2		T430	19
all_values[21]	3689	1			T75	16		T130	9		T254	2
all_values[22]	3708	1			T75	18		T130	7		T430	10
all_values[23]	3689	1			T75	18		T130	7		T254	2
all_values[24]	3778	1			T75	10		T130	6		T254	6
all_values[25]	3748	1			T75	11		T130	8		T254	3
all_values[26]	3599	1			T75	14		T130	6		T254	1
all_values[27]	3680	1			T75	7		T130	8		T254	2
all_values[28]	3726	1			T75	9		T130	3		T430	13
all_values[29]	3706	1			T75	15		T130	4		T254	3
all_values[30]	3721	1			T75	12		T130	1		T254	1
all_values[31]	3751	1			T75	10		T130	8		T254	2
all_values[32]	3696	1			T75	11		T130	7		T254	2
all_values[33]	3632	1			T75	18		T130	7		T430	13
all_values[34]	3717	1			T75	18		T130	4		T254	3
all_values[35]	3684	1			T75	10		T130	4		T254	1
all_values[36]	3820	1			T75	18		T130	10		T254	4
all_values[37]	3750	1			T75	11		T130	4		T254	3
all_values[38]	3722	1			T75	11		T130	9		T254	4
all_values[39]	3758	1			T75	13		T130	6		T430	16
all_values[40]	3682	1			T75	16		T130	5		T254	1
all_values[41]	3589	1			T75	11		T130	5		T430	12
all_values[42]	3733	1			T75	12		T130	10		T254	3
all_values[43]	3633	1			T75	12		T130	6		T254	1
all_values[44]	3789	1			T75	20		T130	7		T254	3
all_values[45]	3714	1			T75	16		T130	5		T254	1
all_values[46]	3746	1			T75	20		T130	3		T430	13
all_values[47]	3661	1			T75	20		T130	3		T430	10
all_values[48]	3736	1			T75	18		T130	8		T254	3
all_values[49]	3776	1			T75	19		T130	6		T254	2
all_values[50]	3712	1			T75	14		T130	3		T254	3
all_values[51]	3743	1			T75	16		T130	7		T254	4
all_values[52]	3779	1			T75	18		T130	6		T430	15
all_values[53]	3640	1			T75	11		T130	6		T430	13
all_values[54]	3668	1			T75	18		T130	7		T254	2
all_values[55]	3603	1			T75	16		T130	3		T254	1
all_values[56]	3801	1			T75	16		T130	5		T254	2
all_values[57]	3657	1			T75	22		T130	4		T254	2
all_values[58]	3688	1			T75	21		T130	2		T254	1
all_values[59]	3698	1			T75	14		T130	5		T254	1
all_values[60]	3745	1			T75	18		T130	8		T254	1
all_values[61]	3821	1			T75	21		T130	4		T254	2
all_values[62]	3727	1			T75	16		T130	5		T254	3
all_values[63]	3679	1			T75	20		T130	6		T254	2