Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c0_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	144611	1			T72	55		T73	5		T74	7
values[2]	12084	1			T72	5		T257	1		T258	3
values[3]	4914	1			T549	1		T552	92		T472	35
values[4]	3060	1			T549	1		T552	52		T472	13
values[5]	2079	1			T552	45		T608	9		T467	34
values[6]	1304	1			T552	24		T608	11		T467	3
values[7]	940	1			T552	24		T608	41		T524	4
values[8]	652	1			T552	26		T608	9		T524	2
values[9]	493	1			T552	25		T608	11		T524	3
values[10]	422	1			T552	15		T608	12		T524	2
values[11]	396	1			T552	2		T608	27		T524	1
values[12]	347	1			T608	17		T524	2		T477	27
values[13]	409	1			T608	15		T524	3		T477	35
values[14]	411	1			T608	11		T524	3		T477	33
values[15]	372	1			T608	9		T524	2		T477	15
values[16]	246	1			T608	8		T524	1		T477	3
values[17]	327	1			T608	27		T524	4		T842	1
values[18]	299	1			T608	20		T524	3		T842	1
values[19]	294	1			T608	12		T524	2		T842	1
values[20]	319	1			T608	19		T524	2		T842	1
values[21]	310	1			T608	6		T524	1		T842	1
values[22]	295	1			T608	13		T524	2		T842	1
values[23]	333	1			T608	37		T524	3		T842	1
values[24]	297	1			T608	21		T524	4		T842	1
values[25]	280	1			T608	17		T524	7		T842	1
values[26]	295	1			T608	17		T524	10		T842	1
values[27]	323	1			T608	7		T524	2		T842	1
values[28]	318	1			T608	20		T524	3		T842	1
values[29]	318	1			T608	10		T524	3		T842	1
values[30]	330	1			T608	17		T524	7		T842	1
values[31]	292	1			T608	29		T524	2		T842	1
values[32]	334	1			T608	11		T524	2		T842	1
values[33]	297	1			T608	13		T524	1		T842	1
values[34]	270	1			T608	9		T524	2		T842	1
values[35]	313	1			T608	17		T524	2		T842	1
values[36]	311	1			T608	11		T524	2		T842	1
values[37]	261	1			T608	10		T524	1		T842	1
values[38]	272	1			T608	9		T524	5		T842	1
values[39]	293	1			T608	9		T524	1		T842	1
values[40]	298	1			T608	9		T524	2		T842	1
values[41]	301	1			T608	17		T524	2		T842	1
values[42]	299	1			T608	23		T524	4		T842	1
values[43]	298	1			T608	8		T524	7		T842	1
values[44]	294	1			T608	24		T524	13		T842	1
values[45]	243	1			T608	13		T524	6		T842	1
values[46]	273	1			T608	10		T524	4		T842	1
values[47]	213	1			T608	13		T524	6		T842	1
values[48]	209	1			T608	19		T524	3		T842	1
values[49]	244	1			T608	18		T524	1		T842	1
values[50]	207	1			T608	11		T524	3		T842	1
values[51]	278	1			T608	7		T524	7		T842	1
values[52]	278	1			T608	7		T524	2		T842	1
values[53]	263	1			T608	7		T524	1		T842	1
values[54]	250	1			T608	8		T524	1		T842	1
values[55]	236	1			T608	25		T524	3		T842	1
values[56]	230	1			T608	19		T524	3		T842	1
values[57]	223	1			T608	13		T524	1		T842	1
values[58]	204	1			T608	14		T524	2		T842	1
values[59]	199	1			T608	9		T524	2		T842	1
values[60]	182	1			T608	8		T524	5		T842	1
values[61]	163	1			T608	18		T524	3		T842	1
values[62]	131	1			T608	9		T524	1		T842	1
values[63]	165	1			T608	21		T524	1		T842	1
values[64]	171	1			T608	4		T524	5		T842	1
values[65]	120	1			T608	7		T524	3		T842	1
values[66]	134	1			T608	11		T524	7		T842	1
values[67]	132	1			T608	10		T524	3		T842	1
values[68]	114	1			T608	4		T524	8		T842	1
values[69]	120	1			T608	3		T524	10		T842	1
values[70]	95	1			T608	3		T524	9		T842	1
values[71]	88	1			T608	4		T524	9		T842	1
values[72]	82	1			T608	2		T524	9		T842	1
values[73]	70	1			T608	5		T524	7		T842	1
values[74]	59	1			T608	10		T524	4		T842	1
values[75]	69	1			T608	4		T524	7		T842	1
values[76]	50	1			T524	5		T842	1		T586	3
values[77]	38	1			T524	6		T842	1		T586	5
values[78]	40	1			T524	6		T842	1		T586	7
values[79]	58	1			T524	13		T842	1		T586	6
values[80]	58	1			T524	5		T842	1		T586	7
values[81]	58	1			T524	4		T842	1		T586	7
values[82]	51	1			T524	10		T842	1		T586	8
values[83]	45	1			T524	14		T842	1		T586	5
values[84]	51	1			T524	5		T842	1		T586	4
values[85]	51	1			T524	8		T842	1		T586	11
values[86]	45	1			T524	1		T842	1		T586	6
values[87]	55	1			T524	6		T842	2		T586	4
values[88]	52	1			T524	11		T842	1		T586	2
values[89]	39	1			T524	3		T842	1		T586	2
values[90]	50	1			T524	4		T842	1		T586	8
values[91]	43	1			T524	1		T842	1		T586	3
values[92]	52	1			T524	6		T842	1		T586	5
values[93]	55	1			T524	6		T842	1		T586	2
values[94]	51	1			T524	8		T842	1		T586	4
values[95]	58	1			T524	3		T842	1		T586	14
values[96]	45	1			T524	5		T842	1		T586	5
values[97]	81	1			T524	5		T842	4		T586	12
values[98]	69	1			T524	4		T842	1		T586	10
values[99]	82	1			T524	6		T842	2		T586	10
values[100]	67	1			T524	8		T842	2		T586	6
values[101]	66	1			T524	5		T842	3		T586	5
values[102]	57	1			T524	2		T842	7		T586	8
values[103]	51	1			T524	5		T842	6		T586	5
values[104]	68	1			T524	12		T842	4		T586	5
values[105]	62	1			T524	4		T842	2		T586	9
values[106]	53	1			T524	2		T842	2		T586	5
values[107]	64	1			T842	4		T586	6		T830	2
values[108]	59	1			T842	1		T586	15		T830	3
values[109]	63	1			T842	4		T586	6		T830	2
values[110]	62	1			T842	4		T586	6		T830	2
values[111]	55	1			T842	3		T586	4		T830	3
values[112]	46	1			T842	1		T586	3		T830	3
values[113]	58	1			T842	1		T586	7		T830	1
values[114]	52	1			T842	1		T586	9		T830	2
values[115]	49	1			T842	4		T586	6		T830	3
values[116]	56	1			T842	1		T586	10		T830	1
values[117]	62	1			T842	1		T586	12		T830	1
values[118]	51	1			T842	1		T586	7		T830	2
values[119]	64	1			T842	2		T586	5		T830	1
values[120]	62	1			T842	2		T586	8		T830	1
values[121]	54	1			T842	2		T586	8		T830	9
values[122]	52	1			T842	3		T586	7		T830	1
values[123]	72	1			T842	4		T586	17		T830	2
values[124]	62	1			T842	2		T586	12		T830	4
values[125]	87	1			T842	1		T586	18		T830	1
values[126]	190	1			T842	5		T586	41		T830	3
values[127]	770	1			T842	19		T586	85		T830	28
values[128]	5043	1			T842	290		T586	36		T830	293