Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.08	95.51	93.81	95.54		94.55	97.53	99.52

Total tests in report: 2930

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.50	39.50	44.64	44.64	43.00	43.00	31.48	31.48			57.87	57.87	59.62	59.62	0.39	0.39	/workspace/coverage/default/92.chip_sw_all_escalation_resets.2923143090
50.46	10.96	55.33	10.69	56.87	13.88	35.58	4.10			68.67	10.80	84.79	25.17	1.52	1.13	/workspace/coverage/cover_reg_top/4.chip_csr_aliasing.1665711787
56.50	6.04	67.78	12.45	65.37	8.49	39.34	3.76			80.19	11.52	84.79	0.00	1.52	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.1666947176
62.47	5.97	67.78	0.01	67.40	2.04	39.38	0.04			80.27	0.08	84.79	0.00	35.18	33.66	/workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.2221862186
65.95	3.49	73.85	6.07	71.79	4.38	43.28	3.90			82.27	2.00	89.34	4.55	35.18	0.00	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2951333641
69.14	3.18	80.62	6.77	72.03	0.24	47.62	4.34			82.30	0.03	89.34	0.00	42.91	7.73	/workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.931425415
71.72	2.58	84.19	3.57	74.75	2.73	54.47	6.85			84.17	1.87	89.51	0.17	43.20	0.29	/workspace/coverage/default/1.chip_jtag_csr_rw.2617184110
74.18	2.46	84.19	0.00	74.83	0.07	54.47	0.00			84.17	0.00	89.51	0.00	57.91	14.71	/workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.286159944
76.53	2.35	84.19	0.00	74.83	0.00	68.58	14.11			84.17	0.00	89.51	0.00	57.91	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3502379749
78.27	1.74	84.27	0.08	74.84	0.01	78.71	10.13			84.18	0.01	89.69	0.17	57.91	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.423501252
79.89	1.62	86.44	2.17	78.10	3.26	79.23	0.52			87.59	3.42	90.03	0.35	57.91	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2403318642
81.37	1.48	86.44	0.00	78.10	0.00	79.23	0.00			87.59	0.00	90.03	0.00	66.81	8.89	/workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.970314222
82.54	1.17	87.55	1.11	79.35	1.25	82.52	3.28			88.65	1.05	90.38	0.35	66.81	0.00	/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2936908692
83.70	1.15	87.55	0.00	79.35	0.00	82.52	0.00			88.65	0.00	90.38	0.00	73.72	6.91	/workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.68270731
84.64	0.95	87.55	0.00	79.35	0.00	82.52	0.00			88.65	0.00	90.38	0.00	79.39	5.68	/workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.4024747958
85.48	0.83	88.25	0.70	79.50	0.15	82.68	0.16			88.80	0.15	94.23	3.85	79.39	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3139785285
86.25	0.78	89.28	1.03	80.45	0.95	82.85	0.17			89.75	0.96	95.80	1.57	79.39	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1783175922
86.99	0.74	89.29	0.01	84.46	4.01	82.86	0.01			89.76	0.01	95.80	0.00	79.79	0.40	/workspace/coverage/cover_reg_top/4.chip_tl_errors.851260876
87.69	0.70	89.29	0.00	84.47	0.01	82.86	0.00			89.76	0.00	95.80	0.00	83.97	4.18	/workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.2115047956
88.38	0.69	90.03	0.74	85.02	0.55	85.10	2.24			90.38	0.62	95.80	0.00	83.97	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.3047333884
89.01	0.62	91.22	1.20	86.10	1.08	85.35	0.25			91.59	1.22	95.80	0.00	83.97	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.2038773541
89.61	0.61	91.22	0.00	86.10	0.00	85.35	0.00			91.59	0.00	95.80	0.00	87.60	3.63	/workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.3186800293
90.10	0.49	91.99	0.77	86.18	0.09	85.80	0.44			91.63	0.03	95.80	0.00	89.20	1.60	/workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.2738908729
90.55	0.44	92.04	0.05	86.24	0.06	86.57	0.77			91.63	0.00	95.80	0.00	90.99	1.79	/workspace/coverage/default/2.chip_sw_alert_test.1401150857
90.98	0.43	92.42	0.38	86.62	0.37	87.98	1.41			92.07	0.45	95.80	0.00	90.99	0.00	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.3131233742
91.36	0.38	92.42	0.00	86.62	0.00	87.98	0.00			92.07	0.00	95.80	0.00	93.24	2.26	/workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.2822560133
91.71	0.35	93.00	0.58	87.64	1.02	88.05	0.08			92.51	0.44	95.80	0.00	93.24	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.3048244793
92.04	0.33	93.52	0.52	88.29	0.65	88.37	0.32			93.00	0.49	95.80	0.00	93.24	0.00	/workspace/coverage/default/1.chip_sw_gpio.2386379536
92.30	0.26	93.52	0.00	88.38	0.09	88.37	0.00			93.01	0.02	95.80	0.00	94.69	1.45	/workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.2650406519
92.53	0.23	93.52	0.00	88.38	0.00	89.76	1.39			93.01	0.00	95.80	0.00	94.69	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2540757015
92.75	0.22	93.52	0.00	88.43	0.05	89.76	0.00			93.03	0.02	95.80	0.00	95.93	1.25	/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.859961868
92.94	0.19	93.80	0.28	88.70	0.27	90.18	0.42			93.21	0.18	95.80	0.00	95.93	0.00	/workspace/coverage/default/2.chip_jtag_csr_rw.3213759786
93.12	0.18	93.80	0.00	89.75	1.05	90.18	0.00			93.21	0.00	95.80	0.00	95.96	0.02	/workspace/coverage/cover_reg_top/0.chip_tl_errors.1583982150
93.27	0.15	93.81	0.01	90.18	0.43	90.18	0.00			93.68	0.47	95.80	0.00	95.96	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3479031404
93.41	0.15	93.81	0.00	90.27	0.09	90.18	0.00			93.70	0.02	95.80	0.00	96.72	0.76	/workspace/coverage/cover_reg_top/75.xbar_stress_all.4214290748
93.56	0.14	93.88	0.07	90.44	0.18	90.38	0.20			93.77	0.07	96.15	0.35	96.72	0.00	/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1051139971
93.70	0.14	93.88	0.00	90.44	0.00	91.20	0.83			93.77	0.00	96.15	0.00	96.72	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2076906845
93.83	0.13	94.06	0.19	90.74	0.30	91.52	0.32			93.77	0.00	96.15	0.00	96.72	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1749763415
93.96	0.13	94.21	0.15	90.82	0.08	91.62	0.10			93.87	0.10	96.50	0.35	96.72	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.927352312
94.07	0.12	94.21	0.00	90.82	0.00	92.28	0.66			93.87	0.00	96.50	0.00	96.76	0.04	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2028467425
94.19	0.12	94.21	0.00	91.02	0.20	92.28	0.00			93.87	0.00	96.50	0.00	97.25	0.49	/workspace/coverage/cover_reg_top/67.xbar_stress_all.1317972780
94.30	0.11	94.21	0.00	91.04	0.02	92.28	0.00			93.87	0.00	96.50	0.00	97.90	0.65	/workspace/coverage/cover_reg_top/82.xbar_random_large_delays.2919566668
94.40	0.10	94.21	0.00	91.04	0.00	92.86	0.58			93.87	0.00	96.50	0.00	97.90	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1655336781
94.48	0.08	94.21	0.00	91.04	0.00	93.37	0.51			93.87	0.00	96.50	0.00	97.90	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3699412813
94.56	0.07	94.21	0.00	91.49	0.44	93.37	0.00			93.87	0.00	96.50	0.00	97.90	0.00	/workspace/coverage/cover_reg_top/13.chip_tl_errors.1979516443
94.63	0.07	94.28	0.07	91.77	0.29	93.39	0.02			93.91	0.04	96.50	0.00	97.90	0.00	/workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.3970009579
94.69	0.07	94.29	0.01	91.81	0.03	93.57	0.18			93.92	0.02	96.68	0.17	97.90	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3938736375
94.76	0.06	94.41	0.12	91.92	0.11	93.62	0.05			94.03	0.11	96.68	0.00	97.90	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3241353236
94.82	0.06	94.41	0.00	91.92	0.00	93.97	0.35			94.03	0.00	96.68	0.00	97.90	0.00	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3310206738
94.87	0.05	94.41	0.00	91.95	0.03	93.97	0.00			94.03	0.00	96.68	0.00	98.19	0.29	/workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.1644331876
94.91	0.04	94.41	0.00	92.06	0.11	93.98	0.01			94.16	0.13	96.68	0.00	98.19	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.647708844
94.95	0.04	94.42	0.01	92.08	0.02	93.98	0.00			94.18	0.02	96.85	0.17	98.20	0.01	/workspace/coverage/default/48.chip_sw_all_escalation_resets.3643380952
94.99	0.04	94.45	0.03	92.08	0.01	93.98	0.01			94.19	0.01	97.03	0.17	98.21	0.01	/workspace/coverage/default/58.chip_sw_all_escalation_resets.15534657
95.03	0.04	94.45	0.00	92.08	0.00	94.20	0.22			94.19	0.00	97.03	0.00	98.21	0.00	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3208757440
95.06	0.04	94.45	0.01	92.09	0.01	94.21	0.01			94.20	0.01	97.20	0.17	98.23	0.01	/workspace/coverage/default/10.chip_sw_all_escalation_resets.4254066629
95.10	0.04	94.46	0.01	92.10	0.01	94.21	0.01			94.21	0.01	97.38	0.17	98.24	0.01	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2342609497
95.13	0.04	94.46	0.00	92.32	0.21	94.21	0.00			94.21	0.00	97.38	0.00	98.24	0.00	/workspace/coverage/cover_reg_top/29.chip_tl_errors.3295027031
95.17	0.03	94.46	0.00	92.32	0.00	94.42	0.21			94.21	0.00	97.38	0.00	98.24	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3457965089
95.20	0.03	94.46	0.00	92.32	0.00	94.45	0.03			94.21	0.00	97.55	0.17	98.24	0.00	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.1933763032
95.23	0.03	94.53	0.07	92.32	0.00	94.53	0.08			94.22	0.01	97.55	0.00	98.24	0.00	/workspace/coverage/default/3.chip_tap_straps_testunlock0.826366210
95.26	0.03	94.59	0.06	92.34	0.03	94.56	0.02			94.26	0.05	97.55	0.00	98.24	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.4275529119
95.28	0.03	94.59	0.00	92.50	0.15	94.56	0.00			94.26	0.00	97.55	0.00	98.24	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.1621711714
95.31	0.02	94.66	0.07	92.54	0.05	94.56	0.00			94.30	0.03	97.55	0.00	98.24	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.3537898100
95.33	0.02	94.66	0.00	92.57	0.03	94.56	0.00			94.30	0.00	97.55	0.00	98.36	0.12	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.3265865580
95.35	0.02	94.66	0.00	92.66	0.09	94.56	0.00			94.33	0.03	97.55	0.00	98.37	0.01	/workspace/coverage/cover_reg_top/53.xbar_stress_all.12489738
95.38	0.02	94.66	0.01	92.66	0.00	94.67	0.12			94.34	0.01	97.55	0.00	98.37	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2179712091
95.40	0.02	94.67	0.01	92.72	0.06	94.67	0.00			94.40	0.06	97.55	0.00	98.37	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.508711958
95.42	0.02	94.73	0.07	92.76	0.05	94.67	0.00			94.42	0.02	97.55	0.00	98.37	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.599410537
95.44	0.02	94.73	0.00	92.79	0.02	94.74	0.07			94.43	0.02	97.55	0.00	98.38	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.2064728469
95.46	0.02	94.73	0.00	92.79	0.00	94.74	0.00			94.43	0.00	97.55	0.00	98.50	0.12	/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.2172104117
95.48	0.02	94.73	0.00	92.79	0.00	94.85	0.11			94.43	0.00	97.55	0.00	98.50	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2645431140
95.49	0.02	94.76	0.03	92.80	0.01	94.89	0.05			94.43	0.00	97.55	0.00	98.51	0.01	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3084206564
95.51	0.01	94.76	0.00	92.88	0.09	94.89	0.00			94.43	0.00	97.55	0.00	98.51	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.3695970078
95.52	0.01	94.76	0.00	92.96	0.07	94.89	0.00			94.43	0.00	97.55	0.00	98.52	0.01	/workspace/coverage/cover_reg_top/9.chip_tl_errors.49858012
95.53	0.01	94.76	0.00	93.02	0.06	94.89	0.00			94.45	0.02	97.55	0.00	98.52	0.00	/workspace/coverage/cover_reg_top/64.xbar_stress_all.4286477722
95.55	0.01	94.76	0.00	93.10	0.08	94.89	0.00			94.45	0.00	97.55	0.00	98.52	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.2793561456
95.56	0.01	94.76	0.00	93.10	0.00	94.89	0.00			94.45	0.00	97.55	0.00	98.59	0.07	/workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.1416421582
95.57	0.01	94.78	0.01	93.13	0.03	94.90	0.01			94.47	0.02	97.55	0.00	98.59	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1498294996
95.58	0.01	94.78	0.00	93.13	0.00	94.97	0.07			94.47	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1335456611
95.59	0.01	94.79	0.01	93.15	0.02	95.00	0.03			94.47	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3611134903
95.60	0.01	94.79	0.00	93.21	0.06	95.00	0.00			94.47	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.1165941031
95.61	0.01	94.79	0.00	93.21	0.00	95.06	0.06			94.47	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.983661126
95.62	0.01	94.79	0.00	93.27	0.06	95.06	0.00			94.47	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/cover_reg_top/1.chip_tl_errors.2070628940
95.63	0.01	94.79	0.00	93.29	0.02	95.06	0.00			94.47	0.00	97.55	0.00	98.63	0.04	/workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.936768284
95.64	0.01	94.79	0.00	93.29	0.00	95.11	0.06			94.47	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2938011357
95.65	0.01	94.79	0.00	93.29	0.01	95.16	0.05			94.47	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2889961326
95.66	0.01	94.81	0.02	93.30	0.01	95.16	0.01			94.48	0.02	97.55	0.00	98.63	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1335208478
95.66	0.01	94.83	0.02	93.31	0.01	95.17	0.01			94.50	0.02	97.55	0.00	98.63	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.550734151
95.67	0.01	94.85	0.02	93.31	0.01	95.17	0.01			94.52	0.02	97.55	0.00	98.63	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1722937305
95.68	0.01	94.87	0.02	93.32	0.01	95.18	0.01			94.53	0.02	97.55	0.00	98.63	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1751535468
95.69	0.01	94.87	0.00	93.37	0.05	95.18	0.00			94.53	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.281396657
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95.93	0.01	94.91	0.00	93.68	0.00	95.43	0.00			94.54	0.00	97.55	0.00	99.44	0.01	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3509410028
95.93	0.01	94.91	0.00	93.68	0.00	95.43	0.00			94.54	0.00	97.55	0.00	99.45	0.01	/workspace/coverage/default/74.chip_sw_all_escalation_resets.1130582037
95.93	0.01	94.91	0.00	93.68	0.00	95.43	0.00			94.54	0.00	97.55	0.00	99.46	0.01	/workspace/coverage/default/76.chip_sw_all_escalation_resets.3891485019
95.93	0.01	94.91	0.00	93.68	0.00	95.43	0.00			94.54	0.00	97.55	0.00	99.47	0.01	/workspace/coverage/default/81.chip_sw_all_escalation_resets.3257274101
95.93	0.01	94.91	0.00	93.68	0.00	95.43	0.00			94.54	0.00	97.55	0.00	99.48	0.01	/workspace/coverage/default/82.chip_sw_all_escalation_resets.3699567140
95.93	0.01	94.91	0.00	93.68	0.00	95.43	0.00			94.54	0.00	97.55	0.00	99.49	0.01	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2908343959
95.94	0.01	94.91	0.00	93.68	0.00	95.43	0.00			94.54	0.00	97.55	0.00	99.51	0.01	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.920726813
95.94	0.01	94.91	0.00	93.68	0.00	95.43	0.00			94.54	0.00	97.55	0.00	99.52	0.01	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2936333726
95.94	0.01	94.91	0.00	93.69	0.01	95.43	0.01			94.54	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4147869507
95.94	0.01	94.91	0.00	93.69	0.00	95.44	0.01			94.54	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2804255999
95.94	0.01	94.91	0.00	93.69	0.00	95.46	0.01			94.54	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.545117386
95.95	0.01	94.91	0.00	93.70	0.01	95.46	0.00			94.54	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.4243258943
95.95	0.01	94.91	0.00	93.71	0.01	95.46	0.00			94.54	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2755651483
95.95	0.01	94.91	0.00	93.72	0.01	95.46	0.00			94.54	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.79283504
95.95	0.01	94.91	0.00	93.73	0.01	95.46	0.00			94.54	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.245223723
95.95	0.01	94.91	0.00	93.73	0.00	95.47	0.01			94.54	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1883787462
95.95	0.01	94.91	0.00	93.73	0.00	95.47	0.01			94.54	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3969945609
95.96	0.01	94.91	0.00	93.73	0.00	95.47	0.00			94.55	0.01	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3642017473
95.96	0.01	94.91	0.00	93.74	0.01	95.47	0.00			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/19.xbar_stress_all.409237859
95.96	0.01	94.91	0.00	93.75	0.01	95.47	0.00			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2586650342
95.96	0.01	94.91	0.00	93.75	0.01	95.47	0.00			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1994709537
95.96	0.01	94.91	0.00	93.76	0.01	95.47	0.00			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2457004335
95.96	0.01	94.91	0.00	93.76	0.00	95.48	0.01			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.476653166
95.96	0.01	94.91	0.00	93.76	0.00	95.49	0.01			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2625474995
95.96	0.01	94.92	0.01	93.76	0.00	95.49	0.00			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.490314424
95.97	0.01	94.93	0.01	93.76	0.00	95.49	0.00			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3924633296
95.97	0.01	94.93	0.01	93.76	0.00	95.49	0.00			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1128199181
95.97	0.01	94.93	0.00	93.76	0.00	95.49	0.01			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1826194689
95.97	0.01	94.93	0.00	93.76	0.00	95.50	0.01			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2156851453
95.97	0.01	94.93	0.00	93.76	0.00	95.50	0.01			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.2609498416
95.97	0.01	94.93	0.00	93.76	0.00	95.51	0.01			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_kmac_idle.2391117374
95.97	0.01	94.93	0.00	93.76	0.00	95.51	0.01			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2633678901
95.97	0.01	94.93	0.00	93.76	0.00	95.52	0.01			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3880555681
95.97	0.01	94.93	0.00	93.76	0.00	95.52	0.01			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.419748775
95.97	0.01	94.93	0.00	93.76	0.01	95.52	0.00			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.4189454483
95.97	0.01	94.93	0.00	93.77	0.01	95.52	0.00			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/11.chip_tl_errors.870282561
95.97	0.01	94.93	0.00	93.77	0.01	95.52	0.00			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1019066561
95.97	0.01	94.93	0.00	93.77	0.01	95.52	0.00			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.402114136
95.98	0.01	94.93	0.00	93.78	0.01	95.52	0.00			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.2378730686
95.98	0.01	94.93	0.00	93.78	0.01	95.52	0.00			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.2733722600
95.98	0.01	94.93	0.00	93.78	0.01	95.52	0.00			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.1054313242
95.98	0.01	94.93	0.00	93.79	0.01	95.52	0.00			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.1222868522
95.98	0.01	94.93	0.00	93.79	0.01	95.52	0.00			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.4141675059
95.98	0.01	94.93	0.00	93.80	0.01	95.52	0.00			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.3853527411
95.98	0.01	94.93	0.00	93.80	0.01	95.52	0.00			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_gpio.3257475474
95.98	0.01	94.93	0.00	93.80	0.01	95.52	0.00			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.927599464
95.98	0.01	94.93	0.00	93.81	0.01	95.52	0.00			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3146056174
95.98	0.01	94.93	0.00	93.81	0.00	95.52	0.01			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3310233795
95.98	0.01	94.93	0.00	93.81	0.00	95.53	0.01			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/2.chip_tap_straps_testunlock0.3084811117
95.98	0.01	94.93	0.00	93.81	0.00	95.53	0.01			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.4168888589
95.98	0.01	94.93	0.00	93.81	0.00	95.53	0.01			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.681696388
95.98	0.01	94.93	0.00	93.81	0.00	95.54	0.01			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.3812972888
95.98	0.01	94.93	0.00	93.81	0.00	95.54	0.01			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3437388878
95.98	0.01	94.93	0.00	93.81	0.00	95.54	0.01			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2992325616
95.98	0.01	94.93	0.00	93.81	0.00	95.54	0.01			94.55	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.397037941

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.669286588
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1249811269
/workspace/coverage/cover_reg_top/0.chip_csr_rw.2208591699
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.2685671155
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.3860444154
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2441857371
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.50266189
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3792316317
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3409292776
/workspace/coverage/cover_reg_top/0.xbar_error_random.3063553634
/workspace/coverage/cover_reg_top/0.xbar_random.2511232089
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2570525063
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.4282094688
/workspace/coverage/cover_reg_top/0.xbar_same_source.1347598925
/workspace/coverage/cover_reg_top/0.xbar_smoke.1418555821
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2306615054
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2926723239
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3834336322
/workspace/coverage/cover_reg_top/0.xbar_stress_all.735892965
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3924048799
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3767219703
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.512346879
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2758921516
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3386059724
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1014486425
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.2249592505
/workspace/coverage/cover_reg_top/1.chip_csr_rw.3873415307
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.226839631
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3782217695
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3385727252
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.1791385029
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2714951359
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1471131733
/workspace/coverage/cover_reg_top/1.xbar_error_random.262148850
/workspace/coverage/cover_reg_top/1.xbar_random.931798645
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2991941506
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.369552092
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.2854997038
/workspace/coverage/cover_reg_top/1.xbar_same_source.930757159
/workspace/coverage/cover_reg_top/1.xbar_smoke.4173413830
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1313649397
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3268939512
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2443799623
/workspace/coverage/cover_reg_top/1.xbar_stress_all.3365210135
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.726765561
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2421752922
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.535275579
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.1963324438
/workspace/coverage/cover_reg_top/10.chip_csr_rw.2345134623
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1193507796
/workspace/coverage/cover_reg_top/10.chip_tl_errors.3796653557
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.2396396581
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1494560920
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.476828481
/workspace/coverage/cover_reg_top/10.xbar_error_random.691010806
/workspace/coverage/cover_reg_top/10.xbar_random.1019518898
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.501402059
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3980761948
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.2564005998
/workspace/coverage/cover_reg_top/10.xbar_same_source.3201661665
/workspace/coverage/cover_reg_top/10.xbar_smoke.2063164458
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.843789821
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2715814609
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.114703556
/workspace/coverage/cover_reg_top/10.xbar_stress_all.508149571
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.1928303990
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.4173927953
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1194785383
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.3540276332
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.332718502
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2890611164
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.1666170383
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2205206361
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3344801363
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3199241403
/workspace/coverage/cover_reg_top/11.xbar_error_random.2226035236
/workspace/coverage/cover_reg_top/11.xbar_random.4269749339
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.169674551
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.1562950521
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3324460861
/workspace/coverage/cover_reg_top/11.xbar_same_source.21856151
/workspace/coverage/cover_reg_top/11.xbar_smoke.2132877085
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.267817703
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.1205429283
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3449705569
/workspace/coverage/cover_reg_top/11.xbar_stress_all.3962485761
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.437800267
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.1669282868
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.941236608
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.1012818734
/workspace/coverage/cover_reg_top/12.chip_csr_rw.4090698289
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2196230684
/workspace/coverage/cover_reg_top/12.chip_tl_errors.3003551420
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.174326107
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.530825974
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1506190755
/workspace/coverage/cover_reg_top/12.xbar_error_random.2683902771
/workspace/coverage/cover_reg_top/12.xbar_random.545577672
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.4166483834
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2434196616
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1258327360
/workspace/coverage/cover_reg_top/12.xbar_same_source.3637550712
/workspace/coverage/cover_reg_top/12.xbar_smoke.544214472
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/workspace/coverage/default/91.chip_sw_all_escalation_resets.1527616897
/workspace/coverage/default/93.chip_sw_all_escalation_resets.556276282
/workspace/coverage/default/94.chip_sw_all_escalation_resets.2266523219
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/workspace/coverage/default/96.chip_sw_all_escalation_resets.2912124251
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3316206641
/workspace/coverage/default/98.chip_sw_all_escalation_resets.2972135130
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2301204174
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/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3543678333
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/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2143902447
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3885295947
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2128188782
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.463565382
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.944148953

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Total test records in report: 2930

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.2683010664			Jul 23 07:35:06 PM PDT 24	Jul 23 07:39:21 PM PDT 24	2477445479 ps
T2	/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2063698379			Jul 23 07:34:12 PM PDT 24	Jul 23 07:43:08 PM PDT 24	4807095852 ps
T3	/workspace/coverage/default/1.chip_jtag_csr_rw.2617184110			Jul 23 07:42:41 PM PDT 24	Jul 23 08:07:37 PM PDT 24	12678701836 ps
T4	/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.2971140573			Jul 23 07:48:11 PM PDT 24	Jul 23 08:04:05 PM PDT 24	5273722120 ps
T5	/workspace/coverage/default/92.chip_sw_all_escalation_resets.2923143090			Jul 23 08:12:40 PM PDT 24	Jul 23 08:21:59 PM PDT 24	4593923550 ps
T6	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.978228862			Jul 23 07:58:11 PM PDT 24	Jul 23 08:14:53 PM PDT 24	9329744248 ps
T81	/workspace/coverage/default/2.chip_sw_rv_timer_irq.2003561608			Jul 23 07:55:54 PM PDT 24	Jul 23 08:00:38 PM PDT 24	3440248576 ps
T82	/workspace/coverage/default/0.chip_sw_aes_smoketest.367755025			Jul 23 07:41:22 PM PDT 24	Jul 23 07:46:42 PM PDT 24	3524077544 ps
T44	/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2936908692			Jul 23 08:04:47 PM PDT 24	Jul 23 09:07:27 PM PDT 24	15818194744 ps
T7	/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.423501252			Jul 23 07:55:56 PM PDT 24	Jul 23 09:24:40 PM PDT 24	45867860440 ps
T121	/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3792042292			Jul 23 07:35:34 PM PDT 24	Jul 23 07:52:10 PM PDT 24	5238933718 ps
T160	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3139785285			Jul 23 07:36:25 PM PDT 24	Jul 23 07:40:30 PM PDT 24	3248425384 ps
T32	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3611134903			Jul 23 08:05:55 PM PDT 24	Jul 23 08:11:30 PM PDT 24	2726515664 ps
T300	/workspace/coverage/default/0.chip_sw_hmac_smoketest.761214524			Jul 23 07:40:21 PM PDT 24	Jul 23 07:47:10 PM PDT 24	3500755372 ps
T17	/workspace/coverage/default/0.chip_sw_usbdev_dpi.2955782455			Jul 23 07:32:14 PM PDT 24	Jul 23 08:26:27 PM PDT 24	11497457228 ps
T62	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.597115362			Jul 23 07:56:31 PM PDT 24	Jul 23 08:06:21 PM PDT 24	4367497814 ps
T180	/workspace/coverage/default/2.chip_plic_all_irqs_10.3047333884			Jul 23 07:58:39 PM PDT 24	Jul 23 08:09:50 PM PDT 24	3911965864 ps
T67	/workspace/coverage/default/3.chip_tap_straps_testunlock0.826366210			Jul 23 08:02:37 PM PDT 24	Jul 23 08:16:18 PM PDT 24	8519510271 ps
T115	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.502114696			Jul 23 07:34:28 PM PDT 24	Jul 23 07:43:59 PM PDT 24	5318761960 ps
T61	/workspace/coverage/default/0.rom_volatile_raw_unlock.3995793483			Jul 23 07:40:29 PM PDT 24	Jul 23 07:42:17 PM PDT 24	2786680525 ps
T304	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2548006328			Jul 23 07:47:27 PM PDT 24	Jul 23 07:56:00 PM PDT 24	4008783672 ps
T320	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3084206564			Jul 23 08:10:02 PM PDT 24	Jul 23 08:17:23 PM PDT 24	3510167380 ps
T63	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.2064728469			Jul 23 07:46:11 PM PDT 24	Jul 23 07:56:27 PM PDT 24	5380996880 ps
T215	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1751831165			Jul 23 08:09:57 PM PDT 24	Jul 23 08:18:31 PM PDT 24	3450417860 ps
T895	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3667337893			Jul 23 07:58:20 PM PDT 24	Jul 23 08:06:42 PM PDT 24	3936214940 ps
T45	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.6219311			Jul 23 08:05:30 PM PDT 24	Jul 23 09:00:51 PM PDT 24	14584496620 ps
T60	/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3561198502			Jul 23 08:02:27 PM PDT 24	Jul 23 08:10:36 PM PDT 24	6136816195 ps
T157	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.3939786201			Jul 23 08:02:30 PM PDT 24	Jul 23 08:13:44 PM PDT 24	5564575394 ps
T295	/workspace/coverage/default/2.chip_sw_aes_masking_off.342719025			Jul 23 07:57:11 PM PDT 24	Jul 23 08:02:09 PM PDT 24	2755752855 ps
T296	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1009440426			Jul 23 07:40:53 PM PDT 24	Jul 23 07:45:11 PM PDT 24	3088614566 ps
T46	/workspace/coverage/default/2.rom_e2e_asm_init_prod.1589830662			Jul 23 08:04:44 PM PDT 24	Jul 23 09:04:27 PM PDT 24	15933397569 ps
T18	/workspace/coverage/default/0.chip_sw_usbdev_pullup.1059251862			Jul 23 07:32:34 PM PDT 24	Jul 23 07:36:27 PM PDT 24	3045174642 ps
T297	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.3240719856			Jul 23 07:45:53 PM PDT 24	Jul 23 09:03:28 PM PDT 24	14225660100 ps
T298	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3142747269			Jul 23 08:08:51 PM PDT 24	Jul 23 08:15:16 PM PDT 24	4262466520 ps
T299	/workspace/coverage/default/1.chip_sw_aes_idle.3975462322			Jul 23 07:48:16 PM PDT 24	Jul 23 07:52:13 PM PDT 24	3012195774 ps
T158	/workspace/coverage/default/3.chip_sw_all_escalation_resets.219740719			Jul 23 08:02:41 PM PDT 24	Jul 23 08:12:21 PM PDT 24	4359803160 ps
T184	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1595372542			Jul 23 08:06:34 PM PDT 24	Jul 23 08:13:55 PM PDT 24	3466775440 ps
T122	/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3633531046			Jul 23 08:04:58 PM PDT 24	Jul 23 09:18:18 PM PDT 24	15467748688 ps
T216	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1544058891			Jul 23 08:06:31 PM PDT 24	Jul 23 08:15:20 PM PDT 24	4305927402 ps
T113	/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2115239654			Jul 23 07:44:00 PM PDT 24	Jul 23 08:01:18 PM PDT 24	6410108927 ps
T400	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3861191786			Jul 23 08:07:32 PM PDT 24	Jul 23 08:15:23 PM PDT 24	3529175330 ps
T896	/workspace/coverage/default/2.chip_sw_example_rom.1010417925			Jul 23 07:52:31 PM PDT 24	Jul 23 07:54:41 PM PDT 24	2936428674 ps
T401	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2275246124			Jul 23 08:13:06 PM PDT 24	Jul 23 08:21:21 PM PDT 24	4129176282 ps
T159	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.170535016			Jul 23 07:32:14 PM PDT 24	Jul 23 07:51:19 PM PDT 24	6317717316 ps
T68	/workspace/coverage/default/0.chip_jtag_mem_access.3551001726			Jul 23 07:27:26 PM PDT 24	Jul 23 07:53:28 PM PDT 24	13635181088 ps
T897	/workspace/coverage/default/0.chip_sw_example_flash.414409012			Jul 23 07:32:30 PM PDT 24	Jul 23 07:36:41 PM PDT 24	2511632400 ps
T8	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2403318642			Jul 23 07:35:05 PM PDT 24	Jul 23 07:38:40 PM PDT 24	2911111945 ps
T204	/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.390023509			Jul 23 07:33:44 PM PDT 24	Jul 23 07:45:33 PM PDT 24	4913067224 ps
T118	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.245223723			Jul 23 07:36:18 PM PDT 24	Jul 23 07:46:29 PM PDT 24	6945168026 ps
T754	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1723571658			Jul 23 08:09:15 PM PDT 24	Jul 23 08:18:19 PM PDT 24	3751273456 ps
T898	/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.3780836609			Jul 23 07:50:59 PM PDT 24	Jul 23 07:56:46 PM PDT 24	2989969144 ps
T266	/workspace/coverage/default/61.chip_sw_all_escalation_resets.688675766			Jul 23 08:11:11 PM PDT 24	Jul 23 08:22:42 PM PDT 24	6092728416 ps
T455	/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3279503291			Jul 23 07:38:31 PM PDT 24	Jul 23 07:53:22 PM PDT 24	5689935730 ps
T259	/workspace/coverage/default/0.chip_sw_plic_sw_irq.874924704			Jul 23 07:36:32 PM PDT 24	Jul 23 07:42:04 PM PDT 24	3565147560 ps
T21	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3172465381			Jul 23 07:57:44 PM PDT 24	Jul 23 08:52:47 PM PDT 24	20415069745 ps
T116	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.983661126			Jul 23 07:35:42 PM PDT 24	Jul 23 07:44:28 PM PDT 24	3985971878 ps
T378	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.854341210			Jul 23 08:08:31 PM PDT 24	Jul 23 08:16:46 PM PDT 24	3552084960 ps
T262	/workspace/coverage/default/1.chip_plic_all_irqs_0.1666947176			Jul 23 07:52:48 PM PDT 24	Jul 23 08:10:13 PM PDT 24	5787257540 ps
T14	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1783175922			Jul 23 07:34:14 PM PDT 24	Jul 23 07:39:13 PM PDT 24	3542388412 ps
T95	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.956602299			Jul 23 07:59:25 PM PDT 24	Jul 23 08:06:15 PM PDT 24	4066073358 ps
T51	/workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.4046204813			Jul 23 07:54:34 PM PDT 24	Jul 23 07:58:43 PM PDT 24	3356194388 ps
T96	/workspace/coverage/default/0.chip_sw_usbdev_vbus.1312317754			Jul 23 07:32:21 PM PDT 24	Jul 23 07:35:55 PM PDT 24	2949346620 ps
T97	/workspace/coverage/default/2.rom_keymgr_functest.2050050883			Jul 23 08:02:48 PM PDT 24	Jul 23 08:10:35 PM PDT 24	4138293390 ps
T98	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2889961326			Jul 23 07:34:20 PM PDT 24	Jul 23 08:17:48 PM PDT 24	26162859967 ps
T99	/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2993054195			Jul 23 08:03:24 PM PDT 24	Jul 23 08:48:58 PM PDT 24	13112553752 ps
T100	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1360026022			Jul 23 07:42:48 PM PDT 24	Jul 23 07:53:54 PM PDT 24	4708462704 ps
T101	/workspace/coverage/default/2.chip_plic_all_irqs_20.2793561456			Jul 23 07:58:57 PM PDT 24	Jul 23 08:13:14 PM PDT 24	5290406824 ps
T102	/workspace/coverage/default/0.chip_sw_csrng_kat_test.3983912122			Jul 23 07:33:38 PM PDT 24	Jul 23 07:37:07 PM PDT 24	2948708270 ps
T139	/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.3283523842			Jul 23 07:50:03 PM PDT 24	Jul 23 07:53:17 PM PDT 24	2586031509 ps
T53	/workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.4140840675			Jul 23 07:48:18 PM PDT 24	Jul 23 07:54:20 PM PDT 24	3748207911 ps
T148	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3208757440			Jul 23 07:54:08 PM PDT 24	Jul 23 07:56:26 PM PDT 24	3296428977 ps
T692	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.580326960			Jul 23 07:34:02 PM PDT 24	Jul 23 07:44:15 PM PDT 24	4717716424 ps
T458	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3352870787			Jul 23 08:11:25 PM PDT 24	Jul 23 08:18:16 PM PDT 24	3169866156 ps
T726	/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1053407735			Jul 23 07:49:09 PM PDT 24	Jul 23 07:59:30 PM PDT 24	5512785504 ps
T402	/workspace/coverage/default/73.chip_sw_all_escalation_resets.464795951			Jul 23 08:11:24 PM PDT 24	Jul 23 08:21:33 PM PDT 24	5327556560 ps
T112	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.545117386			Jul 23 07:55:30 PM PDT 24	Jul 23 08:34:30 PM PDT 24	12339821095 ps
T19	/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2212427289			Jul 23 08:03:11 PM PDT 24	Jul 23 08:13:57 PM PDT 24	6054858202 ps
T108	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.3131233742			Jul 23 08:01:02 PM PDT 24	Jul 23 08:54:30 PM PDT 24	21000083831 ps
T318	/workspace/coverage/default/2.chip_sw_otbn_randomness.1260867128			Jul 23 07:55:48 PM PDT 24	Jul 23 08:12:14 PM PDT 24	6295166186 ps
T261	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2084994483			Jul 23 07:41:39 PM PDT 24	Jul 23 07:45:19 PM PDT 24	2123871450 ps
T410	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.3849948682			Jul 23 07:45:15 PM PDT 24	Jul 23 08:58:43 PM PDT 24	14870220536 ps
T15	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1160121386			Jul 23 07:42:47 PM PDT 24	Jul 23 11:23:54 PM PDT 24	78111159780 ps
T279	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3167791732			Jul 23 07:51:39 PM PDT 24	Jul 23 07:58:26 PM PDT 24	3713085660 ps
T899	/workspace/coverage/default/2.chip_sw_example_manufacturer.3399517134			Jul 23 07:53:11 PM PDT 24	Jul 23 07:56:05 PM PDT 24	2348713506 ps
T468	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.3481648708			Jul 23 07:44:29 PM PDT 24	Jul 23 07:54:03 PM PDT 24	8599237812 ps
T900	/workspace/coverage/default/0.chip_sw_aes_enc.1878882629			Jul 23 07:35:31 PM PDT 24	Jul 23 07:40:04 PM PDT 24	2633270574 ps
T175	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2362729130			Jul 23 07:56:29 PM PDT 24	Jul 23 08:57:41 PM PDT 24	17488353960 ps
T167	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3262054063			Jul 23 07:57:02 PM PDT 24	Jul 23 08:03:38 PM PDT 24	2812455674 ps
T379	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3968089737			Jul 23 08:04:56 PM PDT 24	Jul 23 08:11:00 PM PDT 24	3496915920 ps
T117	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1950953308			Jul 23 07:58:19 PM PDT 24	Jul 23 08:12:02 PM PDT 24	4894372104 ps
T728	/workspace/coverage/default/0.chip_sw_all_escalation_resets.550382936			Jul 23 07:33:05 PM PDT 24	Jul 23 07:45:27 PM PDT 24	6047956080 ps
T176	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3457965089			Jul 23 07:34:34 PM PDT 24	Jul 23 07:52:58 PM PDT 24	5941941696 ps
T901	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4037453842			Jul 23 07:48:55 PM PDT 24	Jul 23 07:59:19 PM PDT 24	4274378442 ps
T380	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3943275592			Jul 23 08:03:03 PM PDT 24	Jul 23 08:09:35 PM PDT 24	3499574700 ps
T227	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.248423791			Jul 23 07:54:32 PM PDT 24	Jul 23 08:20:37 PM PDT 24	9489867344 ps
T411	/workspace/coverage/default/1.rom_e2e_smoke.1041495600			Jul 23 07:56:04 PM PDT 24	Jul 23 09:02:55 PM PDT 24	14947882588 ps
T147	/workspace/coverage/default/2.chip_sw_power_idle_load.413864417			Jul 23 08:00:18 PM PDT 24	Jul 23 08:13:43 PM PDT 24	5066612820 ps
T221	/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.989757998			Jul 23 07:46:27 PM PDT 24	Jul 23 08:07:29 PM PDT 24	8503713838 ps
T224	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2884919182			Jul 23 07:49:12 PM PDT 24	Jul 23 08:30:22 PM PDT 24	21998937720 ps
T253	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.511042460			Jul 23 07:48:32 PM PDT 24	Jul 23 07:55:40 PM PDT 24	4878590312 ps
T109	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2625474995			Jul 23 07:37:26 PM PDT 24	Jul 23 07:49:56 PM PDT 24	19047760120 ps
T149	/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1703102855			Jul 23 07:34:52 PM PDT 24	Jul 23 07:37:30 PM PDT 24	3200021456 ps
T228	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.2332065445			Jul 23 07:55:11 PM PDT 24	Jul 23 08:23:35 PM PDT 24	9095372512 ps
T459	/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3612786113			Jul 23 07:48:47 PM PDT 24	Jul 23 07:52:14 PM PDT 24	2494314936 ps
T713	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.2609498416			Jul 23 07:36:59 PM PDT 24	Jul 23 07:42:14 PM PDT 24	2673723156 ps
T375	/workspace/coverage/default/2.rom_e2e_self_hash.29898510			Jul 23 08:06:24 PM PDT 24	Jul 23 09:45:27 PM PDT 24	26745014450 ps
T130	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1335208478			Jul 23 07:37:27 PM PDT 24	Jul 23 07:50:05 PM PDT 24	7660842648 ps
T376	/workspace/coverage/default/0.rom_e2e_asm_init_dev.1771587864			Jul 23 07:45:40 PM PDT 24	Jul 23 09:08:40 PM PDT 24	15577484173 ps
T226	/workspace/coverage/default/94.chip_sw_all_escalation_resets.2266523219			Jul 23 08:14:51 PM PDT 24	Jul 23 08:25:39 PM PDT 24	5316903784 ps
T902	/workspace/coverage/default/1.chip_sw_aes_entropy.3440023815			Jul 23 07:49:32 PM PDT 24	Jul 23 07:53:25 PM PDT 24	3585185444 ps
T403	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2089499581			Jul 23 08:07:11 PM PDT 24	Jul 23 08:12:52 PM PDT 24	4532367440 ps
T903	/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3349102721			Jul 23 07:53:22 PM PDT 24	Jul 23 08:02:02 PM PDT 24	3416275652 ps
T712	/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1865998539			Jul 23 08:12:35 PM PDT 24	Jul 23 08:19:19 PM PDT 24	3977465740 ps
T20	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.3329250852			Jul 23 07:31:58 PM PDT 24	Jul 23 09:37:42 PM PDT 24	32190106764 ps
T406	/workspace/coverage/default/39.chip_sw_all_escalation_resets.1442083045			Jul 23 08:08:11 PM PDT 24	Jul 23 08:20:49 PM PDT 24	4322656580 ps
T146	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.4249405209			Jul 23 08:03:48 PM PDT 24	Jul 23 08:13:23 PM PDT 24	3797470000 ps
T741	/workspace/coverage/default/49.chip_sw_all_escalation_resets.2902333621			Jul 23 08:09:39 PM PDT 24	Jul 23 08:19:30 PM PDT 24	4610875720 ps
T904	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.420954407			Jul 23 07:50:00 PM PDT 24	Jul 23 08:03:30 PM PDT 24	4362642584 ps
T905	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.2578661464			Jul 23 07:34:18 PM PDT 24	Jul 23 07:52:18 PM PDT 24	7300487952 ps
T342	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1987818391			Jul 23 07:47:46 PM PDT 24	Jul 23 07:52:42 PM PDT 24	3380609433 ps
T906	/workspace/coverage/default/1.rom_e2e_asm_init_rma.3031422074			Jul 23 07:55:52 PM PDT 24	Jul 23 08:59:59 PM PDT 24	15122655890 ps
T305	/workspace/coverage/default/1.chip_plic_all_irqs_20.2038773541			Jul 23 07:49:46 PM PDT 24	Jul 23 08:02:39 PM PDT 24	4912703048 ps
T267	/workspace/coverage/default/29.chip_sw_all_escalation_resets.1463843698			Jul 23 08:07:03 PM PDT 24	Jul 23 08:18:50 PM PDT 24	4845345348 ps
T64	/workspace/coverage/default/2.chip_tap_straps_testunlock0.3084811117			Jul 23 07:59:59 PM PDT 24	Jul 23 08:11:19 PM PDT 24	7274324399 ps
T205	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2425575050			Jul 23 07:58:36 PM PDT 24	Jul 23 08:12:49 PM PDT 24	7658627514 ps
T165	/workspace/coverage/default/1.chip_sw_inject_scramble_seed.1715269589			Jul 23 07:42:23 PM PDT 24	Jul 23 11:08:53 PM PDT 24	64264595799 ps
T460	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.4180931170			Jul 23 07:58:08 PM PDT 24	Jul 23 08:03:38 PM PDT 24	3205174444 ps
T329	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2389847961			Jul 23 07:33:55 PM PDT 24	Jul 23 07:41:52 PM PDT 24	4108408838 ps
T907	/workspace/coverage/default/1.rom_keymgr_functest.4272197310			Jul 23 07:52:55 PM PDT 24	Jul 23 08:04:15 PM PDT 24	4719853224 ps
T908	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3155806509			Jul 23 07:58:38 PM PDT 24	Jul 23 08:08:25 PM PDT 24	4840271200 ps
T822	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2319707104			Jul 23 08:07:12 PM PDT 24	Jul 23 08:13:33 PM PDT 24	3776133740 ps
T206	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1820713908			Jul 23 07:37:02 PM PDT 24	Jul 23 07:53:16 PM PDT 24	9221238636 ps
T59	/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3767593308			Jul 23 07:53:06 PM PDT 24	Jul 23 08:02:27 PM PDT 24	6281725600 ps
T185	/workspace/coverage/default/82.chip_sw_all_escalation_resets.3699567140			Jul 23 08:13:02 PM PDT 24	Jul 23 08:24:46 PM PDT 24	5341567992 ps
T731	/workspace/coverage/default/37.chip_sw_all_escalation_resets.3999601501			Jul 23 08:08:16 PM PDT 24	Jul 23 08:17:50 PM PDT 24	4377089192 ps
T909	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.4049114560			Jul 23 07:54:59 PM PDT 24	Jul 23 08:00:25 PM PDT 24	4363229288 ps
T222	/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.391313536			Jul 23 07:54:05 PM PDT 24	Jul 23 08:16:48 PM PDT 24	8328724684 ps
T111	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2076906845			Jul 23 07:38:47 PM PDT 24	Jul 23 09:14:14 PM PDT 24	29782265823 ps
T910	/workspace/coverage/default/0.rom_e2e_smoke.1826653241			Jul 23 07:40:52 PM PDT 24	Jul 23 08:45:27 PM PDT 24	14568310032 ps
T911	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1325357058			Jul 23 07:33:14 PM PDT 24	Jul 23 07:48:15 PM PDT 24	7023612260 ps
T315	/workspace/coverage/default/0.chip_plic_all_irqs_20.281396657			Jul 23 07:33:34 PM PDT 24	Jul 23 07:45:58 PM PDT 24	4674235820 ps
T912	/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.301566149			Jul 23 07:53:07 PM PDT 24	Jul 23 08:12:30 PM PDT 24	5662704834 ps
T913	/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2263714133			Jul 23 07:40:39 PM PDT 24	Jul 23 07:47:08 PM PDT 24	3084792300 ps
T69	/workspace/coverage/default/0.chip_tap_straps_testunlock0.1858459685			Jul 23 07:34:45 PM PDT 24	Jul 23 07:48:25 PM PDT 24	7980408410 ps
T914	/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.898186829			Jul 23 07:59:23 PM PDT 24	Jul 23 08:11:10 PM PDT 24	5909589912 ps
T915	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3582683587			Jul 23 07:54:44 PM PDT 24	Jul 23 07:59:12 PM PDT 24	2872067052 ps
T916	/workspace/coverage/default/2.chip_sw_edn_sw_mode.3940089961			Jul 23 07:57:45 PM PDT 24	Jul 23 08:36:41 PM PDT 24	8815575644 ps
T229	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3502379749			Jul 23 07:49:54 PM PDT 24	Jul 23 08:12:08 PM PDT 24	7086275144 ps
T917	/workspace/coverage/default/1.chip_sw_hmac_multistream.2314107615			Jul 23 07:49:10 PM PDT 24	Jul 23 08:16:53 PM PDT 24	7423955050 ps
T41	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1900151932			Jul 23 07:41:59 PM PDT 24	Jul 23 08:42:52 PM PDT 24	15228191966 ps
T918	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1090400039			Jul 23 07:34:24 PM PDT 24	Jul 23 07:45:19 PM PDT 24	4716059400 ps
T919	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.17245846			Jul 23 07:58:16 PM PDT 24	Jul 23 08:15:34 PM PDT 24	8157489070 ps
T16	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2457004335			Jul 23 07:41:48 PM PDT 24	Jul 23 07:50:21 PM PDT 24	4120959352 ps
T674	/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.44776799			Jul 23 08:13:35 PM PDT 24	Jul 23 08:21:24 PM PDT 24	3527082592 ps
T330	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.4124673071			Jul 23 07:32:36 PM PDT 24	Jul 23 07:45:42 PM PDT 24	4388290344 ps
T920	/workspace/coverage/default/0.chip_sw_example_concurrency.178620989			Jul 23 07:33:40 PM PDT 24	Jul 23 07:36:34 PM PDT 24	2510804828 ps
T343	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4093183821			Jul 23 08:01:23 PM PDT 24	Jul 23 08:16:19 PM PDT 24	5078648483 ps
T710	/workspace/coverage/default/42.chip_sw_all_escalation_resets.313879635			Jul 23 08:09:14 PM PDT 24	Jul 23 08:18:52 PM PDT 24	6210060520 ps
T921	/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1644640659			Jul 23 07:57:06 PM PDT 24	Jul 23 08:52:56 PM PDT 24	11649010334 ps
T367	/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.527772537			Jul 23 08:05:29 PM PDT 24	Jul 23 08:12:10 PM PDT 24	5269754415 ps
T922	/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1245041753			Jul 23 07:33:10 PM PDT 24	Jul 23 07:41:14 PM PDT 24	4462959336 ps
T923	/workspace/coverage/default/1.chip_sw_hmac_enc_idle.669426751			Jul 23 07:47:50 PM PDT 24	Jul 23 07:52:39 PM PDT 24	3350506394 ps
T733	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.417427512			Jul 23 07:36:56 PM PDT 24	Jul 23 07:45:12 PM PDT 24	3954268748 ps
T456	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.3148991284			Jul 23 07:43:56 PM PDT 24	Jul 23 08:02:11 PM PDT 24	5957346040 ps
T223	/workspace/coverage/default/3.chip_tap_straps_prod.2999385969			Jul 23 08:01:24 PM PDT 24	Jul 23 08:04:10 PM PDT 24	2756965667 ps
T119	/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3310206738			Jul 23 07:57:00 PM PDT 24	Jul 23 08:10:46 PM PDT 24	5959106318 ps
T924	/workspace/coverage/default/2.chip_sw_example_flash.3142320809			Jul 23 07:53:15 PM PDT 24	Jul 23 07:58:33 PM PDT 24	3232073592 ps
T42	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.4031826948			Jul 23 07:45:38 PM PDT 24	Jul 23 08:54:20 PM PDT 24	14643224673 ps
T138	/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4261446763			Jul 23 08:01:12 PM PDT 24	Jul 23 08:11:55 PM PDT 24	5794542296 ps
T377	/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2935615122			Jul 23 07:45:18 PM PDT 24	Jul 23 07:49:10 PM PDT 24	3040558104 ps
T925	/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3416724573			Jul 23 08:05:13 PM PDT 24	Jul 23 08:32:04 PM PDT 24	8609768024 ps
T220	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3924633296			Jul 23 07:35:00 PM PDT 24	Jul 23 07:49:31 PM PDT 24	4696826540 ps
T926	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3217788115			Jul 23 07:35:03 PM PDT 24	Jul 23 07:45:48 PM PDT 24	7128434072 ps
T729	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1619803115			Jul 23 07:36:28 PM PDT 24	Jul 23 08:00:09 PM PDT 24	7746612074 ps
T361	/workspace/coverage/default/1.chip_sival_flash_info_access.805814842			Jul 23 07:41:39 PM PDT 24	Jul 23 07:47:12 PM PDT 24	2455373384 ps
T195	/workspace/coverage/default/24.chip_sw_all_escalation_resets.2162426056			Jul 23 08:09:14 PM PDT 24	Jul 23 08:19:51 PM PDT 24	5621214580 ps
T345	/workspace/coverage/default/2.chip_sw_hmac_enc.1945928960			Jul 23 07:57:11 PM PDT 24	Jul 23 08:00:38 PM PDT 24	3283776886 ps
T316	/workspace/coverage/default/0.chip_plic_all_irqs_0.1621711714			Jul 23 07:34:25 PM PDT 24	Jul 23 07:54:43 PM PDT 24	6090602800 ps
T790	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1503826960			Jul 23 08:14:35 PM PDT 24	Jul 23 08:21:56 PM PDT 24	3784912924 ps
T927	/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2494703044			Jul 23 08:04:00 PM PDT 24	Jul 23 08:25:50 PM PDT 24	4886785972 ps
T350	/workspace/coverage/default/71.chip_sw_all_escalation_resets.2612575375			Jul 23 08:13:21 PM PDT 24	Jul 23 08:24:13 PM PDT 24	4714026248 ps
T231	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3838048113			Jul 23 07:47:33 PM PDT 24	Jul 23 08:20:14 PM PDT 24	9802220700 ps
T461	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2969189046			Jul 23 07:37:05 PM PDT 24	Jul 23 07:41:50 PM PDT 24	3560866907 ps
T928	/workspace/coverage/default/2.chip_sw_aes_enc.1774320509			Jul 23 07:56:34 PM PDT 24	Jul 23 08:02:16 PM PDT 24	2724535244 ps
T929	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1560084990			Jul 23 07:33:50 PM PDT 24	Jul 23 07:44:33 PM PDT 24	4625950810 ps
T930	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2044281488			Jul 23 07:37:18 PM PDT 24	Jul 23 07:49:28 PM PDT 24	10211353330 ps
T382	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.492981405			Jul 23 08:02:14 PM PDT 24	Jul 23 08:09:31 PM PDT 24	3753906136 ps
T931	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.472000864			Jul 23 07:51:22 PM PDT 24	Jul 23 07:56:09 PM PDT 24	3539983613 ps
T225	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.2287390896			Jul 23 07:36:51 PM PDT 24	Jul 23 07:45:55 PM PDT 24	7073144696 ps
T188	/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3318500752			Jul 23 08:10:22 PM PDT 24	Jul 23 08:17:43 PM PDT 24	3915230350 ps
T714	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2364050845			Jul 23 08:09:07 PM PDT 24	Jul 23 08:17:36 PM PDT 24	3491371760 ps
T412	/workspace/coverage/default/1.chip_sw_kmac_app_rom.1825142178			Jul 23 07:48:18 PM PDT 24	Jul 23 07:51:53 PM PDT 24	2472808510 ps
T120	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.2609282083			Jul 23 07:49:20 PM PDT 24	Jul 23 08:23:58 PM PDT 24	7874377950 ps
T932	/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.1370212393			Jul 23 07:47:26 PM PDT 24	Jul 23 08:12:51 PM PDT 24	8569479432 ps
T197	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2633678901			Jul 23 07:34:27 PM PDT 24	Jul 23 07:44:28 PM PDT 24	4738746166 ps
T186	/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3679094808			Jul 23 08:10:16 PM PDT 24	Jul 23 08:18:57 PM PDT 24	3659991180 ps
T103	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.550734151			Jul 23 07:36:16 PM PDT 24	Jul 23 07:42:33 PM PDT 24	3708207248 ps
T200	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2540757015			Jul 23 08:04:18 PM PDT 24	Jul 23 09:21:19 PM PDT 24	44450098878 ps
T442	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3832372899			Jul 23 07:35:00 PM PDT 24	Jul 23 07:55:15 PM PDT 24	12363054933 ps
T443	/workspace/coverage/default/0.chip_sw_flash_crash_alert.56338707			Jul 23 07:34:57 PM PDT 24	Jul 23 07:45:11 PM PDT 24	5094860988 ps
T333	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1892978755			Jul 23 07:32:47 PM PDT 24	Jul 23 07:43:19 PM PDT 24	4354111854 ps
T24	/workspace/coverage/default/0.chip_sw_usbdev_stream.2130352988			Jul 23 07:35:03 PM PDT 24	Jul 23 08:55:31 PM PDT 24	18909499308 ps
T203	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3268306747			Jul 23 07:33:01 PM PDT 24	Jul 23 07:35:18 PM PDT 24	2433599980 ps
T444	/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3269928041			Jul 23 08:07:42 PM PDT 24	Jul 23 09:13:54 PM PDT 24	17549843330 ps
T338	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2355356144			Jul 23 07:45:31 PM PDT 24	Jul 23 08:26:10 PM PDT 24	20927115172 ps
T445	/workspace/coverage/default/0.chip_sw_hmac_oneshot.718370916			Jul 23 07:34:07 PM PDT 24	Jul 23 07:39:06 PM PDT 24	2642665600 ps
T933	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3672447354			Jul 23 07:34:50 PM PDT 24	Jul 23 07:44:12 PM PDT 24	4318410886 ps
T823	/workspace/coverage/default/44.chip_sw_all_escalation_resets.3211391256			Jul 23 08:09:47 PM PDT 24	Jul 23 08:24:32 PM PDT 24	6073045704 ps
T405	/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1782092068			Jul 23 07:58:57 PM PDT 24	Jul 23 08:20:28 PM PDT 24	11417392760 ps
T934	/workspace/coverage/default/2.rom_e2e_asm_init_dev.341832790			Jul 23 08:04:13 PM PDT 24	Jul 23 09:04:07 PM PDT 24	15310551628 ps
T230	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.623149367			Jul 23 07:57:25 PM PDT 24	Jul 23 08:33:31 PM PDT 24	11298144240 ps
T104	/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2769793818			Jul 23 07:59:21 PM PDT 24	Jul 23 08:06:33 PM PDT 24	4136193720 ps
T715	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.4073341937			Jul 23 08:06:39 PM PDT 24	Jul 23 08:15:48 PM PDT 24	3638380616 ps
T716	/workspace/coverage/default/67.chip_sw_all_escalation_resets.95778672			Jul 23 08:12:11 PM PDT 24	Jul 23 08:23:57 PM PDT 24	5640860712 ps
T717	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.267595034			Jul 23 08:00:25 PM PDT 24	Jul 23 08:04:20 PM PDT 24	3451377718 ps
T248	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1577469961			Jul 23 07:56:58 PM PDT 24	Jul 23 08:05:29 PM PDT 24	3466147000 ps
T718	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2441916135			Jul 23 07:46:48 PM PDT 24	Jul 23 09:01:17 PM PDT 24	15208327050 ps
T346	/workspace/coverage/default/0.chip_sival_flash_info_access.2390886861			Jul 23 07:32:11 PM PDT 24	Jul 23 07:37:35 PM PDT 24	2701869990 ps
T352	/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.730058135			Jul 23 07:52:43 PM PDT 24	Jul 23 07:56:12 PM PDT 24	2577366698 ps
T383	/workspace/coverage/default/14.chip_sw_all_escalation_resets.4068038530			Jul 23 08:08:56 PM PDT 24	Jul 23 08:20:53 PM PDT 24	4672644130 ps
T114	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3765164790			Jul 23 08:01:31 PM PDT 24	Jul 23 08:29:17 PM PDT 24	10850329193 ps
T450	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.548090260			Jul 23 07:54:03 PM PDT 24	Jul 23 07:58:22 PM PDT 24	3029632682 ps
T935	/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.924500866			Jul 23 08:05:41 PM PDT 24	Jul 23 08:16:42 PM PDT 24	3983319672 ps
T936	/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1009198708			Jul 23 07:44:53 PM PDT 24	Jul 23 07:50:17 PM PDT 24	3485456596 ps
T110	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2780488419			Jul 23 07:37:01 PM PDT 24	Jul 23 08:53:00 PM PDT 24	24424861958 ps
T201	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3463973381			Jul 23 07:36:33 PM PDT 24	Jul 23 08:19:51 PM PDT 24	21061281703 ps
T344	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.4220830559			Jul 23 07:31:54 PM PDT 24	Jul 23 07:42:31 PM PDT 24	3717352357 ps
T542	/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2143389206			Jul 23 07:47:24 PM PDT 24	Jul 23 08:00:02 PM PDT 24	4782459810 ps
T183	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3699412813			Jul 23 07:33:13 PM PDT 24	Jul 23 07:43:18 PM PDT 24	5129305000 ps
T937	/workspace/coverage/default/2.chip_sw_hmac_multistream.1307598006			Jul 23 08:00:30 PM PDT 24	Jul 23 08:22:15 PM PDT 24	8258258656 ps
T140	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2905845447			Jul 23 07:54:19 PM PDT 24	Jul 23 08:03:51 PM PDT 24	9252990943 ps
T711	/workspace/coverage/default/97.chip_sw_all_escalation_resets.3316206641			Jul 23 08:15:14 PM PDT 24	Jul 23 08:25:08 PM PDT 24	4694111816 ps
T77	/workspace/coverage/default/10.chip_sw_all_escalation_resets.4254066629			Jul 23 08:05:31 PM PDT 24	Jul 23 08:17:04 PM PDT 24	6197473224 ps
T75	/workspace/coverage/default/1.rom_raw_unlock.734641577			Jul 23 07:52:17 PM PDT 24	Jul 23 07:57:07 PM PDT 24	5839029629 ps
T85	/workspace/coverage/default/72.chip_sw_all_escalation_resets.1508223475			Jul 23 08:12:05 PM PDT 24	Jul 23 08:23:29 PM PDT 24	4715765652 ps
T86	/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2015080841			Jul 23 08:01:27 PM PDT 24	Jul 23 08:05:16 PM PDT 24	3504832508 ps
T87	/workspace/coverage/default/0.chip_sw_power_sleep_load.2506270536			Jul 23 07:40:23 PM PDT 24	Jul 23 07:46:48 PM PDT 24	4241091964 ps
T88	/workspace/coverage/default/1.chip_tap_straps_prod.382443355			Jul 23 07:50:13 PM PDT 24	Jul 23 08:06:58 PM PDT 24	8142745394 ps
T89	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1705022171			Jul 23 07:47:12 PM PDT 24	Jul 23 07:53:16 PM PDT 24	3918941454 ps
T90	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3276122938			Jul 23 07:55:01 PM PDT 24	Jul 23 08:17:53 PM PDT 24	6294985480 ps
T91	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3530247615			Jul 23 07:45:40 PM PDT 24	Jul 23 07:53:03 PM PDT 24	5790303590 ps
T92	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1131558301			Jul 23 07:33:42 PM PDT 24	Jul 23 07:58:07 PM PDT 24	9579916970 ps
T189	/workspace/coverage/default/11.chip_sw_all_escalation_resets.1019555272			Jul 23 08:04:14 PM PDT 24	Jul 23 08:17:20 PM PDT 24	5910183288 ps
T208	/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2835106730			Jul 23 07:56:56 PM PDT 24	Jul 23 08:12:06 PM PDT 24	8007709719 ps
T48	/workspace/coverage/default/2.chip_sw_alert_test.1401150857			Jul 23 07:57:14 PM PDT 24	Jul 23 08:01:47 PM PDT 24	3102744396 ps
T938	/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.691933537			Jul 23 07:48:44 PM PDT 24	Jul 23 08:12:38 PM PDT 24	10462453500 ps
T463	/workspace/coverage/default/2.chip_sw_edn_boot_mode.2795953854			Jul 23 07:57:53 PM PDT 24	Jul 23 08:07:22 PM PDT 24	3273782050 ps
T939	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3241460701			Jul 23 07:44:03 PM PDT 24	Jul 23 08:42:23 PM PDT 24	11248846960 ps
T181	/workspace/coverage/default/0.chip_plic_all_irqs_10.1165941031			Jul 23 07:34:23 PM PDT 24	Jul 23 07:44:35 PM PDT 24	3529617928 ps
T353	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1980958227			Jul 23 07:53:25 PM PDT 24	Jul 23 08:34:09 PM PDT 24	13770892445 ps