Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	157143	1			T72	59		T73	7		T74	12
values[2]	4783	1			T72	8		T258	7		T465	1
values[3]	2248	1			T72	1		T832	2		T553	57
values[4]	1672	1			T832	2		T553	30		T472	54
values[5]	1205	1			T832	2		T553	17		T472	49
values[6]	945	1			T832	2		T553	6		T472	46
values[7]	896	1			T832	2		T553	12		T472	51
values[8]	861	1			T832	2		T553	8		T472	30
values[9]	765	1			T832	2		T553	23		T472	10
values[10]	565	1			T832	2		T553	16		T472	5
values[11]	477	1			T832	2		T553	13		T472	9
values[12]	400	1			T832	2		T553	2		T472	3
values[13]	454	1			T832	2		T553	11		T472	3
values[14]	383	1			T832	2		T553	21		T824	1
values[15]	296	1			T832	2		T553	14		T824	1
values[16]	238	1			T832	2		T553	15		T824	1
values[17]	193	1			T832	2		T553	9		T824	1
values[18]	153	1			T832	2		T553	13		T824	1
values[19]	167	1			T832	2		T553	14		T824	1
values[20]	149	1			T832	2		T553	14		T824	1
values[21]	101	1			T832	2		T553	6		T824	1
values[22]	102	1			T832	2		T553	4		T824	1
values[23]	104	1			T832	2		T553	4		T824	1
values[24]	101	1			T832	2		T553	2		T824	1
values[25]	73	1			T832	2		T553	4		T824	1
values[26]	79	1			T832	2		T553	10		T824	1
values[27]	78	1			T832	2		T553	21		T824	1
values[28]	84	1			T832	2		T553	31		T824	1
values[29]	119	1			T832	2		T553	52		T824	1
values[30]	134	1			T832	2		T553	52		T824	1
values[31]	145	1			T832	2		T553	53		T824	1
values[32]	122	1			T832	2		T553	33		T824	1
values[33]	88	1			T832	2		T553	17		T824	1
values[34]	86	1			T832	3		T553	12		T824	1
values[35]	69	1			T832	2		T553	9		T824	1
values[36]	73	1			T832	2		T553	13		T824	1
values[37]	72	1			T832	2		T553	1		T824	1
values[38]	90	1			T832	2		T824	1		T856	1
values[39]	73	1			T832	2		T824	1		T856	1
values[40]	52	1			T832	2		T824	1		T856	1
values[41]	53	1			T832	2		T824	1		T856	1
values[42]	54	1			T832	2		T824	1		T856	1
values[43]	42	1			T832	3		T824	1		T856	1
values[44]	46	1			T832	2		T824	1		T856	1
values[45]	50	1			T832	2		T824	1		T856	1
values[46]	49	1			T832	2		T824	1		T856	1
values[47]	49	1			T832	2		T824	1		T856	1
values[48]	57	1			T832	2		T824	1		T856	1
values[49]	55	1			T832	2		T824	1		T856	1
values[50]	35	1			T832	2		T824	1		T856	1
values[51]	47	1			T832	2		T824	1		T856	1
values[52]	38	1			T832	2		T824	1		T856	1
values[53]	39	1			T832	2		T824	1		T856	1
values[54]	42	1			T832	2		T824	1		T856	1
values[55]	37	1			T832	2		T824	1		T856	1
values[56]	32	1			T832	2		T824	1		T856	1
values[57]	32	1			T832	2		T824	1		T856	1
values[58]	34	1			T832	2		T824	1		T856	1
values[59]	35	1			T832	2		T824	1		T856	1
values[60]	33	1			T832	2		T824	1		T856	1
values[61]	37	1			T832	2		T824	1		T856	1
values[62]	41	1			T832	2		T824	1		T856	1
values[63]	30	1			T832	2		T824	1		T856	1
values[64]	36	1			T832	2		T824	1		T856	1
values[65]	48	1			T832	2		T824	2		T856	1
values[66]	31	1			T832	2		T824	1		T856	1
values[67]	36	1			T832	2		T824	1		T856	1
values[68]	34	1			T832	2		T824	1		T856	1
values[69]	37	1			T832	2		T824	1		T856	1
values[70]	34	1			T832	2		T824	1		T856	1
values[71]	37	1			T832	2		T824	1		T856	2
values[72]	44	1			T832	2		T824	1		T856	1
values[73]	48	1			T832	3		T824	1		T856	1
values[74]	37	1			T832	6		T824	1		T856	1
values[75]	45	1			T832	5		T824	1		T856	1
values[76]	46	1			T832	9		T824	1		T856	1
values[77]	43	1			T832	3		T824	1		T856	1
values[78]	48	1			T832	8		T824	1		T856	1
values[79]	40	1			T832	3		T824	1		T856	1
values[80]	39	1			T832	6		T824	1		T856	1
values[81]	46	1			T832	2		T824	1		T856	1
values[82]	52	1			T832	2		T824	1		T856	1
values[83]	50	1			T832	3		T824	1		T856	1
values[84]	48	1			T832	2		T824	1		T856	1
values[85]	49	1			T832	3		T824	1		T856	1
values[86]	49	1			T832	2		T824	1		T856	1
values[87]	64	1			T832	5		T824	1		T856	1
values[88]	60	1			T832	4		T824	1		T856	1
values[89]	41	1			T832	6		T824	1		T856	1
values[90]	42	1			T832	4		T824	1		T856	1
values[91]	53	1			T832	5		T824	1		T856	1
values[92]	67	1			T832	6		T824	1		T856	2
values[93]	51	1			T832	5		T824	1		T856	1
values[94]	59	1			T832	8		T824	1		T856	1
values[95]	59	1			T832	4		T824	1		T856	1
values[96]	59	1			T832	9		T824	1		T856	1
values[97]	58	1			T832	4		T824	1		T856	1
values[98]	50	1			T832	4		T824	1		T856	1
values[99]	52	1			T832	6		T824	1		T856	1
values[100]	56	1			T832	8		T824	1		T856	1
values[101]	72	1			T832	4		T824	1		T856	1
values[102]	60	1			T832	3		T824	1		T856	1
values[103]	53	1			T832	4		T824	1		T856	1
values[104]	61	1			T832	4		T824	1		T856	2
values[105]	57	1			T832	3		T824	1		T856	1
values[106]	62	1			T832	4		T824	1		T856	2
values[107]	87	1			T832	11		T824	1		T856	2
values[108]	73	1			T832	4		T824	1		T856	1
values[109]	65	1			T832	2		T824	2		T856	4
values[110]	63	1			T832	2		T824	2		T856	4
values[111]	73	1			T832	6		T824	2		T856	2
values[112]	79	1			T832	3		T824	3		T856	1
values[113]	51	1			T832	3		T824	3		T856	2
values[114]	64	1			T832	4		T824	2		T856	3
values[115]	65	1			T832	2		T824	1		T856	1
values[116]	73	1			T832	2		T824	1		T856	1
values[117]	50	1			T832	2		T824	1		T856	4
values[118]	63	1			T832	3		T824	1		T856	4
values[119]	68	1			T832	3		T824	2		T856	7
values[120]	67	1			T832	4		T824	2		T856	1
values[121]	56	1			T832	7		T824	1		T856	1
values[122]	93	1			T832	6		T824	2		T856	2
values[123]	99	1			T832	6		T824	2		T856	2
values[124]	143	1			T832	8		T824	5		T856	1
values[125]	260	1			T832	4		T824	1		T856	2
values[126]	544	1			T832	28		T824	14		T856	22
values[127]	1833	1			T832	193		T824	122		T856	154
values[128]	3135	1			T832	423		T824	172		T856	239