Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	477	1			T74	1		T633	1		T552	1
all_values[1]	520	1			T74	3		T553	2		T472	1
all_values[2]	473	1			T74	1		T633	1		T553	8
all_values[3]	475	1			T74	2		T441	1		T633	2
all_values[4]	449	1			T74	4		T832	1		T633	2
all_values[5]	482	1			T74	4		T633	1		T552	1
all_values[6]	508	1			T74	3		T441	1		T633	3
all_values[7]	472	1			T74	1		T633	3		T553	5
all_values[8]	471	1			T74	3		T633	2		T552	1
all_values[9]	471	1			T74	4		T441	1		T633	5
all_values[10]	468	1			T74	4		T693	1		T832	1
all_values[11]	432	1			T74	3		T553	12		T472	1
all_values[12]	460	1			T74	4		T441	1		T633	2
all_values[13]	474	1			T74	3		T633	1		T553	2
all_values[14]	459	1			T74	3		T832	1		T633	3
all_values[15]	459	1			T74	1		T441	1		T633	2
all_values[16]	471	1			T74	1		T633	4		T553	5
all_values[17]	489	1			T74	3		T633	2		T553	5
all_values[18]	476	1			T74	3		T633	1		T553	4
all_values[19]	470	1			T74	2		T441	1		T633	1
all_values[20]	460	1			T74	3		T441	1		T693	1
all_values[21]	466	1			T74	4		T832	2		T633	3
all_values[22]	462	1			T74	1		T552	2		T553	7
all_values[23]	463	1			T74	3		T441	1		T553	6
all_values[24]	478	1			T74	3		T633	3		T552	2
all_values[25]	480	1			T441	1		T553	5		T472	1
all_values[26]	461	1			T74	4		T441	1		T552	1
all_values[27]	512	1			T74	2		T633	1		T552	2
all_values[28]	491	1			T74	3		T633	2		T553	3
all_values[29]	457	1			T74	4		T553	3		T478	2
all_values[30]	468	1			T74	1		T441	1		T552	1
all_values[31]	459	1			T441	1		T633	2		T553	4
all_values[32]	478	1			T74	3		T633	1		T552	1
all_values[33]	486	1			T447	1		T552	1		T553	6
all_values[34]	454	1			T74	4		T447	1		T633	2
all_values[35]	483	1			T74	1		T633	1		T553	4
all_values[36]	479	1			T74	2		T633	3		T553	7
all_values[37]	444	1			T74	3		T447	1		T633	3
all_values[38]	496	1			T74	3		T441	1		T447	1
all_values[39]	496	1			T74	2		T447	1		T633	1
all_values[40]	460	1			T74	2		T441	2		T633	3
all_values[41]	477	1			T74	3		T552	1		T553	6
all_values[42]	459	1			T74	1		T447	1		T633	1
all_values[43]	461	1			T74	1		T633	1		T553	9
all_values[44]	491	1			T74	3		T441	1		T633	4
all_values[45]	495	1			T633	1		T553	5		T472	2
all_values[46]	470	1			T74	3		T441	1		T447	1
all_values[47]	467	1			T74	2		T441	1		T633	4
all_values[48]	497	1			T74	2		T633	1		T553	2
all_values[49]	470	1			T74	3		T441	1		T633	1