Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3628	1			T74	13		T214	2		T545	1
all_values[1]	3651	1			T74	19		T214	3		T633	7
all_values[2]	3620	1			T74	18		T214	4		T545	2
all_values[3]	3501	1			T74	12		T214	3		T633	10
all_values[4]	3587	1			T74	25		T214	2		T633	9
all_values[5]	3616	1			T74	18		T214	3		T550	1
all_values[6]	3550	1			T74	17		T214	2		T550	2
all_values[7]	3597	1			T74	12		T214	3		T550	1
all_values[8]	3593	1			T74	22		T214	4		T545	1
all_values[9]	3592	1			T74	13		T214	3		T550	1
all_values[10]	3545	1			T74	20		T214	5		T550	1
all_values[11]	3512	1			T74	18		T214	2		T545	1
all_values[12]	3633	1			T74	25		T214	3		T545	1
all_values[13]	3690	1			T74	16		T214	5		T545	4
all_values[14]	3557	1			T74	18		T214	2		T545	2
all_values[15]	3619	1			T74	11		T214	3		T545	1
all_values[16]	3561	1			T74	14		T214	4		T545	2
all_values[17]	3591	1			T74	22		T214	2		T633	12
all_values[18]	3545	1			T74	24		T214	2		T633	7
all_values[19]	3580	1			T74	19		T214	2		T545	1
all_values[20]	3579	1			T74	14		T214	4		T550	1
all_values[21]	3469	1			T74	24		T214	1		T550	1
all_values[22]	3607	1			T74	17		T214	4		T633	5
all_values[23]	3597	1			T74	22		T214	3		T633	5
all_values[24]	3571	1			T74	23		T214	2		T550	1
all_values[25]	3588	1			T74	22		T214	3		T545	2
all_values[26]	3437	1			T74	14		T214	3		T633	10
all_values[27]	3651	1			T74	19		T214	2		T545	2
all_values[28]	3528	1			T74	20		T214	1		T545	2
all_values[29]	3638	1			T74	19		T214	2		T545	1
all_values[30]	3628	1			T74	21		T214	5		T545	1
all_values[31]	3518	1			T74	28		T214	1		T550	1
all_values[32]	3584	1			T74	19		T214	3		T545	1
all_values[33]	3600	1			T74	16		T214	5		T550	1
all_values[34]	3690	1			T74	16		T214	5		T550	1
all_values[35]	3616	1			T74	16		T214	4		T633	7
all_values[36]	3426	1			T74	20		T214	1		T545	2
all_values[37]	3508	1			T74	19		T214	3		T545	2
all_values[38]	3556	1			T74	22		T214	4		T545	4
all_values[39]	3628	1			T74	20		T214	1		T545	3
all_values[40]	3671	1			T74	21		T214	1		T633	8
all_values[41]	3688	1			T74	22		T214	2		T550	1
all_values[42]	3642	1			T74	19		T214	1		T545	1
all_values[43]	3541	1			T74	18		T214	4		T550	2
all_values[44]	3545	1			T74	21		T214	2		T550	1
all_values[45]	3610	1			T74	10		T214	1		T550	1
all_values[46]	3583	1			T74	8		T214	2		T545	1
all_values[47]	3529	1			T74	16		T214	2		T550	1
all_values[48]	3558	1			T74	21		T214	2		T545	2
all_values[49]	3528	1			T74	15		T214	3		T545	1
all_values[50]	3503	1			T74	19		T214	4		T550	1
all_values[51]	3610	1			T74	20		T214	2		T633	6
all_values[52]	3484	1			T74	18		T214	1		T545	2
all_values[53]	3583	1			T74	15		T214	3		T545	2
all_values[54]	3586	1			T74	26		T214	4		T545	2
all_values[55]	3564	1			T74	22		T214	4		T545	2
all_values[56]	3605	1			T74	20		T214	4		T550	1
all_values[57]	3525	1			T74	20		T214	3		T550	1
all_values[58]	3644	1			T74	20		T214	1		T550	1
all_values[59]	3566	1			T74	17		T214	2		T633	6
all_values[60]	3565	1			T74	13		T214	3		T545	1
all_values[61]	3675	1			T74	17		T214	3		T545	1
all_values[62]	3436	1			T74	22		T214	1		T545	1
all_values[63]	3455	1			T74	18		T214	5		T545	1