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LINE 532
SUB-EXPRESSION ((reg2hw.dio_pad_sleep_mode[5].q == 2'h2) ? 1'b0 : dio_oe[5])
--------------------1-------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[5].q == 2'h2)
--------------------1-------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 532
EXPRESSION
Number Term
1 (reg2hw.dio_pad_sleep_mode[6].q == 2'b0) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[6].q == 2'b1) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[6].q == 2'h2) ? 1'b0 : dio_oe[6])))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T51,T53,T9 |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[6].q == 2'b0)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T51,T53,T9 |
LINE 532
SUB-EXPRESSION ((reg2hw.dio_pad_sleep_mode[6].q == 2'b1) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[6].q == 2'h2) ? 1'b0 : dio_oe[6]))
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T8,T51,T53 |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[6].q == 2'b1)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T8,T51,T53 |
LINE 532
SUB-EXPRESSION ((reg2hw.dio_pad_sleep_mode[6].q == 2'h2) ? 1'b0 : dio_oe[6])
--------------------1-------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[6].q == 2'h2)
--------------------1-------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 532
EXPRESSION
Number Term
1 (reg2hw.dio_pad_sleep_mode[7].q == 2'b0) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[7].q == 2'b1) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[7].q == 2'h2) ? 1'b0 : dio_oe[7])))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T51,T53,T9 |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[7].q == 2'b0)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T51,T53,T9 |
LINE 532
SUB-EXPRESSION ((reg2hw.dio_pad_sleep_mode[7].q == 2'b1) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[7].q == 2'h2) ? 1'b0 : dio_oe[7]))
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T51,T53,T54 |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[7].q == 2'b1)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T51,T53,T54 |
LINE 532
SUB-EXPRESSION ((reg2hw.dio_pad_sleep_mode[7].q == 2'h2) ? 1'b0 : dio_oe[7])
--------------------1-------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[7].q == 2'h2)
--------------------1-------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 532
EXPRESSION
Number Term
1 (reg2hw.dio_pad_sleep_mode[8].q == 2'b0) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[8].q == 2'b1) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[8].q == 2'h2) ? 1'b0 : dio_oe[8])))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T51,T53,T54 |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[8].q == 2'b0)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T51,T53,T54 |
LINE 532
SUB-EXPRESSION ((reg2hw.dio_pad_sleep_mode[8].q == 2'b1) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[8].q == 2'h2) ? 1'b0 : dio_oe[8]))
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T51,T53,T54 |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[8].q == 2'b1)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T51,T53,T54 |
LINE 532
SUB-EXPRESSION ((reg2hw.dio_pad_sleep_mode[8].q == 2'h2) ? 1'b0 : dio_oe[8])
--------------------1-------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[8].q == 2'h2)
--------------------1-------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 532
EXPRESSION
Number Term
1 (reg2hw.dio_pad_sleep_mode[9].q == 2'b0) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[9].q == 2'b1) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[9].q == 2'h2) ? 1'b0 : dio_oe[9])))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T8,T51,T53 |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[9].q == 2'b0)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T8,T51,T53 |
LINE 532
SUB-EXPRESSION ((reg2hw.dio_pad_sleep_mode[9].q == 2'b1) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[9].q == 2'h2) ? 1'b0 : dio_oe[9]))
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T51,T53,T54 |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[9].q == 2'b1)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T51,T53,T54 |
LINE 532
SUB-EXPRESSION ((reg2hw.dio_pad_sleep_mode[9].q == 2'h2) ? 1'b0 : dio_oe[9])
--------------------1-------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[9].q == 2'h2)
--------------------1-------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 532
EXPRESSION
Number Term
1 (reg2hw.dio_pad_sleep_mode[10].q == 2'b0) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[10].q == 2'b1) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[10].q == 2'h2) ? 1'b0 : dio_oe[10])))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T8,T9,T10 |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[10].q == 2'b0)
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T8,T9,T10 |
LINE 532
SUB-EXPRESSION ((reg2hw.dio_pad_sleep_mode[10].q == 2'b1) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[10].q == 2'h2) ? 1'b0 : dio_oe[10]))
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[10].q == 2'b1)
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 532
SUB-EXPRESSION ((reg2hw.dio_pad_sleep_mode[10].q == 2'h2) ? 1'b0 : dio_oe[10])
--------------------1--------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[10].q == 2'h2)
--------------------1--------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 532
EXPRESSION
Number Term
1 (reg2hw.dio_pad_sleep_mode[11].q == 2'b0) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[11].q == 2'b1) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[11].q == 2'h2) ? 1'b0 : dio_oe[11])))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[11].q == 2'b0)
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 532
SUB-EXPRESSION ((reg2hw.dio_pad_sleep_mode[11].q == 2'b1) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[11].q == 2'h2) ? 1'b0 : dio_oe[11]))
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T8,T9,T10 |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[11].q == 2'b1)
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T8,T9,T10 |
LINE 532
SUB-EXPRESSION ((reg2hw.dio_pad_sleep_mode[11].q == 2'h2) ? 1'b0 : dio_oe[11])
--------------------1--------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[11].q == 2'h2)
--------------------1--------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 532
EXPRESSION
Number Term
1 (reg2hw.dio_pad_sleep_mode[12].q == 2'b0) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[12].q == 2'b1) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[12].q == 2'h2) ? 1'b0 : dio_oe[12])))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[12].q == 2'b0)
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 532
SUB-EXPRESSION ((reg2hw.dio_pad_sleep_mode[12].q == 2'b1) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[12].q == 2'h2) ? 1'b0 : dio_oe[12]))
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[12].q == 2'b1)
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 532
SUB-EXPRESSION ((reg2hw.dio_pad_sleep_mode[12].q == 2'h2) ? 1'b0 : dio_oe[12])
--------------------1--------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[12].q == 2'h2)
--------------------1--------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 532
EXPRESSION
Number Term
1 (reg2hw.dio_pad_sleep_mode[13].q == 2'b0) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[13].q == 2'b1) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[13].q == 2'h2) ? 1'b0 : dio_oe[13])))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[13].q == 2'b0)
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 532
SUB-EXPRESSION ((reg2hw.dio_pad_sleep_mode[13].q == 2'b1) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[13].q == 2'h2) ? 1'b0 : dio_oe[13]))
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[13].q == 2'b1)
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 532
SUB-EXPRESSION ((reg2hw.dio_pad_sleep_mode[13].q == 2'h2) ? 1'b0 : dio_oe[13])
--------------------1--------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[13].q == 2'h2)
--------------------1--------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 532
EXPRESSION
Number Term
1 (reg2hw.dio_pad_sleep_mode[14].q == 2'b0) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[14].q == 2'b1) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[14].q == 2'h2) ? 1'b0 : dio_oe[14])))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T10 |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[14].q == 2'b0)
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T10 |
LINE 532
SUB-EXPRESSION ((reg2hw.dio_pad_sleep_mode[14].q == 2'b1) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[14].q == 2'h2) ? 1'b0 : dio_oe[14]))
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T8,T9 |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[14].q == 2'b1)
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T8,T9 |
LINE 532
SUB-EXPRESSION ((reg2hw.dio_pad_sleep_mode[14].q == 2'h2) ? 1'b0 : dio_oe[14])
--------------------1--------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[14].q == 2'h2)
--------------------1--------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 532
EXPRESSION
Number Term
1 (reg2hw.dio_pad_sleep_mode[15].q == 2'b0) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[15].q == 2'b1) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[15].q == 2'h2) ? 1'b0 : dio_oe[15])))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[15].q == 2'b0)
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 532
SUB-EXPRESSION ((reg2hw.dio_pad_sleep_mode[15].q == 2'b1) ? 1'b1 : ((reg2hw.dio_pad_sleep_mode[15].q == 2'h2) ? 1'b0 : dio_oe[15]))
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[15].q == 2'b1)
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 532
SUB-EXPRESSION ((reg2hw.dio_pad_sleep_mode[15].q == 2'h2) ? 1'b0 : dio_oe[15])
--------------------1--------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 532
SUB-EXPRESSION (reg2hw.dio_pad_sleep_mode[15].q == 2'h2)
--------------------1--------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
LINE 537
EXPRESSION (reg2hw.dio_pad_sleep_en[0].q & sleep_trig)
--------------1------------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T9,T10 |
1 | 1 | Covered | T8,T9,T10 |
LINE 537
EXPRESSION (reg2hw.dio_pad_sleep_en[1].q & sleep_trig)
--------------1------------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T9,T10 |
1 | 1 | Covered | T8,T9,T10 |
LINE 537
EXPRESSION (reg2hw.dio_pad_sleep_en[2].q & sleep_trig)
--------------1------------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T9,T10 |
1 | 1 | Covered | T8,T9,T10 |
LINE 537
EXPRESSION (reg2hw.dio_pad_sleep_en[3].q & sleep_trig)
--------------1------------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T9,T10 |
1 | 1 | Covered | T8,T9,T10 |
LINE 537
EXPRESSION (reg2hw.dio_pad_sleep_en[4].q & sleep_trig)
--------------1------------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T9,T10 |
1 | 1 | Covered | T8,T9,T10 |
LINE 537
EXPRESSION (reg2hw.dio_pad_sleep_en[5].q & sleep_trig)
--------------1------------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T9,T10 |
1 | 1 | Covered | T8,T9,T10 |
LINE 537
EXPRESSION (reg2hw.dio_pad_sleep_en[6].q & sleep_trig)
--------------1------------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T51,T53 |
1 | 1 | Covered | T8,T51,T53 |
LINE 537
EXPRESSION (reg2hw.dio_pad_sleep_en[7].q & sleep_trig)
--------------1------------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T51,T53 |
1 | 1 | Covered | T8,T51,T53 |
LINE 537
EXPRESSION (reg2hw.dio_pad_sleep_en[8].q & sleep_trig)
--------------1------------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T51,T53 |
1 | 1 | Covered | T8,T51,T53 |
LINE 537
EXPRESSION (reg2hw.dio_pad_sleep_en[9].q & sleep_trig)
--------------1------------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T51,T53 |
1 | 1 | Covered | T8,T51,T53 |
LINE 537
EXPRESSION (reg2hw.dio_pad_sleep_en[10].q & sleep_trig)
--------------1-------------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T9,T10 |
1 | 1 | Covered | T8,T9,T10 |
LINE 537
EXPRESSION (reg2hw.dio_pad_sleep_en[11].q & sleep_trig)
--------------1-------------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T9,T10 |
1 | 1 | Covered | T8,T9,T10 |
LINE 537
EXPRESSION (reg2hw.dio_pad_sleep_en[12].q & sleep_trig)
--------------1-------------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T9,T10 |
1 | 1 | Covered | T8,T9,T10 |
LINE 537
EXPRESSION (reg2hw.dio_pad_sleep_en[13].q & sleep_trig)
--------------1-------------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T9,T10 |
1 | 1 | Covered | T8,T9,T10 |
LINE 537
EXPRESSION (reg2hw.dio_pad_sleep_en[14].q & sleep_trig)
--------------1-------------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T9,T10 |
1 | 1 | Covered | T8,T9,T10 |
LINE 537
EXPRESSION (reg2hw.dio_pad_sleep_en[15].q & sleep_trig)
--------------1-------------- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T8,T9,T10 |
1 | 1 | Covered | T8,T9,T10 |
LINE 591
EXPRESSION (reg2hw.wkup_detector[0].miodio.q ? dio_wkup_mux[reg2hw.wkup_detector_padsel[0]] : mio_wkup_mux[reg2hw.wkup_detector_padsel[0]])
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T51,T53,T54 |
LINE 591
EXPRESSION (reg2hw.wkup_detector[1].miodio.q ? dio_wkup_mux[reg2hw.wkup_detector_padsel[1]] : mio_wkup_mux[reg2hw.wkup_detector_padsel[1]])
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 591
EXPRESSION (reg2hw.wkup_detector[2].miodio.q ? dio_wkup_mux[reg2hw.wkup_detector_padsel[2]] : mio_wkup_mux[reg2hw.wkup_detector_padsel[2]])
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 591
EXPRESSION (reg2hw.wkup_detector[3].miodio.q ? dio_wkup_mux[reg2hw.wkup_detector_padsel[3]] : mio_wkup_mux[reg2hw.wkup_detector_padsel[3]])
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T55 |
LINE 591
EXPRESSION (reg2hw.wkup_detector[4].miodio.q ? dio_wkup_mux[reg2hw.wkup_detector_padsel[4]] : mio_wkup_mux[reg2hw.wkup_detector_padsel[4]])
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 591
EXPRESSION (reg2hw.wkup_detector[5].miodio.q ? dio_wkup_mux[reg2hw.wkup_detector_padsel[5]] : mio_wkup_mux[reg2hw.wkup_detector_padsel[5]])
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 591
EXPRESSION (reg2hw.wkup_detector[6].miodio.q ? dio_wkup_mux[reg2hw.wkup_detector_padsel[6]] : mio_wkup_mux[reg2hw.wkup_detector_padsel[6]])
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |
LINE 591
EXPRESSION (reg2hw.wkup_detector[7].miodio.q ? dio_wkup_mux[reg2hw.wkup_detector_padsel[7]] : mio_wkup_mux[reg2hw.wkup_detector_padsel[7]])
----------------1---------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Not Covered | |