Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	450	1			T430	3		T655	5		T837	2
all_values[1]	447	1			T430	8		T663	1		T525	1
all_values[2]	453	1			T430	6		T878	1		T655	6
all_values[3]	432	1			T446	1		T430	3		T655	7
all_values[4]	441	1			T430	4		T655	1		T837	1
all_values[5]	438	1			T430	1		T663	1		T655	3
all_values[6]	433	1			T430	3		T527	1		T655	7
all_values[7]	450	1			T79	1		T430	3		T404	1
all_values[8]	432	1			T430	4		T663	1		T432	1
all_values[9]	430	1			T655	2		T660	5		T626	1
all_values[10]	464	1			T430	3		T655	4		T837	1
all_values[11]	454	1			T430	3		T525	2		T655	8
all_values[12]	469	1			T79	1		T430	4		T655	4
all_values[13]	395	1			T430	3		T432	1		T655	1
all_values[14]	415	1			T430	1		T655	5		T660	9
all_values[15]	440	1			T430	4		T415	1		T655	4
all_values[16]	412	1			T404	1		T655	2		T837	1
all_values[17]	431	1			T430	3		T432	1		T655	3
all_values[18]	470	1			T430	3		T404	1		T415	1
all_values[19]	448	1			T430	2		T655	4		T837	1
all_values[20]	455	1			T430	2		T663	2		T655	3
all_values[21]	426	1			T79	1		T430	2		T432	1
all_values[22]	428	1			T430	3		T527	1		T878	1
all_values[23]	404	1			T430	2		T655	1		T837	2
all_values[24]	405	1			T446	1		T430	4		T404	1
all_values[25]	428	1			T446	1		T430	4		T663	1
all_values[26]	393	1			T79	1		T430	4		T655	3
all_values[27]	456	1			T430	6		T415	2		T525	1
all_values[28]	458	1			T430	5		T663	1		T415	1
all_values[29]	436	1			T430	2		T432	1		T655	4
all_values[30]	469	1			T79	1		T430	1		T415	1
all_values[31]	427	1			T430	5		T527	1		T655	6
all_values[32]	443	1			T430	2		T878	1		T655	5
all_values[33]	433	1			T79	1		T430	3		T415	1
all_values[34]	467	1			T430	3		T527	1		T655	7
all_values[35]	477	1			T430	6		T663	1		T415	1
all_values[36]	442	1			T430	2		T663	2		T404	1
all_values[37]	477	1			T525	1		T432	1		T655	3
all_values[38]	431	1			T79	1		T430	3		T404	1
all_values[39]	415	1			T430	4		T525	1		T878	1
all_values[40]	449	1			T430	2		T527	1		T878	1
all_values[41]	465	1			T430	2		T655	4		T837	1
all_values[42]	453	1			T446	1		T430	3		T404	2
all_values[43]	457	1			T430	3		T660	3		T626	3
all_values[44]	457	1			T446	1		T430	3		T415	1
all_values[45]	483	1			T446	2		T430	3		T655	2
all_values[46]	401	1			T79	1		T446	1		T430	3
all_values[47]	382	1			T79	1		T430	2		T415	1
all_values[48]	450	1			T430	3		T655	4		T837	3
all_values[49]	416	1			T79	1		T430	2		T663	1