Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.01	95.45	93.70	95.43		94.40	97.53	99.55

Total tests in report: 2937

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
38.14	38.14	44.47	44.47	43.04	43.04	24.61	24.61			57.45	57.45	59.09	59.09	0.18	0.18	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1121556817
48.61	10.47	50.63	6.16	59.47	16.43	27.81	3.20			68.19	10.74	84.27	25.17	1.28	1.10	/workspace/coverage/cover_reg_top/13.chip_csr_rw.1584985954
54.66	6.05	63.12	12.49	67.44	7.96	32.58	4.77			79.29	11.10	84.27	0.00	1.28	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.249592091
59.73	5.07	63.12	0.00	68.05	0.62	32.58	0.00			79.45	0.15	84.27	0.00	30.92	29.64	/workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.1212422026
64.50	4.77	74.68	11.56	70.14	2.09	37.57	4.99			79.82	0.37	84.27	0.00	40.51	9.59	/workspace/coverage/cover_reg_top/99.xbar_stress_all.293399025
67.65	3.15	80.00	5.32	74.12	3.98	41.23	3.66			81.58	1.76	88.46	4.20	40.51	0.00	/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2292029652
70.46	2.81	80.00	0.00	74.12	0.00	41.23	0.00			81.58	0.00	88.46	0.00	57.35	16.84	/workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.3030930585
73.21	2.75	80.01	0.01	74.16	0.03	57.31	16.08			81.61	0.02	88.81	0.35	57.36	0.01	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.861736336
75.29	2.08	80.01	0.00	74.16	0.00	57.31	0.00			81.61	0.00	88.81	0.00	69.85	12.49	/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.4128405893
77.30	2.01	82.45	2.44	77.05	2.89	61.53	4.22			83.79	2.18	89.16	0.35	69.85	0.00	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3485695556
79.01	1.71	84.73	2.29	79.32	2.27	64.55	3.03			86.46	2.67	89.16	0.00	69.85	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1289784231
80.69	1.68	87.84	3.11	82.52	3.19	64.89	0.33			89.54	3.08	89.51	0.35	69.85	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.5601527
82.23	1.54	88.13	0.29	82.66	0.14	73.16	8.28			89.72	0.18	89.86	0.35	69.85	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2296012906
83.42	1.18	88.13	0.00	82.66	0.00	73.16	0.00			89.72	0.00	89.86	0.00	76.96	7.11	/workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.2906438561
84.51	1.09	88.86	0.73	82.81	0.15	74.83	1.66			89.90	0.18	93.71	3.85	76.96	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1972946965
85.47	0.96	89.64	0.79	83.64	0.83	76.68	1.85			90.48	0.58	93.71	0.00	78.65	1.69	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3281506668
86.38	0.92	89.64	0.00	83.64	0.00	76.68	0.00			90.48	0.00	93.71	0.00	84.15	5.50	/workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.2187636385
87.20	0.82	89.64	0.00	83.64	0.00	81.58	4.90			90.48	0.00	93.71	0.00	84.15	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.484183119
87.98	0.78	91.10	1.45	84.46	0.82	83.39	1.81			91.09	0.61	93.71	0.00	84.15	0.00	/workspace/coverage/default/1.chip_sw_power_virus.2121545292
88.64	0.66	91.77	0.67	84.94	0.48	83.78	0.39			91.59	0.49	95.63	1.92	84.15	0.00	/workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.2669509583
89.25	0.61	91.77	0.01	85.27	0.32	84.49	0.71			91.62	0.03	95.63	0.00	86.75	2.60	/workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.3188074365
89.84	0.59	91.77	0.00	85.27	0.00	84.49	0.00			91.62	0.00	95.63	0.00	90.26	3.51	/workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.3618666842
90.34	0.50	92.39	0.62	85.89	0.63	85.57	1.08			92.14	0.52	95.63	0.00	90.40	0.14	/workspace/coverage/default/2.chip_jtag_csr_rw.2499107090
90.80	0.46	92.40	0.01	88.25	2.36	85.57	0.00			92.14	0.00	95.63	0.00	90.79	0.39	/workspace/coverage/cover_reg_top/15.chip_tl_errors.2602843346
91.26	0.46	92.41	0.01	88.26	0.01	88.30	2.74			92.14	0.00	95.63	0.00	90.79	0.00	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2961812532
91.64	0.38	92.41	0.00	88.33	0.07	88.30	0.00			92.14	0.00	95.63	0.00	93.02	2.23	/workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.857777163
91.99	0.35	92.94	0.52	88.79	0.46	88.95	0.65			92.60	0.46	95.63	0.00	93.02	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.3142672810
92.30	0.31	93.51	0.57	89.25	0.46	89.44	0.48			92.95	0.35	95.63	0.00	93.02	0.00	/workspace/coverage/default/1.chip_sw_gpio.913740958
92.57	0.27	93.51	0.00	89.26	0.01	89.44	0.00			92.95	0.00	95.63	0.00	94.64	1.62	/workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.660136069
92.82	0.25	93.83	0.32	90.15	0.89	89.45	0.02			93.10	0.15	95.63	0.00	94.76	0.12	/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.2145773357
93.04	0.23	93.83	0.00	90.15	0.00	90.81	1.35			93.10	0.00	95.63	0.00	94.76	0.00	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.802966150
93.27	0.22	93.83	0.00	90.20	0.05	90.81	0.00			93.10	0.00	95.63	0.00	96.04	1.28	/workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.2472047120
93.44	0.17	93.95	0.12	90.32	0.12	91.47	0.66			93.18	0.08	95.63	0.00	96.09	0.05	/workspace/coverage/default/29.chip_sw_all_escalation_resets.1211874005
93.59	0.16	93.95	0.00	90.40	0.08	91.47	0.00			93.18	0.00	95.63	0.00	96.93	0.85	/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.3559631883
93.72	0.12	93.95	0.00	90.74	0.34	91.49	0.02			93.57	0.39	95.63	0.00	96.93	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3701746520
93.84	0.12	93.95	0.00	90.74	0.00	92.22	0.73			93.57	0.00	95.63	0.00	96.93	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1287391234
93.95	0.11	93.95	0.00	90.74	0.00	92.22	0.00			93.57	0.00	95.63	0.00	97.59	0.66	/workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.1604168573
94.05	0.10	93.96	0.01	90.80	0.05	92.56	0.34			93.58	0.02	95.80	0.17	97.59	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.882804805
94.15	0.10	94.03	0.08	90.82	0.02	92.70	0.14			93.59	0.01	96.15	0.35	97.59	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.133588573
94.24	0.09	94.03	0.00	91.35	0.54	92.70	0.00			93.59	0.00	96.15	0.00	97.61	0.02	/workspace/coverage/cover_reg_top/16.chip_tl_errors.1779895434
94.33	0.09	94.05	0.02	91.46	0.11	92.71	0.01			93.65	0.06	96.50	0.35	97.61	0.00	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3157581783
94.42	0.09	94.05	0.00	91.47	0.01	93.26	0.54			93.65	0.00	96.50	0.00	97.61	0.00	/workspace/coverage/default/13.chip_sw_all_escalation_resets.1657316080
94.50	0.08	94.17	0.12	91.56	0.09	93.40	0.14			93.74	0.10	96.50	0.00	97.61	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2718956164
94.57	0.07	94.22	0.05	91.62	0.06	93.41	0.01			93.74	0.00	96.50	0.00	97.93	0.32	/workspace/coverage/default/0.chip_sw_alert_test.4165115158
94.64	0.07	94.34	0.11	91.72	0.10	93.49	0.08			93.85	0.11	96.50	0.00	97.93	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3073077650
94.70	0.06	94.34	0.00	91.72	0.00	93.84	0.35			93.85	0.00	96.50	0.00	97.93	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.417293489
94.75	0.05	94.39	0.06	91.75	0.03	93.85	0.01			93.88	0.03	96.68	0.17	97.94	0.01	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1200991385
94.80	0.05	94.39	0.00	91.89	0.14	93.85	0.00			94.04	0.16	96.68	0.00	97.94	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1887016022
94.85	0.05	94.39	0.00	91.96	0.06	93.85	0.00			94.06	0.02	96.68	0.00	98.16	0.21	/workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.3284231414
94.90	0.05	94.42	0.03	92.00	0.04	93.85	0.01			94.09	0.02	96.85	0.17	98.17	0.01	/workspace/coverage/default/57.chip_sw_all_escalation_resets.774690176
94.94	0.04	94.42	0.00	92.00	0.00	94.11	0.25			94.09	0.00	96.85	0.00	98.17	0.00	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1966703176
94.98	0.04	94.42	0.00	92.23	0.24	94.11	0.00			94.09	0.00	96.85	0.00	98.17	0.00	/workspace/coverage/cover_reg_top/13.chip_tl_errors.4023549801
95.01	0.04	94.49	0.07	92.23	0.00	94.24	0.14			94.09	0.01	96.85	0.00	98.17	0.00	/workspace/coverage/default/4.chip_tap_straps_rma.124706426
95.05	0.04	94.50	0.01	92.24	0.01	94.25	0.01			94.10	0.01	97.03	0.17	98.18	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.756274494
95.09	0.04	94.50	0.01	92.26	0.01	94.26	0.01			94.11	0.01	97.20	0.17	98.19	0.01	/workspace/coverage/default/99.chip_sw_all_escalation_resets.1483859076
95.12	0.04	94.51	0.01	92.27	0.01	94.26	0.00			94.12	0.01	97.38	0.17	98.20	0.01	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1984468443
95.15	0.03	94.51	0.00	92.36	0.10	94.26	0.00			94.13	0.02	97.38	0.00	98.27	0.07	/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.2203684057
95.18	0.03	94.51	0.00	92.36	0.00	94.26	0.01			94.13	0.00	97.55	0.17	98.27	0.00	/workspace/coverage/default/2.chip_sw_data_integrity_escalation.3500067940
95.21	0.03	94.51	0.00	92.54	0.18	94.26	0.00			94.13	0.00	97.55	0.00	98.27	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.1563324193
95.24	0.03	94.58	0.07	92.57	0.03	94.28	0.02			94.18	0.05	97.55	0.00	98.27	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.741044351
95.27	0.03	94.58	0.00	92.65	0.08	94.28	0.00			94.26	0.07	97.55	0.00	98.27	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1478762598
95.29	0.03	94.58	0.00	92.65	0.00	94.43	0.15			94.26	0.00	97.55	0.00	98.27	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.894496633
95.32	0.02	94.64	0.07	92.70	0.05	94.43	0.00			94.29	0.03	97.55	0.00	98.27	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1580839805
95.34	0.02	94.64	0.00	92.72	0.01	94.43	0.00			94.29	0.00	97.55	0.00	98.40	0.13	/workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.708356785
95.36	0.02	94.65	0.01	92.74	0.02	94.52	0.09			94.29	0.00	97.55	0.00	98.41	0.01	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1249189519
95.38	0.02	94.72	0.07	92.79	0.05	94.52	0.00			94.30	0.02	97.55	0.00	98.41	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3815479669
95.41	0.02	94.78	0.07	92.84	0.05	94.52	0.00			94.32	0.02	97.55	0.00	98.41	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.378138802
95.42	0.02	94.78	0.00	92.84	0.00	94.64	0.12			94.32	0.00	97.55	0.00	98.41	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2822578151
95.44	0.02	94.79	0.01	92.86	0.02	94.72	0.08			94.32	0.00	97.55	0.00	98.41	0.00	/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3285843
95.46	0.02	94.79	0.00	92.96	0.10	94.72	0.00			94.32	0.00	97.55	0.00	98.41	0.00	/workspace/coverage/cover_reg_top/27.chip_tl_errors.782048686
95.47	0.01	94.79	0.00	92.96	0.00	94.78	0.05			94.32	0.00	97.55	0.00	98.45	0.04	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1483882560
95.49	0.01	94.79	0.01	92.99	0.03	94.83	0.05			94.32	0.00	97.55	0.00	98.45	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1347158614
95.50	0.01	94.79	0.00	92.99	0.00	94.91	0.08			94.32	0.00	97.55	0.00	98.45	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.459507027
95.52	0.01	94.80	0.01	93.00	0.01	94.95	0.04			94.34	0.02	97.55	0.00	98.45	0.00	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.413903411
95.53	0.01	94.80	0.00	93.06	0.06	94.95	0.00			94.35	0.02	97.55	0.00	98.45	0.00	/workspace/coverage/cover_reg_top/81.xbar_stress_all.3101182237
95.54	0.01	94.80	0.00	93.06	0.00	94.95	0.00			94.35	0.00	97.55	0.00	98.52	0.07	/workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.682432605
95.55	0.01	94.80	0.00	93.06	0.01	95.02	0.07			94.35	0.00	97.55	0.00	98.52	0.00	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1172443692
95.56	0.01	94.80	0.00	93.13	0.06	95.02	0.00			94.35	0.00	97.55	0.00	98.52	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.3370210229
95.57	0.01	94.80	0.00	93.19	0.06	95.02	0.00			94.35	0.00	97.55	0.00	98.52	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.2669129539
95.58	0.01	94.80	0.00	93.23	0.05	95.02	0.00			94.35	0.00	97.55	0.00	98.53	0.01	/workspace/coverage/cover_reg_top/14.chip_tl_errors.1405353417
95.59	0.01	94.80	0.00	93.24	0.01	95.02	0.00			94.35	0.00	97.55	0.00	98.58	0.05	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3120249048
95.60	0.01	94.82	0.02	93.25	0.01	95.03	0.01			94.37	0.02	97.55	0.00	98.58	0.00	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.770280814
95.61	0.01	94.82	0.00	93.25	0.00	95.08	0.05			94.37	0.00	97.55	0.00	98.58	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.784682145
95.62	0.01	94.84	0.02	93.25	0.01	95.08	0.01			94.39	0.02	97.55	0.00	98.58	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1113876680
95.62	0.01	94.85	0.01	93.29	0.03	95.08	0.01			94.39	0.01	97.55	0.00	98.58	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2872413987
95.63	0.01	94.85	0.00	93.29	0.00	95.13	0.05			94.39	0.00	97.55	0.00	98.58	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.65676252
95.64	0.01	94.85	0.00	93.29	0.00	95.18	0.05			94.39	0.00	97.55	0.00	98.58	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1186247268
95.65	0.01	94.85	0.00	93.29	0.01	95.18	0.00			94.39	0.00	97.55	0.00	98.61	0.04	/workspace/coverage/cover_reg_top/80.xbar_stress_all.1932151518
95.65	0.01	94.85	0.00	93.29	0.00	95.22	0.04			94.39	0.00	97.55	0.00	98.61	0.00	/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3647272429
95.66	0.01	94.85	0.00	93.32	0.03	95.22	0.00			94.39	0.00	97.55	0.00	98.63	0.01	/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.1111853643
95.67	0.01	94.85	0.00	93.33	0.01	95.22	0.00			94.39	0.00	97.55	0.00	98.66	0.04	/workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.3994103619
95.67	0.01	94.85	0.00	93.36	0.04	95.22	0.00			94.39	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.1709843459
95.68	0.01	94.85	0.00	93.36	0.00	95.22	0.00			94.39	0.00	97.55	0.00	98.70	0.04	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.2436098975
95.68	0.01	94.85	0.00	93.39	0.03	95.22	0.00			94.39	0.00	97.55	0.00	98.70	0.00	/workspace/coverage/cover_reg_top/9.chip_tl_errors.434706563
95.69	0.01	94.85	0.00	93.40	0.01	95.22	0.00			94.39	0.00	97.55	0.00	98.72	0.02	/workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.1502314627
95.69	0.01	94.85	0.00	93.43	0.03	95.22	0.00			94.39	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3152239141
95.70	0.01	94.85	0.00	93.43	0.00	95.25	0.03			94.39	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1895774033
95.70	0.01	94.85	0.00	93.43	0.00	95.27	0.03			94.39	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4220707749
95.71	0.01	94.85	0.00	93.45	0.02	95.28	0.01			94.39	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1931188010
95.71	0.01	94.85	0.00	93.47	0.02	95.28	0.00			94.39	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/default/2.chip_sw_gpio.2142111502
95.71	0.01	94.85	0.00	93.47	0.00	95.28	0.00			94.39	0.00	97.55	0.00	98.74	0.02	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.2738577470
95.72	0.01	94.85	0.00	93.47	0.00	95.28	0.00			94.39	0.00	97.55	0.00	98.77	0.02	/workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.1580083045
95.72	0.01	94.85	0.00	93.49	0.02	95.28	0.00			94.39	0.00	97.55	0.00	98.77	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.4240893016
95.73	0.01	94.85	0.00	93.49	0.00	95.30	0.02			94.39	0.00	97.55	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.454045070
95.73	0.01	94.85	0.00	93.49	0.00	95.31	0.01			94.39	0.00	97.55	0.00	98.78	0.01	/workspace/coverage/default/68.chip_sw_all_escalation_resets.2819236150
95.73	0.01	94.85	0.01	93.50	0.01	95.32	0.01			94.39	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1611276040
95.74	0.01	94.85	0.00	93.50	0.00	95.33	0.02			94.39	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2812416578
95.74	0.01	94.85	0.00	93.52	0.02	95.33	0.00			94.39	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.776184038
95.74	0.01	94.85	0.01	93.52	0.00	95.35	0.01			94.39	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.2499547368
95.74	0.01	94.87	0.01	93.52	0.00	95.35	0.01			94.39	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.844639553
95.75	0.01	94.87	0.00	93.52	0.01	95.35	0.00			94.39	0.00	97.55	0.00	98.79	0.01	/workspace/coverage/cover_reg_top/21.chip_tl_errors.612110371
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95.75	0.01	94.87	0.00	93.55	0.01	95.36	0.00			94.39	0.00	97.55	0.00	98.79	0.00	/workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.2779443974
95.75	0.01	94.87	0.00	93.56	0.01	95.36	0.00			94.39	0.00	97.55	0.00	98.79	0.00	/workspace/coverage/cover_reg_top/26.xbar_access_same_device.3253788470
95.76	0.01	94.87	0.00	93.58	0.01	95.36	0.00			94.39	0.00	97.55	0.00	98.79	0.00	/workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.282190552
95.76	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	98.80	0.01	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.1540298000
95.76	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	98.81	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2118753591
95.76	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	98.83	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.123125300
95.76	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	98.84	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1615249026
95.77	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	98.85	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.1341178986
95.77	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	98.86	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2244859738
95.77	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	98.87	0.01	/workspace/coverage/default/10.chip_sw_all_escalation_resets.2133457990
95.77	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	98.88	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1455791626
95.77	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	98.90	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.350570401
95.78	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	98.91	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3134283558
95.78	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	98.92	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.1010336441
95.78	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	98.93	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3303973346
95.78	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	98.94	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2575275138
95.78	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	98.95	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.3591016445
95.79	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	98.97	0.01	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.4105619164
95.79	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	98.98	0.01	/workspace/coverage/default/18.chip_sw_all_escalation_resets.4115068756
95.79	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	98.99	0.01	/workspace/coverage/default/2.chip_sw_all_escalation_resets.1184074380
95.79	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.00	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.512494466
95.79	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.01	0.01	/workspace/coverage/default/20.chip_sw_all_escalation_resets.3224366065
95.80	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.02	0.01	/workspace/coverage/default/22.chip_sw_all_escalation_resets.3705111992
95.80	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.04	0.01	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.185519794
95.80	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.05	0.01	/workspace/coverage/default/24.chip_sw_all_escalation_resets.1823953167
95.80	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.06	0.01	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1151701828
95.80	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.07	0.01	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.81219010
95.80	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.08	0.01	/workspace/coverage/default/28.chip_sw_all_escalation_resets.1261432839
95.81	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.10	0.01	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.578421974
95.81	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.11	0.01	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.3963341193
95.81	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.12	0.01	/workspace/coverage/default/30.chip_sw_all_escalation_resets.2825464720
95.81	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.13	0.01	/workspace/coverage/default/31.chip_sw_all_escalation_resets.4139311586
95.81	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.14	0.01	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.985995564
95.82	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.15	0.01	/workspace/coverage/default/34.chip_sw_all_escalation_resets.1358496089
95.82	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.17	0.01	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.571632529
95.82	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.18	0.01	/workspace/coverage/default/35.chip_sw_all_escalation_resets.1113902292
95.82	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.19	0.01	/workspace/coverage/default/36.chip_sw_all_escalation_resets.3105652593
95.82	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.20	0.01	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1267697730
95.83	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.21	0.01	/workspace/coverage/default/38.chip_sw_all_escalation_resets.199425081
95.83	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.22	0.01	/workspace/coverage/default/4.chip_sw_all_escalation_resets.1367677538
95.83	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.24	0.01	/workspace/coverage/default/42.chip_sw_all_escalation_resets.1365245972
95.83	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.25	0.01	/workspace/coverage/default/44.chip_sw_all_escalation_resets.2109403520
95.83	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.26	0.01	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.714288223
95.84	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.27	0.01	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.960344260
95.84	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.28	0.01	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.302313938
95.84	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.30	0.01	/workspace/coverage/default/51.chip_sw_all_escalation_resets.704960350
95.84	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.31	0.01	/workspace/coverage/default/53.chip_sw_all_escalation_resets.1169116061
95.84	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.32	0.01	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1936784776
95.85	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.33	0.01	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2007996158
95.85	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.34	0.01	/workspace/coverage/default/56.chip_sw_all_escalation_resets.237788539
95.85	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.35	0.01	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3253035439
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95.87	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.45	0.01	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1739453657
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95.88	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.54	0.01	/workspace/coverage/default/93.chip_sw_all_escalation_resets.2727958123
95.88	0.01	94.87	0.00	93.58	0.00	95.36	0.00			94.39	0.00	97.55	0.00	99.55	0.01	/workspace/coverage/default/97.chip_sw_all_escalation_resets.2031459171
95.88	0.01	94.87	0.00	93.59	0.01	95.36	0.00			94.39	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.768822178
95.89	0.01	94.87	0.00	93.60	0.01	95.36	0.00			94.39	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2470417850
95.89	0.01	94.87	0.00	93.61	0.01	95.36	0.00			94.39	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3496325969
95.89	0.01	94.87	0.00	93.62	0.01	95.36	0.00			94.39	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1269879463
95.89	0.01	94.87	0.00	93.62	0.00	95.36	0.01			94.39	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3298944484
95.89	0.01	94.87	0.00	93.62	0.00	95.36	0.00			94.40	0.01	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1306500999
95.89	0.01	94.87	0.00	93.63	0.01	95.36	0.00			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/1.xbar_access_same_device.3671922154
95.90	0.01	94.87	0.00	93.63	0.01	95.36	0.00			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/1.xbar_stress_all.1202283779
95.90	0.01	94.87	0.00	93.64	0.01	95.36	0.00			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.1491293485
95.90	0.01	94.87	0.00	93.65	0.01	95.36	0.00			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.3992906625
95.90	0.01	94.87	0.00	93.65	0.01	95.36	0.00			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.1085388467
95.90	0.01	94.87	0.00	93.66	0.01	95.36	0.00			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2120650996
95.90	0.01	94.87	0.00	93.67	0.01	95.36	0.00			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.1763848773
95.90	0.01	94.87	0.00	93.67	0.00	95.37	0.01			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.833321577
95.90	0.01	94.87	0.00	93.67	0.00	95.38	0.01			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2450441479
95.90	0.01	94.87	0.00	93.67	0.00	95.38	0.01			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1886661580
95.91	0.01	94.87	0.00	93.67	0.00	95.39	0.01			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_flash_init.2074547166
95.91	0.01	94.87	0.00	93.67	0.00	95.39	0.01			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1487913506
95.91	0.01	94.87	0.00	93.67	0.00	95.40	0.01			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1045960950
95.91	0.01	94.87	0.00	93.67	0.00	95.40	0.01			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.3062154859
95.91	0.01	94.87	0.00	93.67	0.00	95.41	0.01			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3170814555
95.91	0.01	94.87	0.00	93.67	0.01	95.41	0.00			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.3936105082
95.91	0.01	94.87	0.00	93.67	0.01	95.41	0.00			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.2763234382
95.91	0.01	94.87	0.00	93.68	0.01	95.41	0.00			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.3557296705
95.91	0.01	94.87	0.00	93.68	0.01	95.41	0.00			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.516160931
95.91	0.01	94.87	0.00	93.69	0.01	95.41	0.00			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.2123833178
95.91	0.01	94.87	0.00	93.69	0.01	95.41	0.00			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.3424474921
95.91	0.01	94.87	0.00	93.69	0.01	95.41	0.00			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_gpio.246094972
95.91	0.01	94.87	0.00	93.70	0.01	95.41	0.00			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3579292007
95.91	0.01	94.87	0.00	93.70	0.01	95.41	0.00			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.4134440473
95.91	0.01	94.87	0.00	93.70	0.00	95.41	0.01			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_tap_straps_testunlock0.3951770502
95.91	0.01	94.87	0.00	93.70	0.00	95.41	0.01			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.917775925
95.92	0.01	94.87	0.00	93.70	0.00	95.42	0.01			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.271182649
95.92	0.01	94.87	0.00	93.70	0.00	95.42	0.01			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.2688565989
95.92	0.01	94.87	0.00	93.70	0.00	95.42	0.01			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3833582456
95.92	0.01	94.87	0.00	93.70	0.00	95.42	0.01			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3903724965
95.92	0.01	94.87	0.00	93.70	0.00	95.42	0.01			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3630130495
95.92	0.01	94.87	0.00	93.70	0.00	95.43	0.01			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.726345456
95.92	0.01	94.87	0.00	93.70	0.00	95.43	0.01			94.40	0.00	97.55	0.00	99.55	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1692465809

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.691960435
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2473227155
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.3345483435
/workspace/coverage/cover_reg_top/0.chip_csr_rw.984865851
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.3506017348
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.153249860
/workspace/coverage/cover_reg_top/0.chip_tl_errors.2163905652
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2994188764
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.982734835
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.543775036
/workspace/coverage/cover_reg_top/0.xbar_error_random.2078191705
/workspace/coverage/cover_reg_top/0.xbar_random.3141542254
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.1900425108
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3350107444
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.763523545
/workspace/coverage/cover_reg_top/0.xbar_same_source.1086943390
/workspace/coverage/cover_reg_top/0.xbar_smoke.521953000
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.117400124
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1303819008
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3102169896
/workspace/coverage/cover_reg_top/0.xbar_stress_all.1063389698
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.4033217153
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3701287469
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.413491755
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.713640350
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2141907216
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3461723522
/workspace/coverage/cover_reg_top/1.chip_csr_rw.1015410179
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.1789847642
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.121290413
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.137337250
/workspace/coverage/cover_reg_top/1.chip_tl_errors.3833959134
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2532026159
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1075550308
/workspace/coverage/cover_reg_top/1.xbar_error_random.1826485884
/workspace/coverage/cover_reg_top/1.xbar_random.1469521411
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.708683307
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3325843790
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3340173424
/workspace/coverage/cover_reg_top/1.xbar_same_source.42915049
/workspace/coverage/cover_reg_top/1.xbar_smoke.3572920766
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.591860432
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.685874059
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2844281721
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1662742473
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.58303756
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2715075948
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.256304464
/workspace/coverage/cover_reg_top/10.chip_csr_rw.2136514168
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.583298665
/workspace/coverage/cover_reg_top/10.chip_tl_errors.3577348462
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.3725473820
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.224633449
/workspace/coverage/cover_reg_top/10.xbar_error_random.1579953921
/workspace/coverage/cover_reg_top/10.xbar_random.1349399195
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3247635611
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.604949814
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.4251679345
/workspace/coverage/cover_reg_top/10.xbar_same_source.3625566140
/workspace/coverage/cover_reg_top/10.xbar_smoke.1593558794
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.378197213
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3465329616
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.1260398450
/workspace/coverage/cover_reg_top/10.xbar_stress_all.3262901293
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.1093041461
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3301121440
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3473730808
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.3406477758
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.2493947252
/workspace/coverage/cover_reg_top/11.chip_csr_rw.1320455944
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.893702212
/workspace/coverage/cover_reg_top/11.chip_tl_errors.1308455514
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.4277670611
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.305646259
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.4132364575
/workspace/coverage/cover_reg_top/11.xbar_error_random.1349260272
/workspace/coverage/cover_reg_top/11.xbar_random.940267969
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3837309203
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.981518689
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.112676113
/workspace/coverage/cover_reg_top/11.xbar_same_source.1686196842
/workspace/coverage/cover_reg_top/11.xbar_smoke.214597674
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2461370263
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3738155082
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3370460992
/workspace/coverage/cover_reg_top/11.xbar_stress_all.3063842361
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2574925189
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2152695183
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1987329993
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2846122770
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.1890334421
/workspace/coverage/cover_reg_top/12.chip_csr_rw.316470719
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.4142547840
/workspace/coverage/cover_reg_top/12.chip_tl_errors.1280177622
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.2491053611
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2137079105
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.579985549
/workspace/coverage/cover_reg_top/12.xbar_error_random.649732640
/workspace/coverage/cover_reg_top/12.xbar_random.2898819310
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.929353880
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.124586870
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.4219690681
/workspace/coverage/cover_reg_top/12.xbar_same_source.237683805
/workspace/coverage/cover_reg_top/12.xbar_smoke.3142872642
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2229067173
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2778312197
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3061479345
/workspace/coverage/cover_reg_top/12.xbar_stress_all.2010612585
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.2372683622
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3003803524
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.336817860
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.592476293
/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.4144684853
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.2354462742
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1424957018
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.1319751116
/workspace/coverage/cover_reg_top/13.xbar_error_random.210770359
/workspace/coverage/cover_reg_top/13.xbar_random.1029470113
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.190051248
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.1484931139
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.4111924401
/workspace/coverage/cover_reg_top/13.xbar_same_source.1351366707
/workspace/coverage/cover_reg_top/13.xbar_smoke.3691653758
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2811875124
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.671500031
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.153888573
/workspace/coverage/cover_reg_top/13.xbar_stress_all.3772116519
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.4197096589
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1227164646
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.2674159484
/workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.3555617064
/workspace/coverage/cover_reg_top/14.chip_csr_rw.2683090808
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.3488775428
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.1586162610
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3110311673
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.2901345758
/workspace/coverage/cover_reg_top/14.xbar_error_random.4013662299
/workspace/coverage/cover_reg_top/14.xbar_random.2492779730
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.2959906942
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.1239130159
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.2226631111
/workspace/coverage/cover_reg_top/14.xbar_same_source.3591059054
/workspace/coverage/cover_reg_top/14.xbar_smoke.1842532227
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.4279413405
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.518945870
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/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.691916315
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/workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.2570198276
/workspace/coverage/default/2.chip_sw_spi_device_tpm.3076542541
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3469467249
/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2519670278
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.139690178
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2084029918
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/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1983914944
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1958766141
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3714797748
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.321907087
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1292088623
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1837853610
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/workspace/coverage/default/2.chip_sw_uart_tx_rx.100886453
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/workspace/coverage/default/21.chip_sw_all_escalation_resets.3631206156
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/workspace/coverage/default/26.chip_sw_all_escalation_resets.2225528050
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/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.66769627
/workspace/coverage/default/3.chip_sw_uart_tx_rx.3854082938
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/workspace/coverage/default/3.chip_tap_straps_testunlock0.4153339456
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.45563260
/workspace/coverage/default/32.chip_sw_all_escalation_resets.3175224059
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1518517416
/workspace/coverage/default/33.chip_sw_all_escalation_resets.2277069319
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1760101928
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1444357605
/workspace/coverage/default/37.chip_sw_all_escalation_resets.1150382897
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.515523497
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3998691204
/workspace/coverage/default/39.chip_sw_all_escalation_resets.1221137610
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3528135645
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1847136433
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3543322559
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.4199320772
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3370346825
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3951592474
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.254481978
/workspace/coverage/default/4.chip_sw_uart_tx_rx.2615839775
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.287663978
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.907582918
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.601623306
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.978153431
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1543589759
/workspace/coverage/default/4.chip_tap_straps_dev.496910849
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/workspace/coverage/default/4.chip_tap_straps_testunlock0.755164935
/workspace/coverage/default/40.chip_sw_all_escalation_resets.765178586
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.4264888329
/workspace/coverage/default/41.chip_sw_all_escalation_resets.2475102581
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1215354224
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1140892219
/workspace/coverage/default/43.chip_sw_all_escalation_resets.1034595740
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1756633113
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1355288509
/workspace/coverage/default/45.chip_sw_all_escalation_resets.1554450905
/workspace/coverage/default/46.chip_sw_all_escalation_resets.3235843817
/workspace/coverage/default/47.chip_sw_all_escalation_resets.103665512
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1872558892
/workspace/coverage/default/48.chip_sw_all_escalation_resets.2356573030
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.433753910
/workspace/coverage/default/49.chip_sw_all_escalation_resets.4228237997
/workspace/coverage/default/5.chip_sw_all_escalation_resets.90287463
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3011216668
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2091030455
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1918585074
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.663747725
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.634695754
/workspace/coverage/default/50.chip_sw_all_escalation_resets.3300927824
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2124833428
/workspace/coverage/default/52.chip_sw_all_escalation_resets.318137
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2697453125
/workspace/coverage/default/54.chip_sw_all_escalation_resets.4029714492
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2669794384
/workspace/coverage/default/55.chip_sw_all_escalation_resets.2108487161
/workspace/coverage/default/58.chip_sw_all_escalation_resets.3226059516
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1522259028
/workspace/coverage/default/59.chip_sw_all_escalation_resets.1316471273
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3879000365
/workspace/coverage/default/6.chip_sw_all_escalation_resets.878876263
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.860141985
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3179915402
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2285837377
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2220286689
/workspace/coverage/default/60.chip_sw_all_escalation_resets.45879402
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2945268872
/workspace/coverage/default/61.chip_sw_all_escalation_resets.1640617423
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.694852664
/workspace/coverage/default/62.chip_sw_all_escalation_resets.2265755383
/workspace/coverage/default/63.chip_sw_all_escalation_resets.3291803312
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1458890264
/workspace/coverage/default/64.chip_sw_all_escalation_resets.2454534696
/workspace/coverage/default/66.chip_sw_all_escalation_resets.2493161017
/workspace/coverage/default/67.chip_sw_all_escalation_resets.4116345064
/workspace/coverage/default/69.chip_sw_all_escalation_resets.355557894
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.166104792
/workspace/coverage/default/7.chip_sw_all_escalation_resets.754820028
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.4075467642
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.4120117050
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2400254843
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1933620005
/workspace/coverage/default/70.chip_sw_all_escalation_resets.2831254836
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1051913849
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2107454688
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1749649662
/workspace/coverage/default/72.chip_sw_all_escalation_resets.325701059
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3033006936
/workspace/coverage/default/73.chip_sw_all_escalation_resets.105071953
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3965728673
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2370952426
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2497511487
/workspace/coverage/default/75.chip_sw_all_escalation_resets.2591456505
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.248161496
/workspace/coverage/default/76.chip_sw_all_escalation_resets.1858454029
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2308240286
/workspace/coverage/default/77.chip_sw_all_escalation_resets.2622293870
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3413777053
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1957819846
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3254826995
/workspace/coverage/default/79.chip_sw_all_escalation_resets.2351635385
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.827605943
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2193480137
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1327453278
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.791086172
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.572127961
/workspace/coverage/default/81.chip_sw_all_escalation_resets.2023942208
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2383145178
/workspace/coverage/default/82.chip_sw_all_escalation_resets.9851308
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3396168806
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1633194432
/workspace/coverage/default/84.chip_sw_all_escalation_resets.649365129
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.4290874560
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3888264917
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1309420591
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1585840039
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1411184619
/workspace/coverage/default/87.chip_sw_all_escalation_resets.3556596011
/workspace/coverage/default/88.chip_sw_all_escalation_resets.314772729
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3600914862
/workspace/coverage/default/9.chip_sw_all_escalation_resets.617833300
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1368741770
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1431682011
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3435897808
/workspace/coverage/default/91.chip_sw_all_escalation_resets.3674568620
/workspace/coverage/default/92.chip_sw_all_escalation_resets.65539851
/workspace/coverage/default/94.chip_sw_all_escalation_resets.1568891083
/workspace/coverage/default/95.chip_sw_all_escalation_resets.1206089411
/workspace/coverage/default/96.chip_sw_all_escalation_resets.3222453662
/workspace/coverage/default/98.chip_sw_all_escalation_resets.4069155680
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.4115801926
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3705948219
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1150904826
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2082634224
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.242727893
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.65676072
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2480218275
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.791700569

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Total test records in report: 2937

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2400254843			Jul 25 08:29:56 PM PDT 24	Jul 25 08:50:51 PM PDT 24	8382192608 ps
T2	/workspace/coverage/default/4.chip_tap_straps_rma.124706426			Jul 25 08:27:12 PM PDT 24	Jul 25 08:30:24 PM PDT 24	3227668344 ps
T3	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2961812532			Jul 25 08:26:05 PM PDT 24	Jul 26 01:42:07 AM PDT 24	135858221328 ps
T4	/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2109300289			Jul 25 08:04:45 PM PDT 24	Jul 25 08:08:36 PM PDT 24	2795476587 ps
T5	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.601623306			Jul 25 08:27:08 PM PDT 24	Jul 25 08:36:46 PM PDT 24	3945885800 ps
T6	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1121556817			Jul 25 08:12:23 PM PDT 24	Jul 25 08:19:46 PM PDT 24	5728234000 ps
T92	/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.503118597			Jul 25 08:15:46 PM PDT 24	Jul 25 08:25:33 PM PDT 24	2937074446 ps
T7	/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3647272429			Jul 25 08:30:42 PM PDT 24	Jul 25 08:46:08 PM PDT 24	10797132472 ps
T8	/workspace/coverage/default/2.chip_jtag_mem_access.1588924135			Jul 25 08:15:46 PM PDT 24	Jul 25 08:43:38 PM PDT 24	13642895532 ps
T33	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.770280814			Jul 25 08:17:08 PM PDT 24	Jul 25 08:25:25 PM PDT 24	3282201972 ps
T119	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.293001142			Jul 25 08:02:23 PM PDT 24	Jul 25 08:07:34 PM PDT 24	3070659553 ps
T202	/workspace/coverage/default/0.chip_sw_hmac_multistream.835612580			Jul 25 08:01:10 PM PDT 24	Jul 25 08:26:16 PM PDT 24	7627229868 ps
T16	/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3285843			Jul 25 08:30:01 PM PDT 24	Jul 25 08:41:06 PM PDT 24	4192421470 ps
T34	/workspace/coverage/default/68.chip_sw_all_escalation_resets.2819236150			Jul 25 08:37:11 PM PDT 24	Jul 25 08:47:23 PM PDT 24	5554430176 ps
T203	/workspace/coverage/default/2.chip_plic_all_irqs_20.249592091			Jul 25 08:23:21 PM PDT 24	Jul 25 08:37:04 PM PDT 24	4973018556 ps
T204	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3033006936			Jul 25 08:37:05 PM PDT 24	Jul 25 08:42:08 PM PDT 24	3429376500 ps
T186	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1972946965			Jul 25 08:25:41 PM PDT 24	Jul 25 08:30:48 PM PDT 24	3478225444 ps
T70	/workspace/coverage/default/29.chip_sw_all_escalation_resets.1211874005			Jul 25 08:33:28 PM PDT 24	Jul 25 08:43:15 PM PDT 24	4393801416 ps
T71	/workspace/coverage/default/69.chip_sw_all_escalation_resets.355557894			Jul 25 08:34:59 PM PDT 24	Jul 25 08:44:08 PM PDT 24	4953213400 ps
T17	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1408988755			Jul 25 08:30:21 PM PDT 24	Jul 25 08:40:43 PM PDT 24	4471003560 ps
T381	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1442286806			Jul 25 08:15:54 PM PDT 24	Jul 25 08:18:57 PM PDT 24	2756939452 ps
T352	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2383145178			Jul 25 08:37:58 PM PDT 24	Jul 25 08:44:45 PM PDT 24	3631165964 ps
T9	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.946206205			Jul 25 08:05:29 PM PDT 24	Jul 25 08:17:21 PM PDT 24	7755083628 ps
T128	/workspace/coverage/default/1.chip_sw_edn_kat.939993128			Jul 25 08:09:20 PM PDT 24	Jul 25 08:20:34 PM PDT 24	3418856562 ps
T126	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1483882560			Jul 25 08:18:52 PM PDT 24	Jul 25 09:09:42 PM PDT 24	37148166409 ps
T120	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3720262090			Jul 25 08:24:04 PM PDT 24	Jul 25 08:28:35 PM PDT 24	2856703618 ps
T158	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.861736336			Jul 25 08:17:24 PM PDT 24	Jul 25 08:36:39 PM PDT 24	7438833096 ps
T520	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.791086172			Jul 25 08:36:38 PM PDT 24	Jul 25 08:42:53 PM PDT 24	4027322850 ps
T174	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.802966150			Jul 25 08:15:57 PM PDT 24	Jul 25 08:40:50 PM PDT 24	20018766839 ps
T438	/workspace/coverage/default/2.chip_sw_flash_ctrl_access.4213511109			Jul 25 08:21:31 PM PDT 24	Jul 25 08:36:35 PM PDT 24	5485048548 ps
T884	/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.4001162621			Jul 25 08:02:55 PM PDT 24	Jul 25 08:07:30 PM PDT 24	2780829488 ps
T201	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2252882913			Jul 25 08:10:15 PM PDT 24	Jul 25 08:19:39 PM PDT 24	6001371384 ps
T52	/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2296012906			Jul 25 07:59:25 PM PDT 24	Jul 25 08:34:59 PM PDT 24	22605568435 ps
T639	/workspace/coverage/default/0.chip_sw_csrng_smoketest.1284432935			Jul 25 08:05:13 PM PDT 24	Jul 25 08:09:45 PM PDT 24	2170129144 ps
T885	/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.188544555			Jul 25 08:12:59 PM PDT 24	Jul 25 08:18:26 PM PDT 24	2782816760 ps
T49	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3485695556			Jul 25 08:22:07 PM PDT 24	Jul 25 09:33:38 PM PDT 24	15318957915 ps
T153	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2870469903			Jul 25 08:25:12 PM PDT 24	Jul 25 08:33:28 PM PDT 24	4536394732 ps
T344	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1235283656			Jul 25 08:17:57 PM PDT 24	Jul 25 08:32:07 PM PDT 24	5345937548 ps
T642	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2170440612			Jul 25 08:21:06 PM PDT 24	Jul 25 08:25:55 PM PDT 24	2993430968 ps
T123	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.531496346			Jul 25 08:22:38 PM PDT 24	Jul 25 08:35:15 PM PDT 24	4163340628 ps
T76	/workspace/coverage/default/3.chip_tap_straps_dev.1389577466			Jul 25 08:26:49 PM PDT 24	Jul 25 08:51:28 PM PDT 24	15825442800 ps
T886	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2906226876			Jul 25 08:17:43 PM PDT 24	Jul 25 08:22:40 PM PDT 24	2895974650 ps
T259	/workspace/coverage/default/2.chip_sw_plic_sw_irq.1659935420			Jul 25 08:28:49 PM PDT 24	Jul 25 08:33:28 PM PDT 24	3197979120 ps
T227	/workspace/coverage/default/50.chip_sw_all_escalation_resets.3300927824			Jul 25 08:34:42 PM PDT 24	Jul 25 08:45:37 PM PDT 24	5339333438 ps
T358	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1200991385			Jul 25 08:36:45 PM PDT 24	Jul 25 08:44:01 PM PDT 24	4320658136 ps
T74	/workspace/coverage/default/0.chip_tap_straps_rma.2917114646			Jul 25 08:02:03 PM PDT 24	Jul 25 08:10:12 PM PDT 24	4698791241 ps
T114	/workspace/coverage/default/1.chip_sw_power_sleep_load.4023359344			Jul 25 08:15:29 PM PDT 24	Jul 25 08:24:06 PM PDT 24	4400230712 ps
T363	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.214135546			Jul 25 08:30:21 PM PDT 24	Jul 25 08:36:22 PM PDT 24	3304700696 ps
T315	/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3862862308			Jul 25 08:21:08 PM PDT 24	Jul 25 08:31:07 PM PDT 24	4571620576 ps
T121	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.882804805			Jul 25 08:03:55 PM PDT 24	Jul 25 08:13:13 PM PDT 24	3997558538 ps
T290	/workspace/coverage/default/2.chip_sw_aes_enc.2539114188			Jul 25 08:19:35 PM PDT 24	Jul 25 08:23:43 PM PDT 24	2993047460 ps
T291	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.4069334111			Jul 25 08:30:32 PM PDT 24	Jul 25 08:38:45 PM PDT 24	3843811480 ps
T292	/workspace/coverage/default/2.chip_sw_csrng_smoketest.3783723506			Jul 25 08:24:59 PM PDT 24	Jul 25 08:28:51 PM PDT 24	2959002576 ps
T127	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1153474682			Jul 25 08:01:52 PM PDT 24	Jul 25 08:16:18 PM PDT 24	9580281692 ps
T293	/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.4165443811			Jul 25 08:02:35 PM PDT 24	Jul 25 08:09:54 PM PDT 24	3059645184 ps
T228	/workspace/coverage/default/62.chip_sw_all_escalation_resets.2265755383			Jul 25 08:34:12 PM PDT 24	Jul 25 08:44:01 PM PDT 24	4419513684 ps
T213	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1847607512			Jul 25 08:00:01 PM PDT 24	Jul 25 08:06:42 PM PDT 24	3330013182 ps
T294	/workspace/coverage/default/91.chip_sw_all_escalation_resets.3674568620			Jul 25 08:36:56 PM PDT 24	Jul 25 08:46:30 PM PDT 24	4318068682 ps
T295	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.507756425			Jul 25 08:08:46 PM PDT 24	Jul 25 08:13:01 PM PDT 24	2692876120 ps
T132	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2358062047			Jul 25 08:20:36 PM PDT 24	Jul 25 08:31:08 PM PDT 24	8194915595 ps
T334	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4012969236			Jul 25 08:05:37 PM PDT 24	Jul 25 08:29:01 PM PDT 24	13370237875 ps
T18	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.413903411			Jul 25 07:59:55 PM PDT 24	Jul 25 10:06:08 PM PDT 24	31674255352 ps
T85	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3281506668			Jul 25 08:02:37 PM PDT 24	Jul 25 08:32:32 PM PDT 24	12067990348 ps
T129	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2120650996			Jul 25 08:02:27 PM PDT 24	Jul 25 08:25:43 PM PDT 24	6600421714 ps
T389	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2615112335			Jul 25 08:07:01 PM PDT 24	Jul 25 08:13:05 PM PDT 24	4495047960 ps
T439	/workspace/coverage/default/14.chip_sw_all_escalation_resets.1010336441			Jul 25 08:30:53 PM PDT 24	Jul 25 08:43:41 PM PDT 24	4998352156 ps
T686	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1151701828			Jul 25 08:32:51 PM PDT 24	Jul 25 08:39:17 PM PDT 24	3932883960 ps
T219	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3518794270			Jul 25 08:21:08 PM PDT 24	Jul 25 08:50:41 PM PDT 24	8445132050 ps
T308	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.735477911			Jul 25 08:29:50 PM PDT 24	Jul 25 08:35:52 PM PDT 24	3232429640 ps
T86	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2860247432			Jul 25 08:31:38 PM PDT 24	Jul 25 08:39:42 PM PDT 24	3769126532 ps
T95	/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.827605943			Jul 25 08:28:54 PM PDT 24	Jul 25 09:33:43 PM PDT 24	21342088760 ps
T69	/workspace/coverage/default/0.rom_volatile_raw_unlock.3318943049			Jul 25 08:02:25 PM PDT 24	Jul 25 08:04:00 PM PDT 24	2135422740 ps
T75	/workspace/coverage/default/1.chip_tap_straps_rma.2655868256			Jul 25 08:13:04 PM PDT 24	Jul 25 08:21:20 PM PDT 24	4807671270 ps
T96	/workspace/coverage/default/2.chip_sw_otbn_smoketest.622510808			Jul 25 08:25:50 PM PDT 24	Jul 25 08:46:39 PM PDT 24	5620326008 ps
T50	/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3685467957			Jul 25 08:05:38 PM PDT 24	Jul 25 09:05:27 PM PDT 24	15806710196 ps
T97	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3152239141			Jul 25 08:19:22 PM PDT 24	Jul 25 08:29:36 PM PDT 24	3960661824 ps
T98	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1341276284			Jul 25 08:26:37 PM PDT 24	Jul 25 08:30:23 PM PDT 24	2482923630 ps
T82	/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.3005101078			Jul 25 08:02:44 PM PDT 24	Jul 25 08:40:54 PM PDT 24	28497723368 ps
T68	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.3479278463			Jul 25 08:18:51 PM PDT 24	Jul 25 08:35:46 PM PDT 24	8830700049 ps
T51	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3737543350			Jul 25 08:10:25 PM PDT 24	Jul 25 09:06:36 PM PDT 24	11690130942 ps
T229	/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.484183119			Jul 25 08:08:31 PM PDT 24	Jul 25 08:25:09 PM PDT 24	6492612852 ps
T350	/workspace/coverage/default/77.chip_sw_all_escalation_resets.2622293870			Jul 25 08:36:31 PM PDT 24	Jul 25 08:42:55 PM PDT 24	4439749804 ps
T383	/workspace/coverage/default/1.rom_e2e_static_critical.564126612			Jul 25 08:20:50 PM PDT 24	Jul 25 09:26:22 PM PDT 24	16634231480 ps
T719	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.512494466			Jul 25 08:31:16 PM PDT 24	Jul 25 08:38:15 PM PDT 24	4534901100 ps
T124	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1368102834			Jul 25 08:22:38 PM PDT 24	Jul 25 08:34:09 PM PDT 24	4176619114 ps
T440	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.694852664			Jul 25 08:34:47 PM PDT 24	Jul 25 08:42:23 PM PDT 24	3499710412 ps
T230	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2009019684			Jul 25 08:05:13 PM PDT 24	Jul 25 08:28:14 PM PDT 24	8423110320 ps
T178	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.1844476244			Jul 25 08:23:47 PM PDT 24	Jul 25 08:50:22 PM PDT 24	22043228411 ps
T887	/workspace/coverage/default/0.chip_sw_clkmgr_jitter.1226057472			Jul 25 08:01:56 PM PDT 24	Jul 25 08:05:11 PM PDT 24	2813546285 ps
T179	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.894496633			Jul 25 08:07:17 PM PDT 24	Jul 25 08:17:52 PM PDT 24	5465897855 ps
T713	/workspace/coverage/default/47.chip_sw_all_escalation_resets.103665512			Jul 25 08:36:10 PM PDT 24	Jul 25 08:45:31 PM PDT 24	5122379288 ps
T319	/workspace/coverage/default/2.chip_plic_all_irqs_0.1289784231			Jul 25 08:24:55 PM PDT 24	Jul 25 08:42:48 PM PDT 24	6157984666 ps
T272	/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.274738882			Jul 25 07:59:57 PM PDT 24	Jul 25 08:08:14 PM PDT 24	8309879043 ps
T239	/workspace/coverage/default/0.rom_keymgr_functest.3631322685			Jul 25 08:05:13 PM PDT 24	Jul 25 08:12:19 PM PDT 24	5007145786 ps
T181	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2564642644			Jul 25 08:03:44 PM PDT 24	Jul 25 08:09:28 PM PDT 24	4888043854 ps
T231	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.535726722			Jul 25 08:20:15 PM PDT 24	Jul 25 08:32:48 PM PDT 24	6087027098 ps
T888	/workspace/coverage/default/0.chip_sw_uart_smoketest.1152619172			Jul 25 08:03:20 PM PDT 24	Jul 25 08:08:20 PM PDT 24	3495108210 ps
T718	/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.271182649			Jul 25 08:02:30 PM PDT 24	Jul 25 08:26:46 PM PDT 24	8324396936 ps
T712	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.714288223			Jul 25 08:32:50 PM PDT 24	Jul 25 08:40:36 PM PDT 24	3838445640 ps
T90	/workspace/coverage/default/0.chip_sw_inject_scramble_seed.2187596898			Jul 25 07:58:42 PM PDT 24	Jul 25 11:01:17 PM PDT 24	64957380496 ps
T265	/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3543322559			Jul 25 08:27:45 PM PDT 24	Jul 25 09:27:53 PM PDT 24	14566714566 ps
T386	/workspace/coverage/default/2.chip_sw_kmac_app_rom.2021422785			Jul 25 08:24:20 PM PDT 24	Jul 25 08:28:20 PM PDT 24	2429715828 ps
T889	/workspace/coverage/default/0.chip_sw_example_flash.3570951765			Jul 25 08:00:18 PM PDT 24	Jul 25 08:04:34 PM PDT 24	2273073506 ps
T170	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.417293489			Jul 25 08:01:41 PM PDT 24	Jul 25 09:41:36 PM PDT 24	51588264648 ps
T148	/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1191395439			Jul 25 08:11:11 PM PDT 24	Jul 25 08:14:58 PM PDT 24	2207577674 ps
T260	/workspace/coverage/default/0.chip_sw_plic_sw_irq.844639553			Jul 25 08:02:56 PM PDT 24	Jul 25 08:06:41 PM PDT 24	3269407292 ps
T523	/workspace/coverage/default/92.chip_sw_all_escalation_resets.65539851			Jul 25 08:37:24 PM PDT 24	Jul 25 08:46:19 PM PDT 24	4917663728 ps
T180	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3260934131			Jul 25 08:06:35 PM PDT 24	Jul 25 08:48:55 PM PDT 24	29487525960 ps
T165	/workspace/coverage/default/49.chip_sw_all_escalation_resets.4228237997			Jul 25 08:34:05 PM PDT 24	Jul 25 08:41:57 PM PDT 24	5458084468 ps
T646	/workspace/coverage/default/63.chip_sw_all_escalation_resets.3291803312			Jul 25 08:34:23 PM PDT 24	Jul 25 08:42:43 PM PDT 24	5622840042 ps
T441	/workspace/coverage/default/1.chip_sw_kmac_smoketest.25799884			Jul 25 08:16:24 PM PDT 24	Jul 25 08:21:17 PM PDT 24	3044894576 ps
T185	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.4094444730			Jul 25 08:04:09 PM PDT 24	Jul 25 08:17:57 PM PDT 24	7594521292 ps
T91	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1249189519			Jul 25 07:59:49 PM PDT 24	Jul 25 11:44:33 PM PDT 24	77821773672 ps
T384	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.4175108734			Jul 25 08:36:59 PM PDT 24	Jul 25 09:24:35 PM PDT 24	14980295200 ps
T221	/workspace/coverage/default/0.chip_sw_pattgen_ios.1763848773			Jul 25 07:59:11 PM PDT 24	Jul 25 08:03:47 PM PDT 24	2805304840 ps
T890	/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1368741770			Jul 25 08:29:17 PM PDT 24	Jul 25 09:40:10 PM PDT 24	20255616894 ps
T130	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1966703176			Jul 25 08:08:02 PM PDT 24	Jul 25 08:21:17 PM PDT 24	5608762363 ps
T10	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.5601527			Jul 25 08:04:21 PM PDT 24	Jul 25 08:10:20 PM PDT 24	2919605044 ps
T524	/workspace/coverage/default/21.chip_sw_all_escalation_resets.3631206156			Jul 25 08:30:38 PM PDT 24	Jul 25 08:42:23 PM PDT 24	5552245900 ps
T87	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1027939989			Jul 25 08:36:42 PM PDT 24	Jul 25 08:43:20 PM PDT 24	4125251920 ps
T707	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.3849642863			Jul 25 08:04:43 PM PDT 24	Jul 25 08:21:25 PM PDT 24	8181448062 ps
T224	/workspace/coverage/default/2.chip_sw_uart_tx_rx.100886453			Jul 25 08:17:36 PM PDT 24	Jul 25 08:29:21 PM PDT 24	4724747560 ps
T46	/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2715127118			Jul 25 08:20:25 PM PDT 24	Jul 25 09:13:15 PM PDT 24	15160044026 ps
T391	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.515523497			Jul 25 08:33:13 PM PDT 24	Jul 25 08:41:52 PM PDT 24	3478012660 ps
T442	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3513389964			Jul 25 08:16:32 PM PDT 24	Jul 25 08:21:41 PM PDT 24	3642837710 ps
T83	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1047064397			Jul 25 08:12:41 PM PDT 24	Jul 25 08:21:58 PM PDT 24	4136901192 ps
T364	/workspace/coverage/default/1.rom_e2e_self_hash.1122971279			Jul 25 08:19:18 PM PDT 24	Jul 25 09:59:25 PM PDT 24	26732181712 ps
T891	/workspace/coverage/default/0.rom_e2e_smoke.4104965201			Jul 25 08:06:27 PM PDT 24	Jul 25 09:12:48 PM PDT 24	14787462332 ps
T337	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.841243155			Jul 25 08:26:02 PM PDT 24	Jul 25 08:38:55 PM PDT 24	5384923777 ps
T892	/workspace/coverage/default/2.chip_sw_kmac_idle.2793990974			Jul 25 08:24:01 PM PDT 24	Jul 25 08:27:47 PM PDT 24	2763982150 ps
T893	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.510719065			Jul 25 08:22:18 PM PDT 24	Jul 25 09:29:32 PM PDT 24	15351977380 ps
T171	/workspace/coverage/default/13.chip_sw_all_escalation_resets.1657316080			Jul 25 08:29:15 PM PDT 24	Jul 25 08:40:20 PM PDT 24	6133157760 ps
T727	/workspace/coverage/default/36.chip_sw_all_escalation_resets.3105652593			Jul 25 08:34:16 PM PDT 24	Jul 25 08:44:59 PM PDT 24	6079633850 ps
T735	/workspace/coverage/default/56.chip_sw_all_escalation_resets.237788539			Jul 25 08:33:22 PM PDT 24	Jul 25 08:40:14 PM PDT 24	4072402484 ps
T742	/workspace/coverage/default/18.chip_sw_all_escalation_resets.4115068756			Jul 25 08:29:57 PM PDT 24	Jul 25 08:40:06 PM PDT 24	5490806596 ps
T166	/workspace/coverage/default/11.chip_sw_all_escalation_resets.2739813975			Jul 25 08:30:38 PM PDT 24	Jul 25 08:42:11 PM PDT 24	5373404472 ps
T345	/workspace/coverage/default/30.chip_sw_all_escalation_resets.2825464720			Jul 25 08:32:01 PM PDT 24	Jul 25 08:40:59 PM PDT 24	5990398252 ps
T894	/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1113482356			Jul 25 08:05:39 PM PDT 24	Jul 25 08:09:38 PM PDT 24	3645320534 ps
T261	/workspace/coverage/default/0.chip_sw_rv_timer_irq.1940465675			Jul 25 08:02:47 PM PDT 24	Jul 25 08:06:50 PM PDT 24	2918826760 ps
T662	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.652873522			Jul 25 08:19:09 PM PDT 24	Jul 25 08:53:10 PM PDT 24	23398047416 ps
T154	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.978153431			Jul 25 08:26:14 PM PDT 24	Jul 25 08:36:18 PM PDT 24	4206575560 ps
T125	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1347158614			Jul 25 07:59:04 PM PDT 24	Jul 25 08:30:29 PM PDT 24	8574531081 ps
T710	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2297858685			Jul 25 08:33:36 PM PDT 24	Jul 25 08:40:17 PM PDT 24	3315342516 ps
T521	/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.200077967			Jul 25 08:09:42 PM PDT 24	Jul 25 08:26:43 PM PDT 24	4544215908 ps
T252	/workspace/coverage/default/57.chip_sw_all_escalation_resets.774690176			Jul 25 08:34:17 PM PDT 24	Jul 25 08:43:17 PM PDT 24	5574362520 ps
T58	/workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.2669509583			Jul 25 08:08:18 PM PDT 24	Jul 25 08:13:19 PM PDT 24	3997045027 ps
T102	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1740721756			Jul 25 08:29:39 PM PDT 24	Jul 25 09:18:43 PM PDT 24	14741227196 ps
T103	/workspace/coverage/default/96.chip_sw_all_escalation_resets.3222453662			Jul 25 08:38:15 PM PDT 24	Jul 25 08:45:34 PM PDT 24	4962573820 ps
T104	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1816109000			Jul 25 08:01:35 PM PDT 24	Jul 25 08:47:02 PM PDT 24	13484830280 ps
T105	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.435169833			Jul 25 08:35:01 PM PDT 24	Jul 25 08:40:30 PM PDT 24	3386605038 ps
T106	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1610332107			Jul 25 08:26:22 PM PDT 24	Jul 25 08:32:05 PM PDT 24	6085095920 ps
T107	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4220707749			Jul 25 08:03:39 PM PDT 24	Jul 25 08:14:51 PM PDT 24	4740680304 ps
T35	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2872413987			Jul 25 08:00:27 PM PDT 24	Jul 25 08:04:59 PM PDT 24	3170271682 ps
T108	/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.499579144			Jul 25 08:28:38 PM PDT 24	Jul 25 08:35:21 PM PDT 24	3118732360 ps
T109	/workspace/coverage/default/1.chip_sw_inject_scramble_seed.451907691			Jul 25 08:06:49 PM PDT 24	Jul 25 11:12:13 PM PDT 24	65828091565 ps
T297	/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1809470267			Jul 25 08:29:14 PM PDT 24	Jul 25 09:15:16 PM PDT 24	13012209074 ps
T163	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.188925993			Jul 25 08:19:14 PM PDT 24	Jul 25 08:51:00 PM PDT 24	11767000848 ps
T298	/workspace/coverage/default/2.chip_sw_otbn_randomness.1215904249			Jul 25 08:21:39 PM PDT 24	Jul 25 08:38:42 PM PDT 24	6077849278 ps
T299	/workspace/coverage/default/0.rom_e2e_self_hash.645834038			Jul 25 08:11:00 PM PDT 24	Jul 25 09:48:21 PM PDT 24	26157940032 ps
T164	/workspace/coverage/default/4.chip_sw_all_escalation_resets.1367677538			Jul 25 08:26:37 PM PDT 24	Jul 25 08:36:56 PM PDT 24	5000978260 ps
T300	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4148185625			Jul 25 08:26:34 PM PDT 24	Jul 25 08:37:14 PM PDT 24	4383847412 ps
T226	/workspace/coverage/default/4.chip_tap_straps_dev.496910849			Jul 25 08:27:37 PM PDT 24	Jul 25 08:30:38 PM PDT 24	2431917620 ps
T301	/workspace/coverage/default/2.chip_sw_hmac_multistream.1499017837			Jul 25 08:21:59 PM PDT 24	Jul 25 08:44:35 PM PDT 24	6608963016 ps
T895	/workspace/coverage/default/1.chip_tap_straps_dev.2542766826			Jul 25 08:13:32 PM PDT 24	Jul 25 08:24:33 PM PDT 24	6860760767 ps
T115	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.4211200056			Jul 25 08:16:32 PM PDT 24	Jul 25 09:26:10 PM PDT 24	28082511697 ps
T714	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.4105619164			Jul 25 08:32:17 PM PDT 24	Jul 25 08:39:14 PM PDT 24	3600305504 ps
T645	/workspace/coverage/default/0.chip_sw_edn_kat.4006799665			Jul 25 08:00:49 PM PDT 24	Jul 25 08:09:47 PM PDT 24	3189756768 ps
T896	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2386648327			Jul 25 08:10:34 PM PDT 24	Jul 25 08:15:24 PM PDT 24	3458982622 ps
T897	/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3857357762			Jul 25 08:07:52 PM PDT 24	Jul 25 08:17:01 PM PDT 24	6588805506 ps
T647	/workspace/coverage/default/25.chip_sw_all_escalation_resets.1948861377			Jul 25 08:31:07 PM PDT 24	Jul 25 08:41:17 PM PDT 24	4672337488 ps
T898	/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.66769627			Jul 25 08:26:48 PM PDT 24	Jul 25 08:54:11 PM PDT 24	8182962360 ps
T223	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2577397515			Jul 25 08:03:19 PM PDT 24	Jul 25 08:15:29 PM PDT 24	4184599500 ps
T899	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.3202541765			Jul 25 08:21:09 PM PDT 24	Jul 25 09:30:39 PM PDT 24	14975601300 ps
T47	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1172443692			Jul 25 08:12:45 PM PDT 24	Jul 25 09:16:02 PM PDT 24	14938334323 ps
T187	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.181188496			Jul 25 08:12:45 PM PDT 24	Jul 25 08:18:06 PM PDT 24	2905266040 ps
T346	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1487913506			Jul 25 07:59:31 PM PDT 24	Jul 25 08:02:31 PM PDT 24	3252395485 ps
T220	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1872558892			Jul 25 08:37:17 PM PDT 24	Jul 25 08:43:57 PM PDT 24	3817792560 ps
T900	/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1446934245			Jul 25 08:27:15 PM PDT 24	Jul 25 08:30:14 PM PDT 24	2292147712 ps
T644	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1506011922			Jul 25 08:20:44 PM PDT 24	Jul 25 10:26:22 PM PDT 24	26635183960 ps
T901	/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3608834493			Jul 25 08:20:30 PM PDT 24	Jul 25 08:39:42 PM PDT 24	5732301376 ps
T255	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1129535692			Jul 25 07:58:58 PM PDT 24	Jul 25 08:21:05 PM PDT 24	9892139992 ps
T262	/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.1812032853			Jul 25 08:03:11 PM PDT 24	Jul 25 08:37:44 PM PDT 24	10837942116 ps
T902	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.2640384525			Jul 25 08:36:57 PM PDT 24	Jul 25 09:50:12 PM PDT 24	15212137156 ps
T377	/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.650950769			Jul 25 08:00:17 PM PDT 24	Jul 25 08:08:23 PM PDT 24	5101274062 ps
T903	/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1924540954			Jul 25 07:58:57 PM PDT 24	Jul 25 08:17:19 PM PDT 24	6348264951 ps
T365	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1337612428			Jul 25 08:10:18 PM PDT 24	Jul 25 09:21:13 PM PDT 24	15129547144 ps
T88	/workspace/coverage/default/2.chip_sw_alert_handler_entropy.1764535702			Jul 25 08:19:26 PM PDT 24	Jul 25 08:25:39 PM PDT 24	2820129977 ps
T904	/workspace/coverage/default/2.chip_sw_edn_auto_mode.3555696777			Jul 25 08:19:45 PM PDT 24	Jul 25 08:36:50 PM PDT 24	4977464344 ps
T182	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3195245416			Jul 25 08:00:02 PM PDT 24	Jul 25 08:02:35 PM PDT 24	4160132248 ps
T732	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2007996158			Jul 25 08:33:48 PM PDT 24	Jul 25 08:39:26 PM PDT 24	4336395264 ps
T522	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3579292007			Jul 25 08:01:41 PM PDT 24	Jul 25 08:15:17 PM PDT 24	4801761582 ps
T905	/workspace/coverage/default/0.chip_sw_hmac_smoketest.1940527105			Jul 25 08:03:46 PM PDT 24	Jul 25 08:09:25 PM PDT 24	3675908280 ps
T183	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3822357813			Jul 25 08:19:22 PM PDT 24	Jul 25 08:21:40 PM PDT 24	2953688690 ps
T270	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1810902787			Jul 25 08:08:00 PM PDT 24	Jul 25 08:09:38 PM PDT 24	2268587241 ps
T118	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.353169994			Jul 25 08:16:55 PM PDT 24	Jul 25 09:26:47 PM PDT 24	24251324000 ps
T689	/workspace/coverage/default/28.chip_sw_all_escalation_resets.1261432839			Jul 25 08:31:53 PM PDT 24	Jul 25 08:43:33 PM PDT 24	6369160324 ps
T232	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3861119747			Jul 25 08:07:08 PM PDT 24	Jul 25 08:31:38 PM PDT 24	8436822632 ps
T214	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3714797748			Jul 25 08:19:06 PM PDT 24	Jul 25 08:23:53 PM PDT 24	2474980045 ps
T140	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3951592474			Jul 25 08:27:57 PM PDT 24	Jul 25 08:39:51 PM PDT 24	6375951322 ps
T159	/workspace/coverage/default/1.chip_plic_all_irqs_10.1709843459			Jul 25 08:12:54 PM PDT 24	Jul 25 08:20:39 PM PDT 24	3894891436 ps
T19	/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3881739146			Jul 25 08:06:50 PM PDT 24	Jul 25 08:14:25 PM PDT 24	5160877154 ps
T906	/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.4223454781			Jul 25 08:18:44 PM PDT 24	Jul 25 08:35:29 PM PDT 24	11365877005 ps
T907	/workspace/coverage/default/1.rom_e2e_asm_init_rma.3669358993			Jul 25 08:19:44 PM PDT 24	Jul 25 09:14:36 PM PDT 24	15443236101 ps
T20	/workspace/coverage/default/0.chip_sw_usbdev_dpi.3478248912			Jul 25 08:00:31 PM PDT 24	Jul 25 08:56:53 PM PDT 24	12353521260 ps
T314	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1267697730			Jul 25 08:33:19 PM PDT 24	Jul 25 08:41:02 PM PDT 24	3743839206 ps
T191	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1287391234			Jul 25 08:04:42 PM PDT 24	Jul 25 09:21:10 PM PDT 24	44155398959 ps
T234	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1812462982			Jul 25 08:08:33 PM PDT 24	Jul 25 08:46:29 PM PDT 24	10785620318 ps
T734	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.4010385225			Jul 25 08:27:14 PM PDT 24	Jul 25 08:33:46 PM PDT 24	3485079298 ps
T780	/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2945268872			Jul 25 08:35:03 PM PDT 24	Jul 25 08:40:42 PM PDT 24	3816928950 ps
T307	/workspace/coverage/default/4.chip_sw_uart_tx_rx.2615839775			Jul 25 08:27:31 PM PDT 24	Jul 25 08:37:53 PM PDT 24	3945596408 ps
T908	/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2900126907			Jul 25 08:30:43 PM PDT 24	Jul 25 08:44:47 PM PDT 24	5576294744 ps
T909	/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3906764749			Jul 25 08:07:20 PM PDT 24	Jul 25 08:16:47 PM PDT 24	4774862380 ps
T910	/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2248652959			Jul 25 08:25:29 PM PDT 24	Jul 25 08:30:19 PM PDT 24	3071467186 ps
T245	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2694502867			Jul 25 07:59:16 PM PDT 24	Jul 25 09:40:37 PM PDT 24	52244077255 ps
T708	/workspace/coverage/default/75.chip_sw_all_escalation_resets.2591456505			Jul 25 08:36:57 PM PDT 24	Jul 25 08:48:51 PM PDT 24	5370413506 ps
T911	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.638690551			Jul 25 08:17:21 PM PDT 24	Jul 25 08:26:51 PM PDT 24	4214656194 ps
T912	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.400058234			Jul 25 08:07:22 PM PDT 24	Jul 25 08:17:42 PM PDT 24	9475900110 ps
T913	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3332164751			Jul 25 08:14:15 PM PDT 24	Jul 25 08:40:08 PM PDT 24	7568930116 ps
T160	/workspace/coverage/default/2.chip_plic_all_irqs_10.3142672810			Jul 25 08:22:55 PM PDT 24	Jul 25 08:32:33 PM PDT 24	3283107926 ps
T25	/workspace/coverage/default/1.chip_sw_gpio_smoketest.552847640			Jul 25 08:16:33 PM PDT 24	Jul 25 08:20:50 PM PDT 24	2985035442 ps
T914	/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1423539088			Jul 25 08:08:26 PM PDT 24	Jul 25 08:15:04 PM PDT 24	7255661678 ps
T251	/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3233813192			Jul 25 07:59:27 PM PDT 24	Jul 25 08:06:26 PM PDT 24	3641556760 ps
T390	/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3362558481			Jul 25 08:24:11 PM PDT 24	Jul 25 08:41:36 PM PDT 24	11008030552 ps
T347	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2267068339			Jul 25 08:29:59 PM PDT 24	Jul 25 08:35:20 PM PDT 24	2932189112 ps
T149	/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3238231131			Jul 25 08:21:57 PM PDT 24	Jul 25 08:27:11 PM PDT 24	3366668414 ps
T723	/workspace/coverage/default/78.chip_sw_all_escalation_resets.1957819846			Jul 25 08:36:07 PM PDT 24	Jul 25 08:45:02 PM PDT 24	5918617352 ps
T235	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.2933604047			Jul 25 08:08:06 PM PDT 24	Jul 25 08:16:17 PM PDT 24	5976705600 ps
T915	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2738663765			Jul 25 08:23:51 PM PDT 24	Jul 25 08:27:59 PM PDT 24	2582436576 ps
T916	/workspace/coverage/default/1.chip_sw_aes_smoketest.1438705773			Jul 25 08:15:46 PM PDT 24	Jul 25 08:18:57 PM PDT 24	2666319800 ps
T375	/workspace/coverage/default/0.chip_sw_edn_boot_mode.2688565989			Jul 25 08:00:16 PM PDT 24	Jul 25 08:09:22 PM PDT 24	3431798544 ps
T117	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.946883907			Jul 25 08:17:08 PM PDT 24	Jul 26 01:17:05 AM PDT 24	130545776204 ps
T917	/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2957115382			Jul 25 08:18:32 PM PDT 24	Jul 25 08:31:57 PM PDT 24	6175418176 ps
T53	/workspace/coverage/default/2.chip_jtag_csr_rw.2499107090			Jul 25 08:15:45 PM PDT 24	Jul 25 08:47:37 PM PDT 24	17533657324 ps
T133	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.557735214			Jul 25 08:26:20 PM PDT 24	Jul 25 08:43:31 PM PDT 24	8260670712 ps
T48	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2999812940			Jul 25 08:08:20 PM PDT 24	Jul 25 09:42:07 PM PDT 24	22332981220 ps
T316	/workspace/coverage/default/40.chip_sw_all_escalation_resets.765178586			Jul 25 08:32:47 PM PDT 24	Jul 25 08:42:40 PM PDT 24	5090171800 ps
T21	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.133588573			Jul 25 08:00:10 PM PDT 24	Jul 25 08:32:55 PM PDT 24	25313162100 ps
T724	/workspace/coverage/default/61.chip_sw_all_escalation_resets.1640617423			Jul 25 08:35:07 PM PDT 24	Jul 25 08:45:36 PM PDT 24	6492072060 ps
T271	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2921153852			Jul 25 08:09:35 PM PDT 24	Jul 25 09:44:32 PM PDT 24	23543762520 ps
T122	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2194833045			Jul 25 08:15:39 PM PDT 24	Jul 25 08:26:10 PM PDT 24	4722547199 ps
T918	/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.924203841			Jul 25 08:20:12 PM PDT 24	Jul 25 08:25:46 PM PDT 24	4082111328 ps
T919	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.849338140			Jul 25 08:18:39 PM PDT 24	Jul 25 08:23:13 PM PDT 24	3243666056 ps
T688	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.3983256877			Jul 25 08:03:43 PM PDT 24	Jul 25 08:11:07 PM PDT 24	6365521244 ps
T333	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.3496325969			Jul 25 08:02:25 PM PDT 24	Jul 25 08:11:15 PM PDT 24	3894590384 ps
T222	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1349940079			Jul 25 07:59:02 PM PDT 24	Jul 25 08:10:46 PM PDT 24	4632603090 ps
T753	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.571632529			Jul 25 08:31:50 PM PDT 24	Jul 25 08:39:13 PM PDT 24	3830668942 ps
T920	/workspace/coverage/default/1.chip_sw_hmac_smoketest.2306670884			Jul 25 08:16:27 PM PDT 24	Jul 25 08:22:47 PM PDT 24	3185630382 ps
T921	/workspace/coverage/default/0.chip_sw_edn_sw_mode.3001074565			Jul 25 08:03:35 PM PDT 24	Jul 25 08:34:27 PM PDT 24	7633533640 ps
T922	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1012979951			Jul 25 08:21:28 PM PDT 24	Jul 25 08:36:33 PM PDT 24	8643036712 ps
T923	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3433568072			Jul 25 08:06:14 PM PDT 24	Jul 25 08:10:15 PM PDT 24	3128394692 ps