Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3363	1			T79	11		T446	6		T430	36
all_values[1]	3397	1			T79	8		T446	1		T856	2
all_values[2]	3491	1			T79	4		T446	4		T856	2
all_values[3]	3487	1			T79	7		T446	3		T430	30
all_values[4]	3350	1			T79	5		T446	8		T856	1
all_values[5]	3390	1			T79	6		T446	4		T430	40
all_values[6]	3418	1			T79	5		T446	4		T856	1
all_values[7]	3327	1			T79	5		T446	7		T856	1
all_values[8]	3434	1			T79	11		T446	7		T856	2
all_values[9]	3415	1			T79	5		T446	6		T856	2
all_values[10]	3462	1			T79	4		T446	4		T856	2
all_values[11]	3392	1			T79	12		T446	7		T856	2
all_values[12]	3489	1			T79	12		T446	2		T856	3
all_values[13]	3446	1			T79	3		T446	3		T856	2
all_values[14]	3333	1			T79	7		T446	8		T856	1
all_values[15]	3334	1			T79	6		T446	8		T430	39
all_values[16]	3362	1			T79	9		T446	4		T856	4
all_values[17]	3401	1			T79	7		T446	3		T856	1
all_values[18]	3393	1			T79	5		T446	6		T856	2
all_values[19]	3384	1			T79	9		T446	4		T856	4
all_values[20]	3504	1			T446	4		T856	1		T430	33
all_values[21]	3390	1			T79	2		T446	3		T856	1
all_values[22]	3334	1			T79	8		T446	4		T856	3
all_values[23]	3440	1			T79	4		T446	6		T856	2
all_values[24]	3399	1			T79	3		T446	2		T856	5
all_values[25]	3431	1			T79	1		T446	3		T856	6
all_values[26]	3388	1			T79	6		T446	3		T856	3
all_values[27]	3351	1			T79	9		T446	5		T856	5
all_values[28]	3363	1			T79	6		T446	4		T856	2
all_values[29]	3376	1			T79	8		T446	4		T856	2
all_values[30]	3376	1			T79	3		T446	5		T856	3
all_values[31]	3334	1			T79	5		T446	6		T856	4
all_values[32]	3371	1			T79	6		T446	4		T856	2
all_values[33]	3421	1			T79	5		T446	9		T430	29
all_values[34]	3321	1			T79	5		T446	2		T856	2
all_values[35]	3257	1			T79	4		T446	6		T430	39
all_values[36]	3487	1			T79	4		T446	9		T430	33
all_values[37]	3509	1			T79	11		T446	3		T430	37
all_values[38]	3317	1			T79	5		T446	2		T856	1
all_values[39]	3264	1			T79	5		T446	4		T856	5
all_values[40]	3403	1			T79	7		T446	6		T856	1
all_values[41]	3370	1			T79	6		T446	2		T856	1
all_values[42]	3384	1			T79	9		T446	6		T856	2
all_values[43]	3385	1			T79	5		T446	6		T856	2
all_values[44]	3350	1			T79	5		T446	5		T856	2
all_values[45]	3440	1			T79	3		T446	5		T856	6
all_values[46]	3374	1			T79	5		T446	7		T856	2
all_values[47]	3358	1			T79	2		T446	5		T856	1
all_values[48]	3405	1			T79	10		T446	6		T856	2
all_values[49]	3307	1			T79	9		T446	7		T856	1
all_values[50]	3414	1			T79	4		T446	4		T856	2
all_values[51]	3425	1			T79	6		T446	2		T856	1
all_values[52]	3355	1			T79	8		T446	6		T856	2
all_values[53]	3407	1			T79	8		T446	1		T856	2
all_values[54]	3337	1			T79	5		T446	4		T856	1
all_values[55]	3406	1			T79	7		T446	5		T856	2
all_values[56]	3396	1			T79	10		T446	6		T856	1
all_values[57]	3296	1			T79	4		T446	5		T856	2
all_values[58]	3398	1			T79	5		T446	4		T430	28
all_values[59]	3354	1			T79	4		T446	4		T430	33
all_values[60]	3405	1			T79	3		T446	4		T856	5
all_values[61]	3362	1			T446	2		T430	34		T415	5
all_values[62]	3374	1			T79	7		T446	2		T856	4
all_values[63]	3349	1			T79	9		T446	6		T856	1