Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.alert_handler_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	143899	1			T71	2		T72	108		T73	40
values[2]	10225	1			T72	4		T77	1		T236	2
values[3]	3969	1			T846	1		T465	91		T467	176
values[4]	2372	1			T846	1		T465	73		T467	90
values[5]	1607	1			T846	1		T465	34		T467	39
values[6]	965	1			T846	1		T465	9		T467	23
values[7]	726	1			T846	1		T465	11		T467	27
values[8]	605	1			T846	1		T465	1		T467	26
values[9]	390	1			T846	1		T467	27		T522	7
values[10]	313	1			T846	1		T467	26		T522	6
values[11]	280	1			T846	1		T522	8		T847	4
values[12]	277	1			T846	1		T522	9		T847	2
values[13]	248	1			T846	1		T522	5		T847	13
values[14]	285	1			T846	1		T522	5		T847	6
values[15]	281	1			T846	1		T522	4		T847	4
values[16]	230	1			T846	1		T522	2		T847	16
values[17]	201	1			T846	1		T522	1		T847	5
values[18]	258	1			T846	1		T522	2		T847	4
values[19]	234	1			T846	1		T522	2		T847	4
values[20]	254	1			T846	1		T522	1		T847	3
values[21]	214	1			T846	1		T522	2		T847	3
values[22]	197	1			T846	1		T522	2		T847	4
values[23]	203	1			T846	1		T522	2		T847	3
values[24]	237	1			T846	1		T522	3		T847	5
values[25]	196	1			T846	1		T522	3		T847	27
values[26]	223	1			T846	1		T522	6		T847	8
values[27]	240	1			T846	1		T522	2		T847	6
values[28]	223	1			T846	1		T522	1		T847	8
values[29]	258	1			T846	1		T522	2		T847	2
values[30]	231	1			T846	1		T522	1		T847	7
values[31]	215	1			T846	1		T522	1		T847	16
values[32]	209	1			T846	1		T522	6		T847	5
values[33]	200	1			T846	1		T522	8		T847	2
values[34]	243	1			T846	1		T522	9		T847	11
values[35]	176	1			T846	1		T522	8		T847	9
values[36]	244	1			T846	1		T522	12		T847	2
values[37]	215	1			T846	1		T522	11		T847	8
values[38]	256	1			T846	1		T522	10		T847	5
values[39]	206	1			T846	1		T522	3		T847	9
values[40]	236	1			T846	1		T522	3		T847	10
values[41]	206	1			T846	1		T522	3		T847	4
values[42]	239	1			T846	1		T522	1		T847	10
values[43]	224	1			T846	1		T522	4		T847	11
values[44]	224	1			T846	1		T522	4		T847	6
values[45]	225	1			T846	1		T522	4		T847	4
values[46]	214	1			T846	1		T522	1		T847	4
values[47]	228	1			T846	1		T522	2		T847	6
values[48]	231	1			T846	1		T522	1		T847	6
values[49]	202	1			T846	1		T522	3		T847	10
values[50]	168	1			T846	1		T522	3		T847	4
values[51]	195	1			T846	1		T522	2		T847	3
values[52]	223	1			T846	1		T522	1		T847	3
values[53]	200	1			T846	1		T522	1		T847	4
values[54]	155	1			T846	1		T522	2		T847	4
values[55]	157	1			T846	1		T522	2		T847	7
values[56]	163	1			T846	1		T522	9		T847	3
values[57]	177	1			T846	1		T522	4		T847	10
values[58]	185	1			T846	1		T522	2		T847	4
values[59]	165	1			T846	1		T522	2		T847	5
values[60]	189	1			T846	1		T522	6		T847	5
values[61]	214	1			T846	1		T522	10		T847	2
values[62]	165	1			T846	1		T522	9		T847	9
values[63]	214	1			T846	1		T522	5		T847	22
values[64]	148	1			T846	1		T522	6		T847	5
values[65]	154	1			T846	1		T522	1		T847	5
values[66]	140	1			T846	1		T847	8		T848	1
values[67]	185	1			T846	1		T847	18		T848	1
values[68]	163	1			T846	1		T848	1		T849	1
values[69]	158	1			T846	1		T848	1		T849	1
values[70]	138	1			T846	1		T848	1		T849	1
values[71]	114	1			T846	1		T848	1		T849	1
values[72]	128	1			T846	1		T848	1		T849	1
values[73]	93	1			T846	1		T848	1		T849	1
values[74]	83	1			T846	1		T848	1		T849	1
values[75]	87	1			T846	1		T848	1		T849	1
values[76]	67	1			T846	1		T848	1		T849	1
values[77]	56	1			T846	1		T848	1		T849	1
values[78]	79	1			T846	1		T848	1		T849	3
values[79]	77	1			T846	1		T848	1		T849	4
values[80]	78	1			T846	1		T848	1		T849	4
values[81]	71	1			T846	1		T848	1		T849	6
values[82]	62	1			T846	1		T848	1		T849	4
values[83]	72	1			T846	1		T848	1		T849	4
values[84]	72	1			T846	1		T848	1		T849	4
values[85]	73	1			T846	1		T848	1		T849	5
values[86]	94	1			T846	1		T848	1		T849	3
values[87]	88	1			T846	2		T848	2		T849	6
values[88]	93	1			T846	4		T848	1		T849	4
values[89]	84	1			T846	1		T848	1		T849	4
values[90]	90	1			T846	2		T848	1		T849	7
values[91]	79	1			T846	2		T848	1		T849	4
values[92]	91	1			T846	3		T848	1		T849	10
values[93]	75	1			T846	1		T848	1		T849	2
values[94]	69	1			T846	1		T848	1		T849	1
values[95]	74	1			T846	3		T848	1		T849	1
values[96]	56	1			T846	1		T848	1		T849	4
values[97]	61	1			T846	1		T848	1		T849	8
values[98]	48	1			T846	3		T848	1		T849	3
values[99]	40	1			T846	1		T848	1		T849	1
values[100]	51	1			T846	1		T848	1		T849	4
values[101]	72	1			T846	3		T848	1		T849	6
values[102]	75	1			T846	3		T848	1		T849	2
values[103]	59	1			T846	1		T848	2		T849	1
values[104]	92	1			T846	5		T848	4		T849	1
values[105]	62	1			T846	2		T848	2		T849	1
values[106]	52	1			T846	2		T848	4		T849	2
values[107]	53	1			T846	1		T848	1		T849	1
values[108]	53	1			T846	2		T848	1		T849	3
values[109]	71	1			T846	3		T848	2		T849	1
values[110]	60	1			T846	5		T848	3		T849	2
values[111]	57	1			T846	2		T848	1		T849	1
values[112]	66	1			T846	2		T848	1		T849	3
values[113]	77	1			T846	3		T848	2		T849	8
values[114]	52	1			T846	1		T848	1		T849	1
values[115]	40	1			T846	1		T848	3		T849	1
values[116]	41	1			T846	2		T848	4		T849	1
values[117]	50	1			T846	1		T848	3		T849	2
values[118]	68	1			T846	1		T848	12		T849	2
values[119]	46	1			T846	1		T848	1		T849	1
values[120]	47	1			T846	2		T848	5		T849	1
values[121]	41	1			T846	2		T848	2		T849	2
values[122]	45	1			T846	2		T848	4		T849	1
values[123]	58	1			T846	3		T848	3		T849	3
values[124]	70	1			T846	1		T848	5		T849	2
values[125]	60	1			T846	1		T848	2		T849	1
values[126]	95	1			T846	3		T848	3		T849	8
values[127]	497	1			T846	34		T848	25		T849	17
values[128]	5110	1			T846	307		T848	301		T849	260

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	159964	1			T71	5		T72	148		T73	35
values[2]	4323	1			T71	1		T72	6		T73	1
values[3]	2052	1			T540	46		T467	84		T573	1
values[4]	1613	1			T540	77		T467	28		T522	3
values[5]	1393	1			T540	103		T467	36		T522	4
values[6]	1126	1			T540	86		T467	13		T522	4
values[7]	897	1			T540	41		T467	2		T522	4
values[8]	667	1			T540	24		T522	3		T848	1
values[9]	609	1			T540	13		T522	1		T848	1
values[10]	604	1			T540	10		T522	9		T848	1
values[11]	505	1			T540	10		T522	5		T848	1
values[12]	494	1			T540	3		T522	4		T848	1
values[13]	447	1			T540	1		T522	3		T848	1
values[14]	417	1			T522	4		T848	1		T849	1
values[15]	382	1			T522	3		T848	1		T849	1
values[16]	351	1			T522	5		T848	1		T849	1
values[17]	255	1			T522	5		T848	1		T849	1
values[18]	231	1			T522	6		T848	1		T849	1
values[19]	237	1			T522	2		T848	1		T849	1
values[20]	229	1			T522	1		T848	1		T849	1
values[21]	236	1			T522	2		T848	1		T849	1
values[22]	233	1			T522	3		T848	1		T849	1
values[23]	224	1			T522	2		T848	1		T849	1
values[24]	206	1			T522	1		T848	1		T849	1
values[25]	163	1			T522	2		T848	1		T849	1
values[26]	171	1			T522	7		T848	1		T849	1
values[27]	180	1			T522	3		T848	1		T849	1
values[28]	117	1			T522	2		T848	1		T849	1
values[29]	93	1			T522	2		T848	1		T849	1
values[30]	111	1			T522	2		T848	1		T849	1
values[31]	148	1			T522	1		T848	1		T849	1
values[32]	143	1			T522	3		T848	1		T849	1
values[33]	110	1			T522	6		T848	1		T849	1
values[34]	107	1			T522	1		T848	1		T849	1
values[35]	75	1			T522	1		T848	1		T849	1
values[36]	78	1			T522	2		T848	1		T849	1
values[37]	82	1			T522	1		T848	1		T849	1
values[38]	93	1			T522	2		T848	1		T849	1
values[39]	95	1			T522	2		T848	1		T849	1
values[40]	87	1			T522	1		T848	1		T849	1
values[41]	127	1			T522	3		T848	1		T849	1
values[42]	103	1			T522	2		T848	1		T849	1
values[43]	104	1			T522	2		T848	1		T849	1
values[44]	109	1			T522	1		T848	1		T849	1
values[45]	82	1			T522	3		T848	1		T849	2
values[46]	69	1			T522	1		T848	1		T849	1
values[47]	75	1			T522	2		T848	1		T849	1
values[48]	80	1			T522	2		T848	1		T849	1
values[49]	69	1			T522	1		T848	1		T849	1
values[50]	68	1			T522	1		T848	1		T849	1
values[51]	58	1			T522	2		T848	1		T849	1
values[52]	73	1			T522	1		T848	1		T849	1
values[53]	77	1			T522	3		T848	1		T849	1
values[54]	49	1			T522	1		T848	1		T849	1
values[55]	65	1			T522	1		T848	1		T849	1
values[56]	58	1			T522	2		T848	1		T849	1
values[57]	56	1			T522	2		T848	1		T849	1
values[58]	62	1			T522	3		T848	1		T849	1
values[59]	67	1			T522	4		T848	1		T849	1
values[60]	57	1			T522	1		T848	1		T849	1
values[61]	48	1			T522	1		T848	1		T849	1
values[62]	51	1			T522	2		T848	1		T849	1
values[63]	47	1			T522	5		T848	1		T849	1
values[64]	55	1			T522	3		T848	1		T849	1
values[65]	57	1			T522	2		T848	1		T849	1
values[66]	50	1			T522	1		T848	1		T849	1
values[67]	53	1			T522	1		T848	1		T849	1
values[68]	56	1			T522	3		T848	1		T849	1
values[69]	50	1			T522	3		T848	1		T849	1
values[70]	47	1			T522	2		T848	1		T849	1
values[71]	45	1			T522	1		T848	1		T849	1
values[72]	50	1			T522	1		T848	1		T849	1
values[73]	61	1			T522	2		T848	1		T849	1
values[74]	65	1			T522	2		T848	1		T849	1
values[75]	61	1			T522	3		T848	1		T849	1
values[76]	63	1			T522	1		T848	2		T849	1
values[77]	77	1			T522	2		T848	2		T849	1
values[78]	60	1			T522	6		T848	2		T849	1
values[79]	61	1			T522	2		T848	2		T849	1
values[80]	66	1			T522	1		T848	1		T849	1
values[81]	72	1			T522	3		T848	3		T849	1
values[82]	70	1			T522	3		T848	4		T849	1
values[83]	71	1			T522	6		T848	2		T849	1
values[84]	62	1			T522	1		T848	4		T849	1
values[85]	89	1			T522	7		T848	4		T849	1
values[86]	80	1			T522	2		T848	6		T849	1
values[87]	84	1			T522	2		T848	1		T849	1
values[88]	69	1			T522	2		T848	5		T849	1
values[89]	70	1			T522	2		T848	4		T849	1
values[90]	77	1			T522	1		T848	3		T849	1
values[91]	87	1			T522	3		T848	4		T849	2
values[92]	85	1			T522	4		T848	3		T849	1
values[93]	84	1			T522	4		T848	2		T849	3
values[94]	74	1			T522	1		T848	1		T849	2
values[95]	82	1			T522	1		T848	1		T849	2
values[96]	68	1			T522	1		T848	1		T849	2
values[97]	88	1			T522	3		T848	3		T849	11
values[98]	84	1			T522	3		T848	4		T849	1
values[99]	94	1			T522	2		T848	5		T849	1
values[100]	98	1			T522	3		T848	3		T849	1
values[101]	91	1			T522	2		T848	1		T849	1
values[102]	79	1			T522	2		T848	1		T849	2
values[103]	92	1			T522	10		T848	1		T849	3
values[104]	74	1			T522	2		T848	2		T849	1
values[105]	77	1			T522	4		T848	3		T849	3
values[106]	81	1			T522	2		T848	2		T849	1
values[107]	79	1			T522	4		T848	2		T849	1
values[108]	74	1			T522	1		T848	1		T849	2
values[109]	90	1			T522	4		T848	3		T849	1
values[110]	80	1			T522	3		T848	2		T849	1
values[111]	77	1			T522	3		T848	1		T849	1
values[112]	88	1			T522	3		T848	3		T849	2
values[113]	88	1			T522	5		T848	6		T849	2
values[114]	97	1			T522	3		T848	2		T849	1
values[115]	85	1			T522	3		T848	1		T849	1
values[116]	90	1			T522	5		T848	1		T849	1
values[117]	102	1			T522	2		T848	1		T849	2
values[118]	119	1			T522	1		T848	2		T849	1
values[119]	115	1			T522	1		T848	1		T849	3
values[120]	109	1			T522	4		T848	2		T849	3
values[121]	119	1			T522	5		T848	2		T849	2
values[122]	117	1			T522	4		T848	1		T849	1
values[123]	119	1			T522	7		T848	2		T849	1
values[124]	149	1			T522	15		T848	1		T849	1
values[125]	261	1			T522	14		T848	1		T849	1
values[126]	811	1			T522	30		T848	20		T849	18
values[127]	3486	1			T522	24		T848	117		T849	128
values[128]	6112	1			T522	2		T848	175		T849	212

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	146128	1			T71	2		T72	120		T73	39
values[2]	10609	1			T72	1		T73	1		T236	3
values[3]	4342	1			T540	109		T850	94		T573	1
values[4]	2451	1			T540	68		T850	60		T478	4
values[5]	1483	1			T540	63		T850	19		T478	13
values[6]	975	1			T540	60		T850	10		T478	3
values[7]	658	1			T540	21		T478	13		T851	3
values[8]	533	1			T540	16		T478	15		T851	3
values[9]	475	1			T540	10		T478	8		T851	3
values[10]	343	1			T540	2		T478	4		T851	2
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