Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.21	95.60	94.19	95.49		94.90	97.53	99.53

Total tests in report: 2935

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.64	39.64	44.87	44.87	42.99	42.99	32.27	32.27			58.02	58.02	59.27	59.27	0.39	0.39	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.921172117
51.99	12.35	57.62	12.74	62.43	19.44	37.61	5.34			70.17	12.15	82.34	23.08	1.75	1.36	/workspace/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.1705445246
57.39	5.40	69.18	11.57	70.29	7.85	40.09	2.48			80.67	10.50	82.34	0.00	1.75	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1972172357
61.58	4.20	69.18	0.00	70.31	0.02	40.09	0.00			80.67	0.00	82.34	0.00	26.91	25.16	/workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.1232646521
64.79	3.21	74.51	5.32	74.31	4.00	43.66	3.57			82.48	1.82	86.89	4.55	26.91	0.00	/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.351464795
67.57	2.78	79.35	4.84	74.64	0.32	45.89	2.23			82.55	0.06	86.89	0.00	36.12	9.21	/workspace/coverage/cover_reg_top/87.xbar_random_large_delays.3328954833
70.12	2.54	79.35	0.00	74.64	0.00	45.89	0.00			82.55	0.00	86.89	0.00	51.38	15.26	/workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.2417516154
72.51	2.39	79.35	0.00	74.64	0.00	60.26	14.37			82.55	0.00	86.89	0.00	51.38	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1302298419
74.85	2.34	82.07	2.72	77.81	3.18	65.44	5.18			84.97	2.43	87.41	0.52	51.38	0.00	/workspace/coverage/default/1.rom_e2e_asm_init_dev.3856523325
76.98	2.13	82.07	0.00	77.81	0.00	65.44	0.00			84.97	0.00	87.41	0.00	64.16	12.78	/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.339185383
78.83	1.85	82.07	0.01	78.15	0.34	66.00	0.55			85.00	0.02	87.41	0.00	74.33	10.16	/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.1713814943
80.67	1.84	84.50	2.43	80.01	1.86	68.00	2.00			86.46	1.46	90.56	3.15	74.48	0.15	/workspace/coverage/default/2.chip_jtag_csr_rw.81228776
82.28	1.62	86.94	2.44	81.42	1.42	71.87	3.87			87.38	0.92	91.61	1.05	74.48	0.00	/workspace/coverage/default/1.chip_sw_power_virus.1185422705
83.70	1.42	87.23	0.29	81.57	0.15	79.41	7.54			87.55	0.18	91.96	0.35	74.48	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2927319818
84.63	0.93	87.23	0.00	82.00	0.43	79.41	0.00			87.67	0.11	91.96	0.00	79.52	5.04	/workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.3595452166
85.47	0.84	87.23	0.00	82.00	0.00	79.41	0.00			87.67	0.00	91.96	0.00	84.55	5.03	/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3938667225
86.20	0.73	87.53	0.30	82.11	0.11	79.42	0.01			87.78	0.11	95.80	3.85	84.55	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1956630318
86.93	0.73	88.83	1.30	83.08	0.96	80.22	0.80			89.08	1.30	95.80	0.00	84.55	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.3669978527
87.65	0.72	89.86	1.03	84.63	1.55	80.37	0.15			90.67	1.59	95.80	0.00	84.55	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3264989156
88.35	0.71	90.80	0.94	85.50	0.87	82.13	1.76			91.31	0.64	95.80	0.00	84.58	0.04	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.927794496
89.03	0.68	92.01	1.22	86.49	0.99	82.84	0.71			92.45	1.14	95.80	0.00	84.58	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.3460190826
89.66	0.62	92.01	0.00	86.59	0.10	82.84	0.00			92.45	0.00	95.80	0.00	88.23	3.64	/workspace/coverage/cover_reg_top/69.xbar_access_same_device.2570483071
90.24	0.58	92.68	0.66	87.17	0.58	83.84	1.00			93.14	0.69	96.33	0.52	88.27	0.05	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.412098686
90.82	0.58	92.69	0.01	87.17	0.01	87.29	3.44			93.14	0.00	96.33	0.00	88.27	0.00	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1674469914
91.23	0.41	92.69	0.00	87.18	0.01	87.29	0.00			93.14	0.00	96.33	0.00	90.74	2.47	/workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.1299711750
91.63	0.40	92.71	0.02	87.22	0.04	87.79	0.51			93.14	0.00	96.33	0.00	92.60	1.86	/workspace/coverage/default/1.chip_sw_alert_test.2105827872
92.00	0.37	92.71	0.00	87.22	0.00	87.79	0.00			93.14	0.00	96.33	0.00	94.82	2.22	/workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.578791726
92.26	0.26	93.32	0.62	87.52	0.31	88.14	0.34			93.40	0.26	96.33	0.00	94.82	0.00	/workspace/coverage/default/0.chip_sw_gpio_smoketest.2016930232
92.50	0.24	93.32	0.00	87.52	0.00	89.53	1.39			93.40	0.00	96.33	0.00	94.87	0.05	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.1523308141
92.73	0.24	93.63	0.30	88.48	0.95	89.54	0.01			93.57	0.17	96.33	0.00	94.87	0.00	/workspace/coverage/cover_reg_top/17.chip_csr_rw.2544231432
92.96	0.22	93.63	0.00	88.68	0.21	89.54	0.00			93.57	0.00	96.33	0.00	95.99	1.13	/workspace/coverage/cover_reg_top/8.xbar_stress_all.356804631
93.18	0.22	93.81	0.18	88.76	0.07	90.36	0.82			93.61	0.03	96.50	0.17	96.03	0.04	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1777985909
93.38	0.21	93.81	0.01	89.93	1.17	90.36	0.00			93.61	0.00	96.50	0.00	96.09	0.06	/workspace/coverage/cover_reg_top/4.chip_tl_errors.3000277110
93.53	0.15	94.02	0.21	90.25	0.32	90.71	0.35			93.61	0.00	96.50	0.00	96.09	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.66893339
93.67	0.14	94.02	0.00	90.25	0.00	90.71	0.00			93.61	0.00	96.50	0.00	96.93	0.85	/workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.3979824915
93.80	0.13	94.02	0.00	90.27	0.02	90.71	0.00			93.61	0.00	96.50	0.00	97.72	0.79	/workspace/coverage/cover_reg_top/77.xbar_access_same_device.1227757907
93.93	0.13	94.02	0.00	90.27	0.00	91.47	0.77			93.61	0.00	96.50	0.00	97.72	0.00	/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.3971021027
94.04	0.11	94.02	0.00	90.58	0.31	91.47	0.00			93.96	0.36	96.50	0.00	97.72	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2276907550
94.15	0.11	94.02	0.00	90.58	0.00	92.12	0.65			93.96	0.00	96.50	0.00	97.72	0.00	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2869877241
94.26	0.11	94.02	0.00	91.14	0.56	92.12	0.00			93.96	0.00	96.50	0.00	97.80	0.08	/workspace/coverage/cover_reg_top/22.chip_tl_errors.2225058175
94.34	0.08	94.03	0.01	91.36	0.22	92.14	0.02			94.21	0.24	96.50	0.00	97.80	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1325672635
94.42	0.08	94.03	0.00	91.36	0.00	92.63	0.49			94.21	0.00	96.50	0.00	97.80	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3446582649
94.50	0.08	94.03	0.00	91.36	0.00	93.09	0.46			94.21	0.00	96.50	0.00	97.80	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2910125751
94.58	0.08	94.03	0.00	91.39	0.02	93.51	0.41			94.22	0.02	96.50	0.00	97.80	0.00	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.699613592
94.65	0.07	94.19	0.16	91.49	0.10	93.59	0.08			94.32	0.10	96.50	0.00	97.80	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.3149075687
94.72	0.07	94.19	0.00	91.66	0.17	93.59	0.00			94.32	0.00	96.50	0.00	98.07	0.27	/workspace/coverage/cover_reg_top/40.xbar_stress_all.1173945141
94.79	0.07	94.28	0.10	91.85	0.19	93.61	0.03			94.40	0.08	96.50	0.00	98.07	0.00	/workspace/coverage/default/1.chip_jtag_csr_rw.1630992459
94.85	0.06	94.28	0.00	91.85	0.00	93.99	0.38			94.40	0.00	96.50	0.00	98.07	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.851001071
94.91	0.06	94.33	0.05	91.91	0.06	94.02	0.03			94.44	0.04	96.68	0.17	98.08	0.01	/workspace/coverage/default/93.chip_sw_all_escalation_resets.865951925
94.96	0.05	94.33	0.00	92.23	0.32	94.02	0.00			94.44	0.00	96.68	0.00	98.08	0.00	/workspace/coverage/cover_reg_top/21.chip_tl_errors.3817662877
95.01	0.05	94.39	0.06	92.29	0.07	94.12	0.10			94.52	0.07	96.68	0.00	98.08	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3203322415
95.06	0.04	94.39	0.00	92.29	0.00	94.21	0.09			94.52	0.00	96.85	0.17	98.08	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3910700363
95.10	0.04	94.44	0.04	92.48	0.19	94.21	0.00			94.53	0.02	96.85	0.00	98.08	0.00	/workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.181060381
95.14	0.04	94.56	0.12	92.48	0.00	94.30	0.09			94.53	0.00	96.85	0.00	98.12	0.04	/workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.3429850458
95.18	0.04	94.61	0.04	92.60	0.12	94.30	0.00			94.60	0.07	96.85	0.00	98.12	0.00	/workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.3469573537
95.22	0.04	94.62	0.01	92.62	0.01	94.30	0.00			94.63	0.02	97.03	0.17	98.13	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.98941573
95.26	0.04	94.64	0.03	92.62	0.01	94.30	0.01			94.64	0.01	97.20	0.17	98.14	0.01	/workspace/coverage/default/22.chip_sw_all_escalation_resets.366268269
95.30	0.04	94.65	0.01	92.65	0.02	94.30	0.00			94.65	0.01	97.38	0.17	98.16	0.01	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3498545560
95.33	0.04	94.66	0.01	92.66	0.01	94.30	0.01			94.65	0.01	97.55	0.17	98.17	0.01	/workspace/coverage/default/4.chip_sw_all_escalation_resets.4098062106
95.36	0.03	94.66	0.00	92.68	0.02	94.30	0.00			94.65	0.00	97.55	0.00	98.34	0.18	/workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.4081400449
95.39	0.03	94.66	0.00	92.68	0.00	94.49	0.18			94.65	0.00	97.55	0.00	98.34	0.00	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.157495116
95.42	0.03	94.66	0.00	92.85	0.17	94.49	0.00			94.65	0.00	97.55	0.00	98.34	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.853826638
95.45	0.03	94.73	0.07	92.88	0.03	94.50	0.01			94.70	0.05	97.55	0.00	98.34	0.00	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1052199788
95.48	0.03	94.73	0.00	93.04	0.16	94.50	0.00			94.70	0.00	97.55	0.00	98.34	0.00	/workspace/coverage/cover_reg_top/12.chip_tl_errors.1123524156
95.50	0.03	94.80	0.07	93.04	0.00	94.57	0.07			94.71	0.01	97.55	0.00	98.34	0.00	/workspace/coverage/default/3.chip_tap_straps_testunlock0.1516178660
95.53	0.02	94.81	0.01	93.04	0.00	94.70	0.13			94.72	0.01	97.55	0.00	98.34	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.1336349441
95.55	0.02	94.81	0.00	93.04	0.00	94.84	0.14			94.72	0.00	97.55	0.00	98.34	0.00	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.881992644
95.57	0.02	94.87	0.07	93.09	0.05	94.84	0.00			94.73	0.02	97.55	0.00	98.34	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.3283494091
95.59	0.02	94.87	0.00	93.16	0.07	94.84	0.00			94.73	0.00	97.55	0.00	98.40	0.06	/workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.2203634387
95.61	0.02	94.92	0.05	93.21	0.05	94.84	0.00			94.76	0.02	97.55	0.00	98.40	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1207724059
95.63	0.02	94.92	0.00	93.24	0.03	94.84	0.00			94.77	0.02	97.55	0.00	98.46	0.06	/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.4106573341
95.65	0.02	94.92	0.00	93.35	0.11	94.84	0.00			94.77	0.00	97.55	0.00	98.46	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.2965659041
95.66	0.02	94.93	0.01	93.36	0.01	94.91	0.07			94.77	0.00	97.55	0.00	98.46	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3540377513
95.68	0.01	94.93	0.00	93.37	0.01	94.91	0.00			94.77	0.00	97.55	0.00	98.53	0.07	/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.455839779
95.69	0.01	94.93	0.00	93.45	0.08	94.91	0.00			94.77	0.00	97.55	0.00	98.53	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.806197287
95.70	0.01	94.93	0.00	93.49	0.04	94.91	0.00			94.77	0.00	97.55	0.00	98.57	0.04	/workspace/coverage/cover_reg_top/72.xbar_access_same_device.4221318781
95.72	0.01	94.93	0.00	93.49	0.00	94.98	0.07			94.77	0.00	97.55	0.00	98.57	0.00	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2422529841
95.73	0.01	94.93	0.00	93.54	0.05	95.00	0.02			94.77	0.00	97.55	0.00	98.57	0.00	/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.1740681440
95.74	0.01	94.95	0.01	93.57	0.03	95.00	0.01			94.79	0.02	97.55	0.00	98.57	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3567808658
95.75	0.01	94.95	0.00	93.61	0.04	95.00	0.00			94.82	0.02	97.55	0.00	98.57	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.1681608371
95.76	0.01	94.97	0.02	93.61	0.01	95.00	0.01			94.83	0.02	97.55	0.00	98.57	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3669188701
95.77	0.01	95.00	0.02	93.62	0.01	95.01	0.01			94.85	0.02	97.55	0.00	98.57	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.4271165214
95.77	0.01	95.00	0.00	93.67	0.05	95.01	0.00			94.85	0.00	97.55	0.00	98.57	0.00	/workspace/coverage/cover_reg_top/25.chip_tl_errors.3549269814
95.78	0.01	95.00	0.00	93.67	0.00	95.04	0.04			94.85	0.00	97.55	0.00	98.58	0.01	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1517453204
95.79	0.01	95.00	0.00	93.67	0.00	95.09	0.04			94.85	0.00	97.55	0.00	98.58	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.63344132
95.80	0.01	95.00	0.00	93.69	0.02	95.09	0.00			94.85	0.00	97.55	0.00	98.60	0.02	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.408094103
95.80	0.01	95.00	0.00	93.71	0.02	95.10	0.02			94.85	0.00	97.55	0.00	98.60	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx.3512263128
95.81	0.01	95.00	0.01	93.72	0.01	95.11	0.01			94.86	0.02	97.55	0.00	98.60	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3533279241
95.82	0.01	95.00	0.00	93.76	0.04	95.11	0.00			94.86	0.00	97.55	0.00	98.60	0.00	/workspace/coverage/cover_reg_top/92.xbar_stress_all.4159319330
95.82	0.01	95.00	0.00	93.76	0.01	95.11	0.00			94.86	0.00	97.55	0.00	98.64	0.04	/workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.3086958147
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95.84	0.01	95.01	0.00	93.80	0.04	95.18	0.00			94.86	0.00	97.55	0.00	98.64	0.00	/workspace/coverage/default/1.chip_sw_gpio.3258408594
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95.91	0.01	95.01	0.00	94.01	0.00	95.26	0.00			94.86	0.00	97.55	0.00	98.77	0.02	/workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.534153107
95.91	0.01	95.01	0.00	94.01	0.00	95.29	0.02			94.86	0.00	97.55	0.00	98.77	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.316462604
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95.94	0.01	95.01	0.00	94.02	0.00	95.37	0.02			94.88	0.00	97.55	0.00	98.79	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.996649784
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95.96	0.01	95.01	0.00	94.03	0.00	95.39	0.00			94.88	0.00	97.55	0.00	98.88	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3048807934
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95.97	0.01	95.01	0.00	94.03	0.00	95.39	0.00			94.88	0.00	97.55	0.00	98.94	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.447618822
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95.98	0.01	95.01	0.00	94.03	0.00	95.39	0.00			94.88	0.00	97.55	0.00	99.02	0.01	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3636112713
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95.99	0.01	95.01	0.00	94.03	0.00	95.39	0.00			94.88	0.00	97.55	0.00	99.06	0.01	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.453591539
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95.99	0.01	95.01	0.00	94.03	0.00	95.39	0.00			94.88	0.00	97.55	0.00	99.08	0.01	/workspace/coverage/default/21.chip_sw_all_escalation_resets.2987287141
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96.00	0.01	95.01	0.00	94.03	0.00	95.39	0.00			94.88	0.00	97.55	0.00	99.11	0.01	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2313002090
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96.00	0.01	95.01	0.00	94.03	0.00	95.39	0.00			94.88	0.00	97.55	0.00	99.13	0.01	/workspace/coverage/default/25.chip_sw_all_escalation_resets.14143665
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96.00	0.01	95.01	0.00	94.03	0.00	95.39	0.00			94.88	0.00	97.55	0.00	99.15	0.01	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1226432746
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96.01	0.01	95.01	0.00	94.03	0.00	95.39	0.00			94.88	0.00	97.55	0.00	99.18	0.01	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.47086251
96.01	0.01	95.01	0.00	94.03	0.00	95.39	0.00			94.88	0.00	97.55	0.00	99.19	0.01	/workspace/coverage/default/29.chip_sw_all_escalation_resets.2948016020
96.01	0.01	95.01	0.00	94.03	0.00	95.39	0.00			94.88	0.00	97.55	0.00	99.20	0.01	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3774594737
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96.06	0.01	95.01	0.00	94.03	0.00	95.39	0.00			94.88	0.00	97.55	0.00	99.52	0.01	/workspace/coverage/default/87.chip_sw_all_escalation_resets.3746196089
96.07	0.01	95.01	0.00	94.03	0.00	95.39	0.00			94.88	0.00	97.55	0.00	99.53	0.01	/workspace/coverage/default/98.chip_sw_all_escalation_resets.589628128
96.07	0.01	95.01	0.00	94.03	0.00	95.40	0.01			94.88	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3763146846
96.07	0.01	95.01	0.00	94.04	0.01	95.40	0.00			94.88	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.3824028117
96.07	0.01	95.01	0.00	94.05	0.01	95.40	0.00			94.88	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_gpio.1577522591
96.07	0.01	95.01	0.00	94.06	0.01	95.40	0.00			94.88	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2858794087
96.07	0.01	95.01	0.00	94.07	0.01	95.40	0.00			94.88	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1656356959
96.08	0.01	95.01	0.00	94.08	0.01	95.40	0.00			94.88	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3697118173
96.08	0.01	95.01	0.00	94.10	0.01	95.40	0.00			94.88	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2596632514
96.08	0.01	95.01	0.00	94.10	0.00	95.41	0.01			94.88	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3408793251
96.08	0.01	95.01	0.00	94.10	0.00	95.42	0.01			94.88	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.717705576
96.08	0.01	95.01	0.00	94.10	0.00	95.42	0.00			94.89	0.01	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1707521352
96.08	0.01	95.01	0.00	94.10	0.00	95.42	0.00			94.90	0.01	97.55	0.00	99.53	0.00	/workspace/coverage/default/2.chip_tap_straps_dev.2089308688
96.09	0.01	95.01	0.00	94.10	0.01	95.42	0.00			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/12.xbar_stress_all.986619835
96.09	0.01	95.01	0.00	94.11	0.01	95.42	0.00			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.3596251257
96.09	0.01	95.01	0.00	94.12	0.01	95.42	0.00			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/23.chip_tl_errors.1730177842
96.09	0.01	95.01	0.00	94.12	0.01	95.42	0.00			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.790378364
96.09	0.01	95.01	0.00	94.13	0.01	95.42	0.00			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.3559274270
96.09	0.01	95.01	0.00	94.14	0.01	95.42	0.00			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.4000984562
96.09	0.01	95.01	0.00	94.14	0.01	95.42	0.00			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.3061842307
96.09	0.01	95.01	0.00	94.14	0.00	95.42	0.01			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1491347815
96.09	0.01	95.01	0.00	94.14	0.00	95.43	0.01			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3622684885
96.10	0.01	95.01	0.00	94.14	0.00	95.44	0.01			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.724769701
96.10	0.01	95.01	0.00	94.14	0.00	95.44	0.01			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.2912477051
96.10	0.01	95.02	0.01	94.14	0.00	95.45	0.01			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.4107705395
96.10	0.01	95.02	0.00	94.14	0.00	95.45	0.01			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.1585406409
96.10	0.01	95.02	0.00	94.14	0.00	95.45	0.01			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.4179175203
96.10	0.01	95.02	0.00	94.14	0.00	95.46	0.01			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.4038213221
96.10	0.01	95.02	0.00	94.14	0.00	95.46	0.01			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1742853814
96.10	0.01	95.02	0.00	94.14	0.00	95.47	0.01			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1778050075
96.10	0.01	95.02	0.00	94.15	0.01	95.47	0.00			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.2515441605
96.10	0.01	95.02	0.00	94.15	0.01	95.47	0.00			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2615078208
96.10	0.01	95.02	0.00	94.16	0.01	95.47	0.00			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.152508138
96.10	0.01	95.02	0.00	94.16	0.01	95.47	0.00			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.3575099620
96.10	0.01	95.02	0.00	94.16	0.01	95.47	0.00			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.3797465244
96.10	0.01	95.02	0.00	94.17	0.01	95.47	0.00			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.1032123336
96.11	0.01	95.02	0.00	94.17	0.01	95.47	0.00			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.982232224
96.11	0.01	95.02	0.00	94.17	0.01	95.47	0.00			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.1383981553
96.11	0.01	95.02	0.00	94.18	0.01	95.47	0.00			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1091531564
96.11	0.01	95.02	0.00	94.18	0.01	95.47	0.00			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.618523979
96.11	0.01	95.02	0.00	94.18	0.01	95.47	0.00			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1166713330
96.11	0.01	95.02	0.00	94.19	0.01	95.47	0.00			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2294851681
96.11	0.01	95.02	0.00	94.19	0.01	95.47	0.00			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1295227570
96.11	0.01	95.02	0.01	94.19	0.00	95.47	0.00			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.3474677625
96.11	0.01	95.02	0.00	94.19	0.00	95.47	0.01			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.231023334
96.11	0.01	95.02	0.00	94.19	0.00	95.47	0.01			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.2642338890
96.11	0.01	95.02	0.00	94.19	0.00	95.48	0.01			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.4281801738
96.11	0.01	95.02	0.00	94.19	0.00	95.48	0.01			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3375761896
96.11	0.01	95.02	0.00	94.19	0.00	95.48	0.01			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2721467535
96.11	0.01	95.02	0.00	94.19	0.00	95.48	0.01			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_power_idle_load.1617993649
96.11	0.01	95.02	0.00	94.19	0.00	95.49	0.01			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.3430056972
96.11	0.01	95.02	0.00	94.19	0.00	95.49	0.01			94.90	0.00	97.55	0.00	99.53	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.4073687985

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3577603773
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.142496960
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.2872495064
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.818425617
/workspace/coverage/cover_reg_top/0.chip_csr_rw.915818954
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1206632679
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2172475887
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.3668817489
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.385929860
/workspace/coverage/cover_reg_top/0.xbar_error_random.2591603317
/workspace/coverage/cover_reg_top/0.xbar_random.2040656744
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.1545274927
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3356574424
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1512736235
/workspace/coverage/cover_reg_top/0.xbar_same_source.3065622848
/workspace/coverage/cover_reg_top/0.xbar_smoke.28099840
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.1716311501
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2242693700
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3420362411
/workspace/coverage/cover_reg_top/0.xbar_stress_all.3690044056
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.673694242
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3532597839
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.3490232178
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3450663917
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.1358621790
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2104268987
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.2489512602
/workspace/coverage/cover_reg_top/1.chip_csr_rw.995642741
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.3902082982
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3338977347
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.587159500
/workspace/coverage/cover_reg_top/1.chip_tl_errors.1171942157
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.4069535931
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2685922487
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.919457957
/workspace/coverage/cover_reg_top/1.xbar_error_random.2465300321
/workspace/coverage/cover_reg_top/1.xbar_random.1520895065
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2931805434
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3358336818
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.2937475991
/workspace/coverage/cover_reg_top/1.xbar_same_source.583641750
/workspace/coverage/cover_reg_top/1.xbar_smoke.4020363061
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3345086290
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1957769540
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1296605488
/workspace/coverage/cover_reg_top/1.xbar_stress_all.1112633147
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.2630781016
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3700987186
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.2025516835
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.380675918
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.2276175379
/workspace/coverage/cover_reg_top/10.chip_csr_rw.3843917098
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1073644932
/workspace/coverage/cover_reg_top/10.chip_tl_errors.2788295859
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.2846628173
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1727424353
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.885849817
/workspace/coverage/cover_reg_top/10.xbar_error_random.1044730641
/workspace/coverage/cover_reg_top/10.xbar_random.993892249
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3700088283
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2676152377
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.3222343027
/workspace/coverage/cover_reg_top/10.xbar_same_source.3064038078
/workspace/coverage/cover_reg_top/10.xbar_smoke.1669124249
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.2105544215
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.751749778
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3316586962
/workspace/coverage/cover_reg_top/10.xbar_stress_all.1905144201
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.91288409
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3281991402
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2887666440
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.2239916504
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.3084807688
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2469149991
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.4016974182
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2605955694
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3156885931
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3900436059
/workspace/coverage/cover_reg_top/11.xbar_error_random.4029085327
/workspace/coverage/cover_reg_top/11.xbar_random.3314459035
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3280918487
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.1154975246
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2787976909
/workspace/coverage/cover_reg_top/11.xbar_same_source.198467554
/workspace/coverage/cover_reg_top/11.xbar_smoke.2318243566
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.3660790411
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2967337035
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.1583345765
/workspace/coverage/cover_reg_top/11.xbar_stress_all.2284504504
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2458796102
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1799348614
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.3062359832
/workspace/coverage/cover_reg_top/12.chip_csr_rw.1959101439
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.252313819
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.2844851770
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.196167379
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1534897119
/workspace/coverage/cover_reg_top/12.xbar_error_random.3155848340
/workspace/coverage/cover_reg_top/12.xbar_random.3835764524
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.2500932952
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3636449497
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3470432797
/workspace/coverage/cover_reg_top/12.xbar_same_source.1706380505
/workspace/coverage/cover_reg_top/12.xbar_smoke.3796617072
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3611755038
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.138990976
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2556841092
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.2203417702
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1159108791
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2798319445
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.4282281737
/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.2841776389
/workspace/coverage/cover_reg_top/13.chip_csr_rw.2441993595
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/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1219527638
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/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.562751352
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/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.4215512852
/workspace/coverage/default/38.chip_sw_all_escalation_resets.1414795503
/workspace/coverage/default/39.chip_sw_all_escalation_resets.234839507
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3012702626
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2206999720
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2536196646
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1274842955
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2147464425
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.4003489582
/workspace/coverage/default/4.chip_sw_uart_tx_rx.1147627896
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.789846194
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1581802362
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/workspace/coverage/default/4.chip_tap_straps_testunlock0.1394215189
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1618879454
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/workspace/coverage/default/45.chip_sw_all_escalation_resets.121396226
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/workspace/coverage/default/47.chip_sw_all_escalation_resets.1398129442
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.317591634
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/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.319976599
/workspace/coverage/default/49.chip_sw_all_escalation_resets.2458305478
/workspace/coverage/default/5.chip_sw_all_escalation_resets.3809060557
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.4088204385
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3835054670
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1321346292
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1482798186
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1975538174
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/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.234218637
/workspace/coverage/default/51.chip_sw_all_escalation_resets.2984087039
/workspace/coverage/default/52.chip_sw_all_escalation_resets.105640255
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2645520681
/workspace/coverage/default/53.chip_sw_all_escalation_resets.2527002935
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3290152134
/workspace/coverage/default/54.chip_sw_all_escalation_resets.1263403213
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3930960840
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.290176214
/workspace/coverage/default/56.chip_sw_all_escalation_resets.2774091774
/workspace/coverage/default/57.chip_sw_all_escalation_resets.2346502522
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.876660156
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1844100023
/workspace/coverage/default/59.chip_sw_all_escalation_resets.888967665
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3785373893
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2677177039
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.178646869
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1392918592
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2645122159
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2978222786
/workspace/coverage/default/61.chip_sw_all_escalation_resets.311781974
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3010251971
/workspace/coverage/default/62.chip_sw_all_escalation_resets.1541877464
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.682923996
/workspace/coverage/default/63.chip_sw_all_escalation_resets.3869257202
/workspace/coverage/default/64.chip_sw_all_escalation_resets.2391185040
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.919102154
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2123960253
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3155781427
/workspace/coverage/default/66.chip_sw_all_escalation_resets.1757445631
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2634344167
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3172255836
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.834176563
/workspace/coverage/default/69.chip_sw_all_escalation_resets.690376619
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.4040637374
/workspace/coverage/default/7.chip_sw_all_escalation_resets.3986305040
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1549801793
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1054225992
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.966010344
/workspace/coverage/default/70.chip_sw_all_escalation_resets.2412404009
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3990094082
/workspace/coverage/default/73.chip_sw_all_escalation_resets.2204844301
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1654124121
/workspace/coverage/default/74.chip_sw_all_escalation_resets.671910378
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3312464735
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1839130816
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.4268837481
/workspace/coverage/default/76.chip_sw_all_escalation_resets.3179566006
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3341331983
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.623948515
/workspace/coverage/default/78.chip_sw_all_escalation_resets.3734170013
/workspace/coverage/default/79.chip_sw_all_escalation_resets.2057112946
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3422216975
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2844154321
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.303751608
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2171769358
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2734199115
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3544942234
/workspace/coverage/default/81.chip_sw_all_escalation_resets.3218140874
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.673298581
/workspace/coverage/default/82.chip_sw_all_escalation_resets.3569617448
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.141511251
/workspace/coverage/default/83.chip_sw_all_escalation_resets.1158526618
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.937974515
/workspace/coverage/default/84.chip_sw_all_escalation_resets.3253001103
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.21717762
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2902892484
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1955419574
/workspace/coverage/default/86.chip_sw_all_escalation_resets.100316835
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3577316461
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1391683933
/workspace/coverage/default/88.chip_sw_all_escalation_resets.3837194015
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1260415568
/workspace/coverage/default/89.chip_sw_all_escalation_resets.437142444
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3016808110
/workspace/coverage/default/9.chip_sw_all_escalation_resets.1876081945
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3574607421
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.171545626
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.166722718
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2048189647
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2484331852
/workspace/coverage/default/92.chip_sw_all_escalation_resets.182245491
/workspace/coverage/default/94.chip_sw_all_escalation_resets.584619036
/workspace/coverage/default/96.chip_sw_all_escalation_resets.2323323886
/workspace/coverage/default/97.chip_sw_all_escalation_resets.403455886
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2494066540
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2977637779
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.2228013429
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1215687174
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.404429584
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.318785338
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1492223447
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2165061556
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.98159144

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Total test records in report: 2935

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/1.chip_sw_aon_timer_irq.4112999210			Jul 26 07:48:44 PM PDT 24	Jul 26 07:55:27 PM PDT 24	4442548840 ps
T2	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2475960581			Jul 26 07:42:50 PM PDT 24	Jul 26 07:50:30 PM PDT 24	7479988452 ps
T3	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3687811340			Jul 26 07:48:49 PM PDT 24	Jul 26 08:24:29 PM PDT 24	8612392932 ps
T6	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.699613592			Jul 26 07:47:55 PM PDT 24	Jul 26 08:50:24 PM PDT 24	14249807774 ps
T21	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3763146846			Jul 26 07:44:28 PM PDT 24	Jul 26 07:50:15 PM PDT 24	3674996308 ps
T4	/workspace/coverage/default/1.chip_sival_flash_info_access.2656110986			Jul 26 07:46:57 PM PDT 24	Jul 26 07:52:19 PM PDT 24	3450466340 ps
T5	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.921172117			Jul 26 07:46:08 PM PDT 24	Jul 26 08:09:06 PM PDT 24	10638661414 ps
T7	/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.3971021027			Jul 26 08:09:42 PM PDT 24	Jul 26 08:30:36 PM PDT 24	11900776490 ps
T86	/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.927794496			Jul 26 08:14:47 PM PDT 24	Jul 26 08:22:32 PM PDT 24	3709513326 ps
T87	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3143114559			Jul 26 07:43:07 PM PDT 24	Jul 26 08:11:52 PM PDT 24	7153857622 ps
T46	/workspace/coverage/default/0.chip_tap_straps_rma.2912477051			Jul 26 07:46:04 PM PDT 24	Jul 26 07:48:50 PM PDT 24	2666622337 ps
T41	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1228238141			Jul 26 07:50:00 PM PDT 24	Jul 26 09:01:57 PM PDT 24	14945814511 ps
T408	/workspace/coverage/default/1.chip_sw_hmac_oneshot.1668055447			Jul 26 07:53:41 PM PDT 24	Jul 26 07:58:06 PM PDT 24	3184255120 ps
T171	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2840329636			Jul 26 08:11:06 PM PDT 24	Jul 26 08:17:32 PM PDT 24	3347572364 ps
T376	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1517453204			Jul 26 08:11:42 PM PDT 24	Jul 26 08:18:16 PM PDT 24	3904754272 ps
T130	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1674469914			Jul 26 07:49:15 PM PDT 24	Jul 26 09:06:18 PM PDT 24	17638844466 ps
T59	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1777985909			Jul 26 08:06:47 PM PDT 24	Jul 26 08:18:26 PM PDT 24	6017681144 ps
T187	/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2374319826			Jul 26 07:46:05 PM PDT 24	Jul 26 07:53:27 PM PDT 24	3472649804 ps
T44	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.881992644			Jul 26 08:00:05 PM PDT 24	Jul 26 08:04:17 PM PDT 24	4170685947 ps
T117	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.508799142			Jul 26 07:53:33 PM PDT 24	Jul 26 08:04:22 PM PDT 24	5268178636 ps
T118	/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3781753476			Jul 26 08:04:00 PM PDT 24	Jul 26 08:25:52 PM PDT 24	4996906820 ps
T191	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1778050075			Jul 26 07:42:28 PM PDT 24	Jul 26 07:48:16 PM PDT 24	4490168245 ps
T11	/workspace/coverage/default/1.chip_sw_spi_device_pass_through.1201932672			Jul 26 07:49:06 PM PDT 24	Jul 26 08:03:35 PM PDT 24	8274525486 ps
T43	/workspace/coverage/default/1.rom_e2e_asm_init_dev.3856523325			Jul 26 07:58:33 PM PDT 24	Jul 26 08:58:44 PM PDT 24	15309393896 ps
T230	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.2003638132			Jul 26 08:00:23 PM PDT 24	Jul 26 08:13:10 PM PDT 24	4416059994 ps
T119	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3444053870			Jul 26 07:46:33 PM PDT 24	Jul 26 07:56:52 PM PDT 24	3961209057 ps
T66	/workspace/coverage/default/0.chip_tap_straps_dev.2056251125			Jul 26 07:45:01 PM PDT 24	Jul 26 08:07:46 PM PDT 24	11392711154 ps
T272	/workspace/coverage/default/2.chip_sw_aon_timer_irq.3445749464			Jul 26 07:59:46 PM PDT 24	Jul 26 08:07:53 PM PDT 24	4033817800 ps
T131	/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1549801793			Jul 26 08:06:30 PM PDT 24	Jul 26 09:53:02 PM PDT 24	30254979656 ps
T132	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2582330608			Jul 26 08:03:05 PM PDT 24	Jul 26 08:40:17 PM PDT 24	9713031024 ps
T67	/workspace/coverage/default/3.chip_tap_straps_dev.625819585			Jul 26 08:04:33 PM PDT 24	Jul 26 08:37:30 PM PDT 24	18030290346 ps
T45	/workspace/coverage/default/1.chip_tap_straps_testunlock0.3083274879			Jul 26 07:51:51 PM PDT 24	Jul 26 08:03:17 PM PDT 24	7780564154 ps
T154	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3462395759			Jul 26 08:06:06 PM PDT 24	Jul 26 08:39:16 PM PDT 24	8410707856 ps
T161	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.746477708			Jul 26 07:47:38 PM PDT 24	Jul 26 08:24:03 PM PDT 24	9297585856 ps
T734	/workspace/coverage/default/1.chip_sw_aes_enc.2230384065			Jul 26 07:46:03 PM PDT 24	Jul 26 07:49:28 PM PDT 24	2772336884 ps
T60	/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3986653193			Jul 26 07:46:17 PM PDT 24	Jul 26 07:56:52 PM PDT 24	4756849420 ps
T186	/workspace/coverage/default/0.rom_e2e_static_critical.1583976362			Jul 26 07:49:39 PM PDT 24	Jul 26 09:02:21 PM PDT 24	17086582706 ps
T758	/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3650891417			Jul 26 07:43:18 PM PDT 24	Jul 26 07:50:55 PM PDT 24	4769798250 ps
T275	/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1898571631			Jul 26 07:43:00 PM PDT 24	Jul 26 08:01:21 PM PDT 24	5469891962 ps
T228	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1102772985			Jul 26 07:42:35 PM PDT 24	Jul 26 07:51:16 PM PDT 24	3773528806 ps
T14	/workspace/coverage/default/0.chip_sw_gpio_smoketest.2016930232			Jul 26 07:56:18 PM PDT 24	Jul 26 08:02:47 PM PDT 24	3108355528 ps
T113	/workspace/coverage/default/0.chip_sw_power_sleep_load.4089601418			Jul 26 07:44:53 PM PDT 24	Jul 26 07:55:44 PM PDT 24	10560499336 ps
T17	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.412098686			Jul 26 07:46:00 PM PDT 24	Jul 26 08:24:37 PM PDT 24	25296867722 ps
T101	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.2422529841			Jul 26 07:46:54 PM PDT 24	Jul 26 08:35:10 PM PDT 24	12427008251 ps
T102	/workspace/coverage/default/0.chip_sw_uart_tx_rx.3512263128			Jul 26 07:42:35 PM PDT 24	Jul 26 07:53:14 PM PDT 24	4076650644 ps
T103	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1344416036			Jul 26 07:49:36 PM PDT 24	Jul 26 08:11:16 PM PDT 24	6439985587 ps
T104	/workspace/coverage/default/16.chip_sw_all_escalation_resets.4020863585			Jul 26 08:09:31 PM PDT 24	Jul 26 08:18:34 PM PDT 24	4463374722 ps
T105	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.1618879454			Jul 26 08:12:34 PM PDT 24	Jul 26 08:19:29 PM PDT 24	4087862648 ps
T106	/workspace/coverage/default/2.chip_sw_example_rom.3992283420			Jul 26 07:55:15 PM PDT 24	Jul 26 07:57:38 PM PDT 24	2628791120 ps
T107	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.781948527			Jul 26 08:18:14 PM PDT 24	Jul 26 08:25:27 PM PDT 24	3553540060 ps
T108	/workspace/coverage/default/1.chip_sw_plic_sw_irq.3965363206			Jul 26 07:49:55 PM PDT 24	Jul 26 07:54:59 PM PDT 24	3037003484 ps
T109	/workspace/coverage/default/0.chip_sw_power_idle_load.1617993649			Jul 26 07:55:51 PM PDT 24	Jul 26 08:06:32 PM PDT 24	4571469876 ps
T447	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.4215512852			Jul 26 08:18:19 PM PDT 24	Jul 26 08:25:45 PM PDT 24	3846784480 ps
T916	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3740926815			Jul 26 07:58:41 PM PDT 24	Jul 26 08:04:02 PM PDT 24	2646777656 ps
T229	/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1413713721			Jul 26 08:10:14 PM PDT 24	Jul 26 08:37:33 PM PDT 24	8163195696 ps
T166	/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.126070971			Jul 26 07:43:02 PM PDT 24	Jul 26 11:22:02 PM PDT 24	255322651832 ps
T18	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2604472042			Jul 26 08:03:08 PM PDT 24	Jul 26 08:36:13 PM PDT 24	25123020278 ps
T365	/workspace/coverage/default/53.chip_sw_all_escalation_resets.2527002935			Jul 26 08:11:58 PM PDT 24	Jul 26 08:24:06 PM PDT 24	5527005700 ps
T263	/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3942268072			Jul 26 07:51:01 PM PDT 24	Jul 26 08:14:12 PM PDT 24	9417425316 ps
T184	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.1523308141			Jul 26 08:05:50 PM PDT 24	Jul 26 08:43:35 PM PDT 24	18800704851 ps
T375	/workspace/coverage/default/32.chip_sw_all_escalation_resets.3729780848			Jul 26 08:11:09 PM PDT 24	Jul 26 08:23:51 PM PDT 24	6104465464 ps
T700	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1607793940			Jul 26 07:47:09 PM PDT 24	Jul 26 07:55:34 PM PDT 24	7359523564 ps
T705	/workspace/coverage/default/98.chip_sw_all_escalation_resets.589628128			Jul 26 08:15:23 PM PDT 24	Jul 26 08:24:27 PM PDT 24	5113736888 ps
T759	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3673182854			Jul 26 08:12:12 PM PDT 24	Jul 26 08:18:52 PM PDT 24	3800858418 ps
T78	/workspace/coverage/default/93.chip_sw_all_escalation_resets.865951925			Jul 26 08:14:59 PM PDT 24	Jul 26 08:26:56 PM PDT 24	6607913176 ps
T42	/workspace/coverage/default/2.rom_e2e_shutdown_output.1168013523			Jul 26 08:09:45 PM PDT 24	Jul 26 09:10:57 PM PDT 24	27318747608 ps
T91	/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.4286311336			Jul 26 07:44:17 PM PDT 24	Jul 26 07:50:04 PM PDT 24	3749508608 ps
T92	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.319976599			Jul 26 08:11:54 PM PDT 24	Jul 26 08:21:22 PM PDT 24	3987184032 ps
T93	/workspace/coverage/default/2.chip_sw_flash_init.781710632			Jul 26 08:02:06 PM PDT 24	Jul 26 08:42:09 PM PDT 24	19782896751 ps
T63	/workspace/coverage/default/4.chip_tap_straps_testunlock0.1394215189			Jul 26 08:05:21 PM PDT 24	Jul 26 08:09:50 PM PDT 24	3437068474 ps
T94	/workspace/coverage/default/6.chip_sw_all_escalation_resets.606498358			Jul 26 08:08:10 PM PDT 24	Jul 26 08:18:39 PM PDT 24	5230122536 ps
T95	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.438895267			Jul 26 07:53:16 PM PDT 24	Jul 26 09:57:38 PM PDT 24	23801022286 ps
T96	/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1123409399			Jul 26 07:46:20 PM PDT 24	Jul 26 07:52:11 PM PDT 24	5233900600 ps
T58	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2927319818			Jul 26 07:45:48 PM PDT 24	Jul 26 08:31:13 PM PDT 24	33545188860 ps
T227	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.780804010			Jul 26 07:49:08 PM PDT 24	Jul 26 07:59:16 PM PDT 24	3914072292 ps
T736	/workspace/coverage/default/2.chip_sw_power_sleep_load.3879698306			Jul 26 08:03:43 PM PDT 24	Jul 26 08:15:23 PM PDT 24	10259780340 ps
T260	/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.242487370			Jul 26 07:50:51 PM PDT 24	Jul 26 08:03:28 PM PDT 24	7010254714 ps
T279	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2691844080			Jul 26 07:45:58 PM PDT 24	Jul 26 08:24:23 PM PDT 24	26594186968 ps
T195	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1043553946			Jul 26 07:53:48 PM PDT 24	Jul 26 07:57:28 PM PDT 24	2568925041 ps
T198	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1557538247			Jul 26 07:45:33 PM PDT 24	Jul 26 07:53:56 PM PDT 24	4019253576 ps
T15	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.3602123353			Jul 26 07:48:19 PM PDT 24	Jul 26 07:52:41 PM PDT 24	2888164184 ps
T234	/workspace/coverage/default/28.chip_sw_all_escalation_resets.727895027			Jul 26 08:18:01 PM PDT 24	Jul 26 08:27:40 PM PDT 24	4610827616 ps
T185	/workspace/coverage/default/0.chip_sw_flash_init.2772051404			Jul 26 07:41:33 PM PDT 24	Jul 26 08:12:25 PM PDT 24	21543491830 ps
T123	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3203322415			Jul 26 07:44:57 PM PDT 24	Jul 26 07:53:43 PM PDT 24	3713973863 ps
T280	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1131677648			Jul 26 07:59:41 PM PDT 24	Jul 26 08:07:45 PM PDT 24	5220291830 ps
T281	/workspace/coverage/default/62.chip_sw_all_escalation_resets.1541877464			Jul 26 08:14:38 PM PDT 24	Jul 26 08:27:52 PM PDT 24	5478789120 ps
T12	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3540377513			Jul 26 07:44:02 PM PDT 24	Jul 26 07:54:07 PM PDT 24	4248085527 ps
T316	/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.889953765			Jul 26 08:02:55 PM PDT 24	Jul 26 08:11:45 PM PDT 24	4129527576 ps
T429	/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1606438058			Jul 26 08:05:26 PM PDT 24	Jul 26 08:11:32 PM PDT 24	2963493656 ps
T121	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1463590049			Jul 26 07:58:35 PM PDT 24	Jul 26 08:00:32 PM PDT 24	2426010277 ps
T16	/workspace/coverage/default/2.chip_sw_gpio_smoketest.1723484807			Jul 26 08:06:19 PM PDT 24	Jul 26 08:12:01 PM PDT 24	2610439535 ps
T917	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2471408141			Jul 26 07:46:00 PM PDT 24	Jul 26 08:07:22 PM PDT 24	15935846309 ps
T114	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.4179175203			Jul 26 07:46:11 PM PDT 24	Jul 27 02:02:10 AM PDT 24	154639358386 ps
T361	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.142916022			Jul 26 07:50:10 PM PDT 24	Jul 26 07:56:25 PM PDT 24	3534973664 ps
T199	/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1745958763			Jul 26 08:01:46 PM PDT 24	Jul 26 08:12:38 PM PDT 24	5012257160 ps
T735	/workspace/coverage/default/1.chip_sw_edn_sw_mode.247779938			Jul 26 07:51:55 PM PDT 24	Jul 26 08:30:21 PM PDT 24	9358724168 ps
T265	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3498545560			Jul 26 08:12:50 PM PDT 24	Jul 26 08:22:53 PM PDT 24	4628875304 ps
T124	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.934775907			Jul 26 08:04:18 PM PDT 24	Jul 26 08:18:54 PM PDT 24	4652385212 ps
T168	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1656356959			Jul 26 07:45:33 PM PDT 24	Jul 26 08:14:19 PM PDT 24	13093388390 ps
T308	/workspace/coverage/default/1.rom_e2e_static_critical.249986306			Jul 26 07:58:58 PM PDT 24	Jul 26 09:08:00 PM PDT 24	17074120340 ps
T309	/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.303751608			Jul 26 08:07:37 PM PDT 24	Jul 26 09:09:35 PM PDT 24	16159372440 ps
T310	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3016808110			Jul 26 08:07:18 PM PDT 24	Jul 26 08:14:59 PM PDT 24	4262247760 ps
T311	/workspace/coverage/default/11.chip_sw_all_escalation_resets.3947198114			Jul 26 08:08:59 PM PDT 24	Jul 26 08:20:53 PM PDT 24	4654995848 ps
T312	/workspace/coverage/default/0.chip_sw_pattgen_ios.618523979			Jul 26 07:42:08 PM PDT 24	Jul 26 07:46:14 PM PDT 24	3337133288 ps
T125	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2876029864			Jul 26 08:04:33 PM PDT 24	Jul 26 08:16:33 PM PDT 24	4688038940 ps
T261	/workspace/coverage/default/22.chip_sw_all_escalation_resets.366268269			Jul 26 08:09:23 PM PDT 24	Jul 26 08:19:53 PM PDT 24	4884296740 ps
T406	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2962661317			Jul 26 07:54:07 PM PDT 24	Jul 26 09:42:53 PM PDT 24	24877763806 ps
T353	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.1024201505			Jul 26 07:50:14 PM PDT 24	Jul 26 07:54:42 PM PDT 24	2365932112 ps
T918	/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.2485291935			Jul 26 07:47:22 PM PDT 24	Jul 26 07:54:11 PM PDT 24	5855627132 ps
T750	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.919102154			Jul 26 08:14:10 PM PDT 24	Jul 26 08:20:00 PM PDT 24	3245563814 ps
T411	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3702669788			Jul 26 07:51:26 PM PDT 24	Jul 26 09:13:51 PM PDT 24	18087001598 ps
T85	/workspace/coverage/default/0.chip_sw_inject_scramble_seed.1151189092			Jul 26 07:44:09 PM PDT 24	Jul 26 11:24:41 PM PDT 24	66048027300 ps
T440	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3979689061			Jul 26 07:55:21 PM PDT 24	Jul 26 07:58:47 PM PDT 24	2883813184 ps
T373	/workspace/coverage/default/23.chip_sw_all_escalation_resets.2971488791			Jul 26 08:09:29 PM PDT 24	Jul 26 08:19:34 PM PDT 24	4560415580 ps
T19	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.982313941			Jul 26 08:03:30 PM PDT 24	Jul 26 08:10:45 PM PDT 24	7046888776 ps
T395	/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2897859680			Jul 26 07:58:40 PM PDT 24	Jul 26 08:01:55 PM PDT 24	3034023400 ps
T120	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3718154338			Jul 26 07:44:13 PM PDT 24	Jul 26 08:21:37 PM PDT 24	11548255326 ps
T919	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2757582994			Jul 26 07:48:17 PM PDT 24	Jul 26 07:52:00 PM PDT 24	2408308456 ps
T920	/workspace/coverage/default/2.chip_sw_clkmgr_jitter.434085857			Jul 26 08:03:59 PM PDT 24	Jul 26 08:08:08 PM PDT 24	2784172488 ps
T407	/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3080560802			Jul 26 07:58:05 PM PDT 24	Jul 26 09:02:08 PM PDT 24	15929593776 ps
T921	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1189115287			Jul 26 07:49:43 PM PDT 24	Jul 26 08:46:21 PM PDT 24	10954357816 ps
T286	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1347825528			Jul 26 07:49:40 PM PDT 24	Jul 26 07:58:59 PM PDT 24	8259938117 ps
T162	/workspace/coverage/default/0.chip_plic_all_irqs_10.3669978527			Jul 26 07:48:07 PM PDT 24	Jul 26 07:58:11 PM PDT 24	3625148410 ps
T448	/workspace/coverage/default/0.chip_sw_kmac_idle.3114991423			Jul 26 07:46:00 PM PDT 24	Jul 26 07:51:08 PM PDT 24	3211727088 ps
T922	/workspace/coverage/default/1.chip_sw_example_rom.3312709311			Jul 26 07:45:08 PM PDT 24	Jul 26 07:47:35 PM PDT 24	3201860654 ps
T923	/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1175037597			Jul 26 08:01:11 PM PDT 24	Jul 26 08:14:15 PM PDT 24	5385035866 ps
T181	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1742853814			Jul 26 07:46:52 PM PDT 24	Jul 26 07:53:48 PM PDT 24	3991083000 ps
T231	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1392918592			Jul 26 08:09:46 PM PDT 24	Jul 26 08:18:00 PM PDT 24	3466347038 ps
T219	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.649108097			Jul 26 07:49:21 PM PDT 24	Jul 26 07:54:46 PM PDT 24	2770142107 ps
T238	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1667063562			Jul 26 08:07:58 PM PDT 24	Jul 26 08:33:52 PM PDT 24	8184510656 ps
T924	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1303885196			Jul 26 07:48:53 PM PDT 24	Jul 26 08:55:14 PM PDT 24	15526569658 ps
T232	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1411990641			Jul 26 08:07:25 PM PDT 24	Jul 26 08:31:07 PM PDT 24	8519181267 ps
T196	/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.2635485969			Jul 26 08:05:12 PM PDT 24	Jul 26 08:10:39 PM PDT 24	2831532445 ps
T925	/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.1021344512			Jul 26 07:55:22 PM PDT 24	Jul 26 08:01:40 PM PDT 24	3490695128 ps
T237	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1302298419			Jul 26 07:44:43 PM PDT 24	Jul 26 08:04:10 PM PDT 24	6998156372 ps
T174	/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3350879565			Jul 26 08:13:10 PM PDT 24	Jul 26 08:21:29 PM PDT 24	4306141784 ps
T926	/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3244086606			Jul 26 08:03:10 PM PDT 24	Jul 26 08:11:30 PM PDT 24	5340220352 ps
T68	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3567808658			Jul 26 07:41:37 PM PDT 24	Jul 26 07:48:18 PM PDT 24	3383369560 ps
T79	/workspace/coverage/default/90.chip_sw_all_escalation_resets.2048189647			Jul 26 08:15:36 PM PDT 24	Jul 26 08:25:23 PM PDT 24	5429233240 ps
T239	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3282631117			Jul 26 07:43:55 PM PDT 24	Jul 26 08:07:42 PM PDT 24	7733884678 ps
T820	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.876660156			Jul 26 08:13:10 PM PDT 24	Jul 26 08:20:18 PM PDT 24	3437334020 ps
T369	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2303557051			Jul 26 07:56:10 PM PDT 24	Jul 26 08:05:22 PM PDT 24	4358069912 ps
T197	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1956630318			Jul 26 07:45:18 PM PDT 24	Jul 26 07:49:38 PM PDT 24	2813795216 ps
T415	/workspace/coverage/default/48.chip_sw_all_escalation_resets.1759102360			Jul 26 08:11:31 PM PDT 24	Jul 26 08:23:12 PM PDT 24	6431414056 ps
T416	/workspace/coverage/default/36.chip_sw_all_escalation_resets.1104465990			Jul 26 08:10:06 PM PDT 24	Jul 26 08:22:47 PM PDT 24	5031939600 ps
T360	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.274211876			Jul 26 07:42:49 PM PDT 24	Jul 26 07:52:17 PM PDT 24	3552830592 ps
T417	/workspace/coverage/default/85.chip_sw_all_escalation_resets.2902892484			Jul 26 08:16:24 PM PDT 24	Jul 26 08:26:52 PM PDT 24	4948303780 ps
T418	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1966400493			Jul 26 08:02:21 PM PDT 24	Jul 26 08:22:05 PM PDT 24	5632829850 ps
T419	/workspace/coverage/default/0.rom_e2e_self_hash.3875539591			Jul 26 07:54:30 PM PDT 24	Jul 26 09:36:39 PM PDT 24	26261374286 ps
T258	/workspace/coverage/default/3.chip_sw_data_integrity_escalation.3256353253			Jul 26 08:05:15 PM PDT 24	Jul 26 08:19:30 PM PDT 24	5572547600 ps
T297	/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.2098646257			Jul 26 08:08:47 PM PDT 24	Jul 26 08:54:52 PM PDT 24	12998769546 ps
T298	/workspace/coverage/default/0.chip_sw_aes_entropy.1237358805			Jul 26 07:43:07 PM PDT 24	Jul 26 07:47:46 PM PDT 24	2598034358 ps
T299	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3034595593			Jul 26 07:46:46 PM PDT 24	Jul 26 07:50:20 PM PDT 24	2333295140 ps
T300	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3166339305			Jul 26 07:48:13 PM PDT 24	Jul 26 08:57:46 PM PDT 24	15539966440 ps
T240	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2141820226			Jul 26 07:45:05 PM PDT 24	Jul 26 08:26:34 PM PDT 24	10579187462 ps
T301	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1166713330			Jul 26 07:49:34 PM PDT 24	Jul 26 07:55:13 PM PDT 24	3182100296 ps
T302	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.4184473602			Jul 26 08:08:52 PM PDT 24	Jul 26 08:18:05 PM PDT 24	3610886520 ps
T303	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4032607140			Jul 26 07:45:38 PM PDT 24	Jul 26 08:07:12 PM PDT 24	12779393412 ps
T35	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2901609682			Jul 26 07:58:30 PM PDT 24	Jul 26 08:04:57 PM PDT 24	5601031506 ps
T382	/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3952024375			Jul 26 07:53:02 PM PDT 24	Jul 26 08:00:07 PM PDT 24	5506376814 ps
T241	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4288266268			Jul 26 07:55:39 PM PDT 24	Jul 26 08:12:30 PM PDT 24	6638263219 ps
T266	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3010251971			Jul 26 08:12:51 PM PDT 24	Jul 26 08:21:30 PM PDT 24	4218109804 ps
T259	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3252029974			Jul 26 07:46:00 PM PDT 24	Jul 26 07:55:35 PM PDT 24	3872609560 ps
T744	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1051906306			Jul 26 07:52:12 PM PDT 24	Jul 26 07:59:55 PM PDT 24	6537566462 ps
T927	/workspace/coverage/default/0.chip_tap_straps_prod.1763200632			Jul 26 07:44:49 PM PDT 24	Jul 26 07:58:01 PM PDT 24	9610874077 ps
T760	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.834176563			Jul 26 08:15:19 PM PDT 24	Jul 26 08:23:20 PM PDT 24	3807988452 ps
T928	/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2861826357			Jul 26 07:47:44 PM PDT 24	Jul 26 07:53:51 PM PDT 24	3287376274 ps
T929	/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3452779970			Jul 26 07:45:47 PM PDT 24	Jul 26 07:54:19 PM PDT 24	4805382166 ps
T930	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1400667543			Jul 26 07:48:11 PM PDT 24	Jul 26 08:07:49 PM PDT 24	5685967936 ps
T370	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2213590336			Jul 26 08:07:09 PM PDT 24	Jul 26 08:19:37 PM PDT 24	4024323336 ps
T242	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.465580916			Jul 26 08:09:53 PM PDT 24	Jul 26 08:16:19 PM PDT 24	4066728528 ps
T348	/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.166722718			Jul 26 08:07:09 PM PDT 24	Jul 26 08:17:46 PM PDT 24	4295238840 ps
T428	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.784436922			Jul 26 07:50:39 PM PDT 24	Jul 26 08:13:52 PM PDT 24	5780616894 ps
T765	/workspace/coverage/default/67.chip_sw_all_escalation_resets.27937137			Jul 26 08:13:07 PM PDT 24	Jul 26 08:22:45 PM PDT 24	4865820504 ps
T931	/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.4025414706			Jul 26 07:47:45 PM PDT 24	Jul 26 07:51:25 PM PDT 24	2571287784 ps
T932	/workspace/coverage/default/2.chip_sw_example_flash.378036508			Jul 26 07:55:00 PM PDT 24	Jul 26 07:58:18 PM PDT 24	2426043940 ps
T933	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1732523039			Jul 26 07:59:01 PM PDT 24	Jul 26 08:42:18 PM PDT 24	21509486920 ps
T334	/workspace/coverage/default/2.chip_plic_all_irqs_0.1972172357			Jul 26 08:02:05 PM PDT 24	Jul 26 08:24:38 PM PDT 24	6703122808 ps
T172	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.317591634			Jul 26 08:11:53 PM PDT 24	Jul 26 08:17:42 PM PDT 24	3230388496 ps
T934	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3323596229			Jul 26 08:03:02 PM PDT 24	Jul 26 08:06:34 PM PDT 24	2426954568 ps
T138	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3051921995			Jul 26 08:03:22 PM PDT 24	Jul 26 08:15:47 PM PDT 24	5577381250 ps
T935	/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2068998409			Jul 26 07:42:55 PM PDT 24	Jul 26 07:46:38 PM PDT 24	2951295080 ps
T936	/workspace/coverage/default/0.chip_sw_edn_sw_mode.3604272909			Jul 26 07:45:35 PM PDT 24	Jul 26 08:23:24 PM PDT 24	9344087688 ps
T366	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2344661530			Jul 26 08:01:38 PM PDT 24	Jul 26 08:10:51 PM PDT 24	18900677822 ps
T533	/workspace/coverage/default/0.chip_sw_all_escalation_resets.417844595			Jul 26 07:41:49 PM PDT 24	Jul 26 07:53:21 PM PDT 24	4787242300 ps
T122	/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1897705928			Jul 26 07:58:18 PM PDT 24	Jul 26 08:11:27 PM PDT 24	8989244942 ps
T270	/workspace/coverage/default/0.chip_sw_rv_timer_irq.4224537562			Jul 26 07:45:11 PM PDT 24	Jul 26 07:50:13 PM PDT 24	2607555844 ps
T374	/workspace/coverage/default/33.chip_sw_all_escalation_resets.3897942902			Jul 26 08:12:07 PM PDT 24	Jul 26 08:22:19 PM PDT 24	4057524910 ps
T937	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.278604328			Jul 26 07:44:20 PM PDT 24	Jul 26 07:50:48 PM PDT 24	6143662096 ps
T763	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1181621429			Jul 26 08:13:47 PM PDT 24	Jul 26 08:20:30 PM PDT 24	4229244272 ps
T938	/workspace/coverage/default/1.chip_sw_hmac_enc_idle.2922844042			Jul 26 07:50:15 PM PDT 24	Jul 26 07:55:36 PM PDT 24	3067930968 ps
T147	/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3463711708			Jul 26 08:04:48 PM PDT 24	Jul 26 08:09:11 PM PDT 24	3545723066 ps
T534	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.917674398			Jul 26 07:50:22 PM PDT 24	Jul 26 07:54:44 PM PDT 24	3477370900 ps
T939	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.829482839			Jul 26 08:05:02 PM PDT 24	Jul 26 08:10:59 PM PDT 24	3036499924 ps
T940	/workspace/coverage/default/1.chip_tap_straps_rma.3168167377			Jul 26 07:52:32 PM PDT 24	Jul 26 08:02:42 PM PDT 24	5723336130 ps
T941	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.605169345			Jul 26 08:00:52 PM PDT 24	Jul 26 09:19:00 PM PDT 24	15723934612 ps
T262	/workspace/coverage/default/87.chip_sw_all_escalation_resets.3746196089			Jul 26 08:14:24 PM PDT 24	Jul 26 08:24:51 PM PDT 24	5059722058 ps
T337	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1217203412			Jul 26 07:48:02 PM PDT 24	Jul 26 07:58:05 PM PDT 24	3912652500 ps
T362	/workspace/coverage/default/4.chip_sw_uart_tx_rx.1147627896			Jul 26 08:06:58 PM PDT 24	Jul 26 08:17:31 PM PDT 24	4737336142 ps
T133	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3368787028			Jul 26 07:50:06 PM PDT 24	Jul 26 07:57:39 PM PDT 24	5067790584 ps
T751	/workspace/coverage/default/46.chip_sw_all_escalation_resets.2660920853			Jul 26 08:14:27 PM PDT 24	Jul 26 08:22:35 PM PDT 24	4428597666 ps
T449	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.3991330736			Jul 26 07:44:12 PM PDT 24	Jul 26 07:50:25 PM PDT 24	3443018994 ps
T942	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1252489822			Jul 26 07:59:44 PM PDT 24	Jul 26 08:57:43 PM PDT 24	51306183992 ps
T341	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1789670171			Jul 26 07:43:14 PM PDT 24	Jul 26 07:56:14 PM PDT 24	4968392280 ps
T349	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3657477077			Jul 26 07:57:37 PM PDT 24	Jul 26 08:06:00 PM PDT 24	4625332792 ps
T371	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3360985996			Jul 26 07:46:37 PM PDT 24	Jul 26 07:59:15 PM PDT 24	4610240060 ps
T739	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2732703321			Jul 26 08:12:30 PM PDT 24	Jul 26 08:19:18 PM PDT 24	3260455600 ps
T178	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.717705576			Jul 26 07:48:25 PM PDT 24	Jul 26 09:25:04 PM PDT 24	48510728173 ps
T127	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.157495116			Jul 26 07:44:52 PM PDT 24	Jul 26 07:57:31 PM PDT 24	5302898122 ps
T740	/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.4268837481			Jul 26 08:13:45 PM PDT 24	Jul 26 08:21:17 PM PDT 24	3944365890 ps
T128	/workspace/coverage/default/2.chip_sw_edn_boot_mode.2920405475			Jul 26 07:59:48 PM PDT 24	Jul 26 08:09:56 PM PDT 24	2874365050 ps
T943	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.750155383			Jul 26 07:42:33 PM PDT 24	Jul 26 07:47:02 PM PDT 24	2910193644 ps
T944	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1399244646			Jul 26 07:49:36 PM PDT 24	Jul 26 07:54:05 PM PDT 24	3359501567 ps
T738	/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2839203488			Jul 26 07:44:34 PM PDT 24	Jul 26 07:54:23 PM PDT 24	5577641282 ps
T271	/workspace/coverage/default/2.chip_sw_rv_timer_irq.1899485423			Jul 26 08:00:23 PM PDT 24	Jul 26 08:07:01 PM PDT 24	3393211746 ps
T691	/workspace/coverage/default/1.chip_sw_aes_masking_off.2613342960			Jul 26 07:49:23 PM PDT 24	Jul 26 07:56:34 PM PDT 24	3684450327 ps
T354	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.693405611			Jul 26 07:42:43 PM PDT 24	Jul 26 07:54:13 PM PDT 24	4495341260 ps
T945	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1603263907			Jul 26 07:42:46 PM PDT 24	Jul 26 07:55:20 PM PDT 24	4567301866 ps
T946	/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.420425699			Jul 26 08:02:46 PM PDT 24	Jul 26 08:10:57 PM PDT 24	4725136744 ps
T80	/workspace/coverage/default/73.chip_sw_all_escalation_resets.2204844301			Jul 26 08:14:06 PM PDT 24	Jul 26 08:22:24 PM PDT 24	4222413330 ps
T20	/workspace/coverage/default/0.chip_sw_usbdev_config_host.3924754685			Jul 26 07:44:59 PM PDT 24	Jul 26 08:17:02 PM PDT 24	7627957090 ps
T947	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.1507736455			Jul 26 07:43:08 PM PDT 24	Jul 26 07:54:40 PM PDT 24	5639479410 ps
T335	/workspace/coverage/default/1.chip_plic_all_irqs_20.3460190826			Jul 26 07:53:09 PM PDT 24	Jul 26 08:08:40 PM PDT 24	5188005638 ps
T821	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3172255836			Jul 26 08:15:01 PM PDT 24	Jul 26 08:20:51 PM PDT 24	4158525620 ps
T245	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.851001071			Jul 26 07:45:26 PM PDT 24	Jul 26 07:52:22 PM PDT 24	4980997459 ps
T948	/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.487261086			Jul 26 08:09:24 PM PDT 24	Jul 26 08:20:13 PM PDT 24	3675402736 ps
T84	/workspace/coverage/default/0.chip_sw_usbdev_vbus.879486993			Jul 26 07:42:23 PM PDT 24	Jul 26 07:46:23 PM PDT 24	3451874538 ps
T748	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.1142296487			Jul 26 08:04:09 PM PDT 24	Jul 26 08:21:56 PM PDT 24	6910261992 ps
T36	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1401209542			Jul 26 07:44:31 PM PDT 24	Jul 26 07:51:02 PM PDT 24	5208975064 ps
T397	/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1408344156			Jul 26 07:44:26 PM PDT 24	Jul 26 07:48:26 PM PDT 24	2766831834 ps
T332	/workspace/coverage/default/25.chip_sw_all_escalation_resets.14143665			Jul 26 08:09:28 PM PDT 24	Jul 26 08:20:51 PM PDT 24	4747033800 ps
T949	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2990290690			Jul 26 08:01:06 PM PDT 24	Jul 26 08:04:50 PM PDT 24	2784490870 ps
T220	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2294317312			Jul 26 07:45:01 PM PDT 24	Jul 26 07:54:17 PM PDT 24	4703337817 ps
T357	/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3908841712			Jul 26 07:53:08 PM PDT 24	Jul 26 08:01:09 PM PDT 24	3576304408 ps
T282	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2744092157			Jul 26 07:48:35 PM PDT 24	Jul 26 07:50:40 PM PDT 24	2265877204 ps
T288	/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3835054670			Jul 26 08:07:33 PM PDT 24	Jul 26 08:23:08 PM PDT 24	5968872440 ps
T188	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3248248398			Jul 26 07:46:01 PM PDT 24	Jul 26 08:06:28 PM PDT 24	12458407692 ps
T950	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2418546407			Jul 26 08:04:17 PM PDT 24	Jul 26 08:29:35 PM PDT 24	8787380748 ps
T52	/workspace/coverage/default/2.chip_jtag_csr_rw.81228776			Jul 26 07:56:21 PM PDT 24	Jul 26 08:16:27 PM PDT 24	12180989917 ps
T430	/workspace/coverage/default/96.chip_sw_all_escalation_resets.2323323886			Jul 26 08:15:38 PM PDT 24	Jul 26 08:27:26 PM PDT 24	4676431856 ps
T431	/workspace/coverage/default/2.chip_sw_hmac_oneshot.3457705160			Jul 26 08:00:43 PM PDT 24	Jul 26 08:05:25 PM PDT 24	3578457848 ps
T432	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.290176214			Jul 26 08:12:26 PM PDT 24	Jul 26 08:21:03 PM PDT 24	3661551696 ps
T129	/workspace/coverage/default/0.chip_sw_edn_auto_mode.904702146			Jul 26 07:46:55 PM PDT 24	Jul 26 08:04:55 PM PDT 24	4382805400 ps
T433	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.1585406409			Jul 26 07:47:49 PM PDT 24	Jul 26 08:05:42 PM PDT 24	7131130148 ps
T97	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1325969167			Jul 26 07:51:39 PM PDT 24	Jul 26 08:21:43 PM PDT 24	26315470044 ps
T221	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3682124194			Jul 26 07:45:04 PM PDT 24	Jul 26 07:49:43 PM PDT 24	2678972006 ps
T434	/workspace/coverage/default/41.chip_sw_all_escalation_resets.3549973769			Jul 26 08:10:49 PM PDT 24	Jul 26 08:21:46 PM PDT 24	5489075790 ps
T435	/workspace/coverage/default/2.rom_keymgr_functest.3458560677			Jul 26 08:07:14 PM PDT 24	Jul 26 08:15:53 PM PDT 24	4937800538 ps
T126	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3036855912			Jul 26 08:04:14 PM PDT 24	Jul 26 08:16:21 PM PDT 24	4194871448 ps
T839	/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3115969473			Jul 26 08:10:05 PM PDT 24	Jul 26 08:16:21 PM PDT 24	3648397300 ps