Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	158174	1			T71	5		T72	104		T73	38
values[2]	4775	1			T71	1		T72	5		T73	1
values[3]	2299	1			T540	4		T455	1		T465	110
values[4]	1777	1			T540	6		T455	4		T465	89
values[5]	1328	1			T540	3		T455	7		T465	51
values[6]	1185	1			T540	11		T455	2		T465	34
values[7]	1086	1			T540	4		T455	1		T465	36
values[8]	908	1			T540	9		T455	3		T465	59
values[9]	854	1			T540	14		T455	4		T465	37
values[10]	760	1			T540	13		T455	2		T465	16
values[11]	651	1			T540	11		T455	2		T465	9
values[12]	490	1			T540	9		T455	1		T465	6
values[13]	477	1			T540	6		T455	2		T465	9
values[14]	497	1			T540	5		T455	2		T465	8
values[15]	462	1			T540	8		T455	1		T465	12
values[16]	465	1			T540	4		T455	2		T465	16
values[17]	473	1			T540	4		T455	2		T465	27
values[18]	473	1			T540	8		T455	2		T465	25
values[19]	472	1			T540	6		T455	2		T465	20
values[20]	412	1			T540	7		T455	5		T465	27
values[21]	341	1			T540	3		T455	3		T465	20
values[22]	241	1			T540	5		T455	1		T465	13
values[23]	202	1			T540	5		T455	1		T465	7
values[24]	198	1			T540	4		T455	3		T465	5
values[25]	241	1			T540	7		T455	4		T465	2
values[26]	202	1			T540	5		T455	2		T848	1
values[27]	211	1			T540	4		T455	4		T848	1
values[28]	202	1			T540	8		T455	7		T848	1
values[29]	186	1			T540	6		T455	6		T848	1
values[30]	162	1			T540	4		T455	1		T848	1
values[31]	166	1			T540	4		T455	3		T848	1
values[32]	174	1			T540	5		T455	4		T848	1
values[33]	174	1			T540	4		T455	2		T848	1
values[34]	140	1			T540	4		T455	1		T848	1
values[35]	131	1			T540	3		T455	1		T848	1
values[36]	150	1			T540	4		T455	4		T848	1
values[37]	154	1			T540	6		T455	3		T848	1
values[38]	125	1			T540	5		T455	1		T848	1
values[39]	143	1			T540	6		T455	1		T848	1
values[40]	122	1			T540	6		T455	1		T848	1
values[41]	94	1			T540	6		T455	2		T848	1
values[42]	122	1			T540	4		T455	3		T848	1
values[43]	99	1			T540	9		T455	1		T848	1
values[44]	101	1			T540	7		T455	3		T848	1
values[45]	80	1			T540	6		T455	3		T848	1
values[46]	52	1			T540	3		T455	7		T848	1
values[47]	49	1			T540	6		T455	5		T848	1
values[48]	48	1			T540	3		T455	3		T848	1
values[49]	44	1			T540	4		T455	1		T848	1
values[50]	45	1			T540	7		T455	2		T848	1
values[51]	49	1			T540	14		T455	1		T848	1
values[52]	53	1			T540	7		T455	4		T848	1
values[53]	52	1			T540	8		T455	1		T848	1
values[54]	40	1			T540	2		T455	2		T848	1
values[55]	43	1			T540	6		T455	2		T848	1
values[56]	47	1			T540	7		T455	3		T848	1
values[57]	54	1			T540	7		T455	3		T848	1
values[58]	44	1			T540	7		T455	2		T848	1
values[59]	48	1			T540	8		T455	4		T848	1
values[60]	39	1			T540	6		T455	2		T848	1
values[61]	45	1			T540	5		T455	1		T848	1
values[62]	34	1			T540	3		T455	2		T848	1
values[63]	42	1			T540	5		T455	5		T848	1
values[64]	48	1			T540	10		T455	1		T848	1
values[65]	44	1			T540	8		T455	2		T848	1
values[66]	46	1			T540	5		T455	1		T848	1
values[67]	42	1			T540	3		T455	1		T848	1
values[68]	56	1			T540	5		T455	3		T848	1
values[69]	51	1			T540	7		T455	6		T848	1
values[70]	58	1			T540	2		T455	1		T848	1
values[71]	53	1			T540	2		T455	2		T848	1
values[72]	49	1			T540	4		T455	1		T848	1
values[73]	51	1			T540	10		T455	2		T848	1
values[74]	48	1			T540	8		T455	2		T848	1
values[75]	61	1			T540	9		T455	3		T848	1
values[76]	71	1			T540	10		T455	4		T848	1
values[77]	55	1			T540	11		T455	1		T848	1
values[78]	52	1			T540	9		T455	1		T848	1
values[79]	52	1			T540	4		T455	2		T848	1
values[80]	61	1			T540	12		T455	1		T848	1
values[81]	58	1			T540	11		T455	6		T848	1
values[82]	56	1			T540	6		T455	8		T848	1
values[83]	61	1			T540	11		T455	5		T848	1
values[84]	52	1			T540	7		T455	2		T848	1
values[85]	71	1			T540	8		T455	5		T848	1
values[86]	67	1			T540	8		T455	2		T848	1
values[87]	53	1			T540	6		T455	1		T848	1
values[88]	58	1			T540	11		T455	6		T848	1
values[89]	63	1			T540	6		T455	7		T848	1
values[90]	68	1			T540	4		T455	1		T848	1
values[91]	64	1			T540	7		T455	4		T848	1
values[92]	63	1			T540	11		T455	5		T848	1
values[93]	63	1			T540	4		T455	2		T848	1
values[94]	63	1			T540	6		T455	3		T848	1
values[95]	58	1			T540	4		T455	2		T848	4
values[96]	57	1			T540	4		T455	2		T848	3
values[97]	66	1			T540	6		T455	4		T848	2
values[98]	68	1			T540	6		T455	5		T848	3
values[99]	58	1			T540	4		T455	1		T848	8
values[100]	71	1			T540	10		T455	3		T848	2
values[101]	66	1			T540	4		T455	3		T848	2
values[102]	77	1			T540	12		T455	2		T848	2
values[103]	67	1			T540	12		T455	2		T848	1
values[104]	86	1			T540	14		T455	4		T848	5
values[105]	59	1			T540	7		T455	2		T848	1
values[106]	77	1			T540	9		T455	4		T848	1
values[107]	68	1			T540	4		T455	7		T848	2
values[108]	69	1			T540	7		T455	6		T848	3
values[109]	77	1			T540	6		T455	3		T848	1
values[110]	85	1			T540	7		T455	3		T848	1
values[111]	84	1			T540	6		T455	3		T848	2
values[112]	66	1			T540	6		T455	1		T848	1
values[113]	83	1			T540	6		T455	2		T848	1
values[114]	80	1			T540	5		T455	4		T848	2
values[115]	88	1			T540	8		T455	3		T848	4
values[116]	68	1			T540	9		T455	8		T848	2
values[117]	90	1			T540	9		T455	6		T848	4
values[118]	67	1			T540	9		T455	4		T848	1
values[119]	75	1			T540	11		T455	6		T848	4
values[120]	70	1			T540	4		T455	4		T848	2
values[121]	86	1			T540	10		T455	13		T848	2
values[122]	92	1			T540	10		T455	15		T848	1
values[123]	112	1			T540	13		T455	10		T848	2
values[124]	190	1			T540	25		T455	17		T848	1
values[125]	354	1			T540	51		T455	41		T848	1
values[126]	623	1			T540	39		T455	58		T848	13
values[127]	2003	1			T540	31		T455	38		T848	148
values[128]	3199	1			T540	2		T455	4		T848	233